Patent classifications
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GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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TECHNICAL SUBJECTS COVERED BY FORMER USPC
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TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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257/00
Active solid-state devices, e.g. transistors, solid-state diodes
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Y10S257/906
Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
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Y10S257/906

Method of forming semiconductor device including protrusion type isolation layer
09741611 · 2017-08-22 · ·

A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion.

Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry
10943907 · 2021-03-09 · ·

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Integrated Circuitry Comprising An Array, Method Of Forming An Array, Method Of Forming DRAM Circuitry, And Method Used In The Fabrication Of Integrated Circuitry
20200266197 · 2020-08-20 · ·

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry
10707211 · 2020-07-07 · ·

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Integrated Circuitry Comprising An Array, Method Of Forming An Array, Method Of Forming DRAM Circuitry, And Method Used In The Fabrication Of Integrated Circuitry
20200098761 · 2020-03-26 · ·

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.