The single layer compressive substrate force sensor may include electrode patterns formed directly on a first side and second side of the compressive substrate. At least some of the electrode patterns are configured to provide a change in capacitance proportional with a compressive force applied to at least one of the electrode patterns, which compresses the compressive substrate. The single layer compressive substrate force sensor may include a first top electrode and a second top electrode pattern separated by an insulator to void contact between the electrode patterns. In operation, the first top electrode pattern and the second top electrode pattern are configured to provide projective capacitance, and thus provide detection of light touches or hover actions by an object.

A coating made of platinum-gold alloy is provided, together with a method of its preparation by electrodeposition. The alloy is composed of more than 50 atomic percent platinum. The microstructure of the alloy consists of generally ellipsoidal grains. More than half of the grains have a major axis of 10 nm or less.

Methods and systems for engineering a nanostructure are provided. An exemplary method includes creating at least one cytosine-cytosine and/or thymine-thymine mismatch in at least one oligonucleotide sequence, placing a metal ion into the mismatch of the oligonucleotide sequence to form an electronically functionalized nanostructure, and inducing self-assembly of the oligonucleotide sequence into a defined structure.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface, and wherein a second bump placement restriction specifies an allowed distance range between the bump and a qubit chip element in a layout of a second surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal between the first surface and the second surface and is positioned according to the set of bump placement restrictions.

The present invention relates to metal coatings and methods thereof. In certain embodiments, the invention relates to ultra-low wear noble metal alloys, such as for use in electrical contact coatings.