Patent classifications
Y10T29/42
RF acoustic wave resonators integrated with high electron mobility transistors including a shared piezoelectric/buffer layer and methods of forming the same
An RF integrated circuit device can includes a substrate and a High Electron Mobility Transistor (HEMT) device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to confine formation of a 2DEG channel region of the HEMT device. An RF piezoelectric resonator device can be on the substrate including the ScAlN layer sandwiched between a top electrode and a bottom electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.
Method of constructing a jaw member for an end effector assembly
An end effector assembly for use with an electrosurgical instrument is provided. The end effector assembly has a pair of opposing jaw members. One or more of the jaw members includes a support base, an electrical jaw lead, and a sealing plate coupled to the electrical jaw lead. The sealing plate has a stainless steel layer and one or more piezo electric sensors. The jaw member also includes an insulative plate disposed between the support base and the sealing plate.
Fully-wet via patterning method in piezoelectric sensor
Various embodiments of the present disclosure are directed towards a method for forming a piezoelectric device including a piezoelectric membrane and a plurality of conductive layers. The method includes forming the plurality of conductive layers in the piezoelectric membrane, the plurality of conductive layers are vertically offset one another. A masking layer is formed over the piezoelectric membrane. An etch process is performed according to the masking layer to concurrently expose an upper surface of each conductive layer in the plurality of conductive layers. A plurality of conductive vias are formed over the upper surface of the plurality of conductive layers.
Heterostructure and method of fabrication
The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
APPARATUS PROVIDING SIMPLIFIED ALIGNMENT OF OPTICAL FIBER IN PHOTONIC INTEGRATED CIRCUITS
A structure for optically aligning an optical fiber to a protonic device and method of fabrication of same. The structure optically aligns an optical fiber to the protonic device using a lens between the two which is moveable by actuator heads. The lens is moveable by respective motive sources associated with the actuator heads.
METHOD FOR PRODUCING PIEZOELECTRIC MULTI-LAYERED COMPONENTS
The present invention relates to a method for producing piezoelectric multi-layered components (2), which comprises the following steps: applying an electrode material (5) to green sheets (3) containing a piezoelectric material, applying a layer of a first auxiliary material (9) to at least one green sheet (3) containing the piezoelectric material, forming a stack (1), in which the green sheets (3), to which electrode material (5) is applied, are arranged one on top of another, wherein at least one ply of the green sheet (3), to which the layer of the first auxiliary material (9) is applied, is arranged in the stack (1), sintering the stack (1), wherein the layer of the first auxiliary material (9) is thinned, and firing the stack (1), wherein the stack (1) is singulated along the at least one ply into at least two multi-layered components (2).
Piezoelectric actuator
A piezoelectric actuator is disclosed that may include a insulating layer, individual electrodes, a common electrode, and a piezoelectric layer. The common electrode may include divisional electrodes that are connected with one another. The individual electrodes may be disposed between the insulating layer and the piezoelectric layer while the piezoelectric layer may be disposed between the individual electrodes and the common electrode. Further, the divisional electrodes may be configured to face the individual electrodes.
Method and device for real time estimation of the applied pressure and of noisiness in a brake element, in particular a brake pad
A brake element is sensorized by at least one piezoceramic sensor arranged between a metallic support element and a block of friction material of a brake element, the sensor being completely embedded within the block. An electrical voltage signal generated by at least one piezoceramic sensor, without the need for a power supply, is picked up by an electrical circuit integrated into the metallic support element. The electrical voltage signal is processed in the form of equal length of samples per unit of time of the detected signal by successively processing in real time each sample of equal length of time sample of the signal by applying an algorithm. The algorithm is selected from at least one of a sequence of integrations of voltage values in the sample carried out in an interval of time in the order of milliseconds; FFT voltage data sample; and integral of the voltage data sample.
Method for forming film bulk acoustic resonator
Methods for forming a film bulk acoustic resonator (FBAR) are provided. In the method, formation of several mutually overlapped and hence connected sacrificial material layers above and under a resonator sheet facilitates the removal of the sacrificial material layers. Cavities left after the removal overlap at a polygonal area with non-parallel sides. This reduces the likelihood of boundary reflections of transverse parasitic waves causing standing wave resonance in the FBAR, thereby enhancing its performance in parasitic wave crosstalk. Further, according to the disclosure, the FBAR is enabled to be integrated with CMOS circuitry and hence exhibits higher reliability.
Planarization method
The invention provides a planarization method, which can make the local flatness of the product to be processed more uniform. The product has a cavity filled with oxide and includes a first electrode layer, a piezoelectric layer and a second electrode layer superposed on the cavity. The first electrode layer covers the cavity and includes a first inclined face around the first electrode layer, and the piezoelectric layer covers the first electrode layer and is arranged on the first electrode layer. The planarization method includes: depositing a passivation layer on the second electrode layer and etching the passivation layer completely until the thickness of the passivation layer is reduced to the required thickness.