METHOD FOR PRODUCING A SEMI-CONDUCTOR ARRANGEMENT AND CORRESPONDING SEMI-CONDUCTOR ARRANGEMENT

Abstract

A method for producing a semiconductor arrangement, said method includes fastening a semiconductor on a base element by means of a sintered layer, wherein a side of the sintered layer which faces the base element is configured planar; and perforating a region of the base element, which directly contacts the sinter, wherein the perforating includes generating a plurality of through-openings having a closed border in the region of the base element for adjusting a stiffness of at least a portion of the base element in a targeted manner

Claims

1.-10. (canceled)

11. A method for producing a semiconductor arrangement, said method comprising: fastening a semiconductor on a base element by means of a sintered layer, wherein a side of the sintered layer which faces the base element is configured planar; and perforating a region of the base element, which directly contacts the sintered layer, said perforating comprising generating a plurality of through-openings having a closed border in the region of the base element for adjusting a stiffness of at least a portion of the base element in a targeted manner.

12. The method of claim 11, wherein the perforating is performed prior to the fastening of the semiconductor on the base element.

13. The method of claim 11, wherein the region of the base element comprises a planar surface, which is traversed by the plurality of through-openings and after the fastening of the semiconductor contacts the sintered layer.

14. The method of claim 13, wherein the base element has a further region which adjoins the planar surface and is angled with respect to the planar surface.

15. The method of claim 11, further comprising prior to the fastening step applying a contact layer on the semiconductor.

16. The method of claim 15, wherein the contact layer is a DCB-layer or an IMS-layer.

17. The method of claim 11, wherein the semiconductor is one of an IGBT, a diode and a MOSFET.

18. A semiconductor arrangement, comprising: at least one base element; and a semiconductor fastened on the base element by means of a sintered layer, wherein a side of the sintered layer which faces the base element is configured planar, and wherein a region of the base element which directly contacts the sintered layer has a plurality of through-openings with a closed border for adjusting a stiffness of at least a portion of the base element in a targeted manner.

Description

[0023] In the following the invention is explained in more detail by way of the exemplary embodiments shown in the drawing without limiting the invention. Hereby it is shown in

[0024] FIG. 1 a cross sectional view through a region of a semiconductor arrangement, which has a base element and a semiconductor fastened on the base element by means of a sintered layer, and

[0025] FIG. 2 a detail view of the base element.

[0026] FIG. 1 shows a cross sectional view of a semiconductor arrangement 1 with a base element 2 and a semiconductor 3, of which here only a section is shown. The semiconductor 3 is fastened on the base element 2 by means of a sintered layer 4. For this purpose the sintered layer 4 engages on one side directly on the base element 2 and on the other side directly on the contact layer 5, which is for example configured as a DCB-layer and thus has a copper layer 6 and a substrate layer 7. The substrate layer 7 is preferably made of Al.sub.2O.sub.3.

[0027] Besides the sintered layer 4 at least one further sintered layer, in the here shown exemplary embodiment two further sintered layers 8, can be provided. The sintered layer 8 directly contacts the base element 2 in a region 9 of the base element, wherein the base element 2 in this region has a planar surface 10. In the here shown view of the semiconductor arrangement 1 it can be seen that an angled region 11 of the base element 2 adjoins this planar surface 10. Preferably such a region 11 is present on each side of the surface 10.

[0028] As a result of the regions 11 indentations 12 are formed in the base element 2, with the base 13 of the indentations preferably being planar and extending parallel to the planar surface 10. On the side of the indentation 12 that faces away from the surface 10 or the substrate layer 7 a further planar surface 14 can be present. The surface 14 can be parallel to the surface 10 and/or be situated in the same imagined plane as the surface 10.

[0029] FIG. 2 shows a detail view of the base element 2. It can be seen that the base element 2 in the region 9, which is in direct contact with the sintered layer 4 (here not shown), is perforated at least in regions, i.e., it has at least one recess 15, in particular a plurality of recesses 15 of which here only one is exemplarily shown. Analogously, the surface 14 on which a sintered layer 8 can also be arranged, can also be provided with at least one such recess 15. Also here only some of the recesses 15 are exemplarily indicated. It can be seen that the recesses 15 are formed as through-openings and in cross section have a closed border and are circular. Of course the recesses 15 can also be configured as blind recesses and/or can have any other cross sectional configuration.

[0030] By means of the perforation of the region 9 and preferably also of the surface 14 the stiffness of the base element 2 can be reduced in regions thus facilitating elastic deformation of the base element 2 in the case of thermal tensions between the sintered layer 4 and the base element 2. In this way damage to the sintered layer 4 and/or the semiconductor 3 due to these thermal tensions is prevented or at least reduced.