Trench-gate RESURF semiconductor device and manufacturing method

Abstract

A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Claims

1. A method of manufacturing a trench-gate semiconductor device, comprising: forming a silicon substrate with an epitaxial layer doped with a first type of dopant, and which defines a device drift region; etching a gate trench into the substrate; forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench; implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant; depositing, doping and annealing a gate electrode in the gate trench; implanting and annealing a semiconductor body region on each side of the gate trench; implanting and annealing source regions on each side of the gate trench over the semiconductor body region; forming a second portion of gate oxide on top of the first portion of gate oxide; etching the semiconductor body region using the second portion of gate oxide as a mask to form a moat region at the sides of the source regions to form contact openings for contact with the source regions; implanting and annealing RESURF regions at a base of the moat, wherein the RESURF regions are formed on each side of the gate trench, doped with the second type of dopant of opposite polarity type to the first type of dopant, and extend more deeply into the drift region than the gate trench; and depositing and patterning a metallisation layer to form source and gate contacts, wherein the pillar region is beneath and in substantial contact with the gate trench and configured and arranged to act as an additional RESURF region and reduce the effective width of the drift region in an area between the RESURF regions and increase gate shielding, and wherein the pillar region is formed to a depth which is at least substantially equal to the depth of the RESURF regions.

2. A method as claimed in claim 1, wherein the pillar region is formed with a width of between 0.7 and 1.0 times the width of the gate trench.

3. A method as claimed in claim 1, wherein the first type of dopant is n-type and the second type of dopant is p-type.

4. A method as claimed in claim 1, further comprising forming an implant region of the second type of dopant at ends of the gate trench to couple the pillar region to the RESURF regions.

5. A method as claimed in claim 1, further comprising depositing and patterning a metallisation layer on the opposite side of the substrate to the source and gate contacts to form a drain contact.

6. A method as claimed in claim 1, further comprising forming an implant region connected to the source regions and to the pillar region to bias the pillar region at a potential of the source regions.

7. A method as claimed in claim 1, further comprising forming the RESURF regions with a silicon layer doped with the first type of dopant, and wherein the RESURF regions are configured to interact with the device drift region to deplete electrons in the device drift region and reduce an electric field that occurs within the device drift region.

8. A method as claimed in claim 1, wherein the contact openings provide access to a lateral portion of the source regions.

9. The method of claim 1, wherein the implanting the pillar region beneath the gate trench includes the use of implant energies ranging from 120 keV to 260 keV and occurs after the formation of the thicker gate oxide at the bottom of the trench.

10. The method of claim 9, wherein the implanting the pillar region beneath the gate trench uses Boron.

11. A method of manufacturing a trench-gate semiconductor device, comprising: forming a silicon substrate with an epitaxial layer doped with a first type of dopant, and which defines a device drift region; etching a gate trench into the substrate; forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench; implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant; depositing, doping and annealing a gate electrode in the gate trench; implanting and annealing a semiconductor body region on each side of the gate trench; implanting and annealing source regions on each side of the gate trench over the semiconductor body region; forming a second portion of gate oxide on top of the first portion of gate oxide; etching the semiconductor body region using the second portion of gate oxide as a mask to form a moat region at the sides of the source regions and contact openings for contact with the source regions; implanting and annealing RESURF regions at a base of the moat; depositing and patterning a metallisation layer to form source and gate contacts; forming an implant region of the second type of dopant at ends of the gate trench to couple the pillar region to the implanted and annealed RESURF regions, wherein the implant region is connected to the source regions and to the pillar region to bias the pillar region at a potential of the source regions, and wherein the pillar region beneath the gate trench is configured and arranged relative to the implanted and annealed RESURF regions to act as an additional RESURF region and reduce the effective width of the drift region between the implanted and annealed RESURF regions and increasing gate shielding.

12. A method of manufacturing a trench-gate semiconductor device, comprising: etching a gate trench into a silicon substrate having an epitaxial layer, the epitaxial layer being doped with a first type of dopant and defining a device drift region; forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench; implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant; forming a gate electrode in the gate trench, a semiconductor body region on each side of the gate trench, and source regions on each side of the gate trench over the semiconductor body region; forming a second portion of gate oxide on top of the first portion of gate oxide, a moat region at the sides of the source regions to form contact openings for contact with the source regions; implanting and annealing RESURF regions at a base of the moat; and forming a metallisation layer to form source and gate contacts, an implant region of the second type of dopant at ends of the gate trench to couple the pillar region to the RESURF regions, and causing the source regions to be connected to the pillar region in order to bias the pillar region at a potential of the source regions, wherein the pillar region implanted beneath the gate trench is configured and arranged with the RESURF regions to act as an additional RESURF region and reduce the effective width of the drift region and increase gate shielding.

Description

(1) An example of the invention will now be described in detail with reference to the accompanying drawings, in which:

(2) FIG. 1 shows a known vertical RESURF trench MOSFET;

(3) FIG. 2 shows graphically a relationship between the width of the epitaxial layer and the optimal doping level;

(4) FIG. 3 shows a vertical RESURF trench MOSFET of the invention;

(5) FIG. 4 shows the device of FIG. 3 in plan view;

(6) FIG. 5 shows simulation results to show the advantages of the invention; and

(7) FIG. 6 shows the effect of varying the depth of the additional trench in the design of the invention on the device characteristics.

(8) The invention provides an additional implant beneath the gate trench within a trench-gate MOS of the type described above. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

(9) FIG. 3 shows how the invention is used to modify the known structure of FIG. 1, i.e. with the same cell pitch of 1.5 μm but an additional p-type pillar 30 is implanted into the trench base after oxide growth.

(10) The additional pillar 30 is connected to the source bias, for example at the end of each trench stripe (or at regular intervals), where it merges with the high dose shallow (30 keV) p-type source region implant.

(11) FIG. 3 also shows the gate oxide regions 32 of the dielectric layer 1.

(12) The same reference numerals are used as in FIG. 1, and the structure is the same apart from the additional implant of the p-type polysilicon pillar 30.

(13) Multiple p-type implants, typically Boron, can be used for this purpose, and are implanted at energies ranging from 120 keV to 260 keV to form a pillar with the same depth as the p-type RESURF pillars 6 implanted into the moat region 7.

(14) Following the implants, the thermal budget is limited as much as possible to ensure that the lateral spread of the implanted Boron ions is minimised.

(15) To implement the invention, the process described above is changed in only one respect, in that after creation of the thick dielectric at the bottom of the gate trench, the p-type pillar 30, which functions as an additional RESURF region, is implanted.

(16) The process flow thus comprises:

(17) forming the silicon substrate with an epitaxial layer (5) doped with a first type of dopant (typically n-type), and which defines a device drift region;

(18) etching the gate trench into the substrate;

(19) forming the gate oxide around the inside of the trench, including the side walls of the trench where the gate dielectric 32 will be formed;

(20) forming a thicker gate oxide at the bottom of the trench;

(21) implanting the pillar region 30 of the invention beneath the gate trench, and doped with a second type of dopant of opposite type to the first type of dopant (i.e. typically p-type);

(22) depositing, doping and annealing the gate electrode 4 in the gate trench, followed by levelling;

(23) implanting and annealing a semiconductor body region 3 on each side of the gate trench;

(24) implanting and annealing the source regions 2 on each side of the gate trench over the semiconductor body region 3;

(25) forming the top contact part of the dielectric 1;

(26) etching the semiconductor body region 3 using the dielectric as a mask to form a moat region 7 at the sides of the source regions 2 to form contact openings for contact with the source regions 2;

(27) implanting and annealing the RESURF regions 6 at the base of the moat 7; and

(28) depositing and patterning metallisation layers to form source and gate contacts and a drain contact.

(29) The base of the drift region typically has a higher doping level to form a drain contact region adjacent the drain contact. This drain contact is formed at the end of the process, after thinning of the substrate layer. For example, 750 μm wafers can be processed, and then thinned to 150 μm prior to drain metallisation.

(30) The additional pillar 30 is connected to the source potential. For this purpose, an additional implant of the second type (typically p-type) is used to make contact between the additional deep pillar 30 and the source regions. This is achieved by providing the additional p-type implant at the end of each gate trench stripe, and this enables the additional p-type RESURF region to be biased at source potential.

(31) This additional p-type implant can be implanted at the beginning of the process to delineate the active area of the device from the edge termination. By providing the additional p-type implant all around the edge termination region, it provides connection across the underside of the trench, i.e. it makes lateral connection between the implants 30 and 6. The additional p-type implant thus extends under the trench.

(32) FIG. 4 shows the structure in plan view.

(33) Two gate trenches are shown, in which are formed the gate contacts 4. The source regions 2 (with the semiconductor body areas 3 and the drift regions 5 beneath) are on each side of each gate trench.

(34) The moat area 7 is laterally outside the source regions and the RESURF implant wells 6 are beneath the moat area 7.

(35) The gate trench is isolated by the gate dielectric so the gate is isolated from source potential. The additional implant 8 outside the active area connects the pillar 30 to the implant wells 6.

(36) In the structure of the invention, the width (W.sub.n) of the epitaxial layer between adjacent p-type RESURF pillars can be reduced to ˜0.3 μm.

(37) From Equation 1 and FIG. 2, this corresponds to an epitaxial doping (N.sub.n) of ˜1.5e17 cm.sup.−3 for the same value of BV. This level of RESURF can be achieved without having to sacrifice cell pitch and switching performance.

(38) FIG. 5 shows a summary of a simulation of the process of the invention. Transistor parameters are given for two known processes (“known1” and “known2”). The invention is implemented as a modification to the second known process, with two gate dielectric layer thicknesses (LS=33 nm and HS=38 nm). The LS 33 nm gate oxide corresponds to the Lowside transistor optimization and the HS corresponds 38 nm gate oxide corresponds to the Highside transistor optimization.

(39) The values specified in FIG. 5 are:

(40) RON at Vgs=4.5V is the on-state drain-source resistance of the device with an applied gate voltage of 4.5V;

(41) RON at Vgs=10V is the on-state drain-source resistance of the device with an applied gate voltage of 10V;

(42) BVdss is the breakdown voltage BV of the device when a drain voltage is applied relative to the source;

(43) Vgstx is the threshold voltage of the device when conducting 1 mA of drain current relative to the source;

(44) Qgd is the gate/drain charge;

(45) Qgs is the gate/source charge;

(46) Qgtot is the total charge of the MOSFET when a gate voltage of 4.5V is applied relative to the source;

(47) Qgd FoM is a figure of merit and is equal to Qgd×RON;

(48) Qgtot FoM is a figure of merit and is equal to Qgtot×RON.

(49) The performance of the thicker gate oxide version of the invention (HS) is then compared with the two known processes (“known1” and “known2”). Note that no substrate resistances have been added to the specific RON values.

(50) The advanced RESURF concept of the invention offers a marked improvement over the standard RESURF technology of FIG. 1 as well as the other test process. There is not just an improvement in the Figure of Merit but also in the actual Qgd and Qgtot (4.5 Vgs) parameter values. This can be contributed to the extra gate shielding afforded by the additional p-type pillar.

(51) FIG. 6 shows how the device performance varies with trench depth. The specific on resistance value Rspec (the RON value multiplied by the active area of the device) and the BV value are plotted. FIG. 5 shows that the concept works over the trench depth range. The envisioned trench depth window is 0.55 μm±0.1 μm.

(52) The processing parameters other than for the additional RESURF pillar have not been given in enormous detail, as these are all conventional and the same as employed in the structure of FIG. 1. The options will be apparent to those skilled in the art.

(53) Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.