Thin film capacitor, circuit board incorporating the same, and thin film capacitor manufacturing method

Abstract

Disclosed herein a thin film capacitor that includes a lower electrode layer, an upper electrode layer, and a dielectric layer disposed between the lower electrode layer and the upper electrode layer. The dielectric layer has a through hole. The upper electrode layer has a connection part connected to the lower electrode layer through the through hole and an electrode part insulated from the connection part by a slit. A surface of the lower electrode layer that contacts the connection part through the through hole includes an annular area positioned along an inner wall surface of the through hole and a center area surrounded by the annular area. The annular area is lower in surface roughness than the center area.

Claims

1. A thin film capacitor comprising: a lower electrode layer; an upper electrode layer; and a dielectric layer disposed between the lower electrode layer and the upper electrode layer, wherein the dielectric layer has a through hole, wherein the upper electrode layer has a connection part connected to the lower electrode layer through the through hole and an electrode part insulated from the connection part by a slit, wherein a surface of the lower electrode layer that contacts the connection part through the through hole includes an annular area positioned along an inner wall surface of the through hole and a center area surrounded by the annular area, and wherein the annular area is lower in surface roughness than the center area.

2. The thin film capacitor as claimed in claim 1, wherein the surface roughness of the annular area is 0.1 nm or more and 3 nm or less, and the surface roughness of the center area is larger than 3 nm and 50 nm or less.

3. The thin film capacitor as claimed in claim 1, wherein a width of the annular area is 0.1 μm or more and 10 μm or less.

4. The thin film capacitor as claimed in claim 1, wherein the lower electrode layer comprises Ni.

5. A circuit board incorporating a thin film capacitor, the thin film capacitor comprising: a lower electrode layer; an upper electrode layer; and a dielectric layer disposed between the lower electrode layer and the upper electrode layer, wherein the dielectric layer has a through hole, wherein the upper electrode layer has a connection part connected to the lower electrode layer through the through hole and an electrode part insulated from the connection part by a slit, wherein a surface of the lower electrode layer that contacts the connection part through the through hole includes an annular area positioned along an inner wall surface of the through hole and a center area surrounded by the annular area, and wherein the annular area is lower in surface roughness than the center area.

6. A method of manufacturing a thin film capacitor, the method comprising: forming a dielectric layer on a surface of a lower electrode layer; forming a through hole in the dielectric layer; forming an upper electrode layer on a surface of the dielectric layer; and forming a slit in the upper electrode layer to form a connection part connected to the lower electrode layer through the through hole and an electrode part insulated from the connection part by the slit, wherein the forming the through hole is performed by wet-etching such that an annular part, which constitutes a part of the surface of the lower electrode layer that is exposed to the through hole and positioned along an inner wall surface of the through hole is lower in surface roughness than a center area surrounded by the annular area.

7. The method of manufacturing a thin film capacitor as claimed in claim 6, wherein the forming the through hole includes: wet-etching the dielectric layer through a first mask having a diameter smaller than a diameter of the through hole to expose the center area; and wet-etching the dielectric layer through a second mask having a diameter larger than that of the first mask to expose the annular area.

8. The method of manufacturing a thin film capacitor as claimed in claim 6, wherein the forming the through hole is performed by wet etching the dielectric layer through a mask having a diameter smaller than a diameter of the through hole to expose the center area overlapping an opening of the mask and the annular area covered with the mask.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a schematic cross-sectional view for explaining the structure of a thin film capacitor 1 according to an embodiment of the present invention;

(3) FIG. 2 is a schematic cross-sectional view illustrating a contact portion between the connection part 22 and the lower electrode layer 10 in an enlarged manner;

(4) FIG. 3 is a schematic cross-sectional view of a circuit board 2 incorporating the thin film capacitor 1;

(5) FIG. 4 is an enlarged schematic cross-sectional view for explaining a process of embedding the thin film capacitor 1 in the circuit board 2;

(6) FIGS. 5 to 8 are process views for explaining a manufacturing method for the thin film capacitor 1;

(7) FIG. 9 is a plan view of the through hole 30b;

(8) FIGS. 10A and 10B are process views for explaining a first process of forming an annular area A1 and a center area A2;

(9) FIG. 11 is a process view for explaining a second process of forming the annular area A1 and the center area A2;

(10) FIG. 12A is a photograph of a sample including the actually formed through hole 30b; and

(11) FIG. 12B is an enlarged view of the sample.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(12) Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

(13) FIG. 1 is a schematic cross-sectional view for explaining the structure of a thin film capacitor 1 according to an embodiment of the present invention.

(14) As illustrated in FIG. 1, the thin film capacitor 1 according to the present embodiment includes a lower electrode layer 10, an upper electrode layer 20, and a dielectric layer 30 disposed between the lower electrode layer 10 and the upper electrode layer 20. The lower electrode layer 10 serves as a base for the thin film capacitor 1 and is made of, e.g., Ni (nickel). The reason that Ni is used as the material of the lower electrode layer 10 is that, as described later, the lower electrode layer 10 is used as a support body for the dielectric layer 30 in a process of baking the dielectric layer 30 and thus needs to have high temperature durability. The upper electrode layer 20 is made of, e.g., Cu (copper) and composed of a laminated film of a seed layer S and an electrolytic plating layer P.

(15) The dielectric layer 30 is formed using a perovskite dielectric material. Examples of the perovskite dielectric material include: a ferroelectric or dielectric material having a perovskite structure such as BaTiO.sub.3 (barium titanate), (Ba.sub.1-xS.sub.x)TiO.sub.3 (barium strontium titanate), (Ba.sub.1-XCa.sub.X)TiO.sub.3, PbTiO.sub.3, and Pb (Zr.sub.XTi.sub.1-X)O.sub.3; a complex perovskite relaxer ferroelectric material represented by, e.g., Pb (Mg.sub.1/3Nb.sub.2/3)O.sub.3; a bismuth layered compound represented by, e.g., Bi.sub.4Ti.sub.3O.sub.12 and SrBi.sub.2Ta.sub.2O.sub.9; and tungsten bronze ferroelectric material represented by, e.g., (Sr.sub.1-xBa.sub.x)Nb.sub.2O.sub.6 and PbNb.sub.2O.sub.6. Meanwhile, a ratio of A site and B site in the perovskite structure, perovskite relaxer ferroelectric material, bismuth layered compound, and tungsten bronze ferroelectric material is typically an integral ratio; however, it is allowable to intentionally depart the ratio from the integral ratio to improve the characteristics. An additive can be appropriately added to the dielectric layer 30 as an accessory component to control the characteristics of the dielectric layer 30. The thickness of the dielectric layer 30 is, e.g., 10 nm to 1000 nm.

(16) The upper electrode layer 20 has a ring-shaped slit SL formed therein and is divided thereby into an electrode part 21 and a connection part 22. The electrode part 21 functions as one capacitance electrode of the thin film capacitor 1 and faces, through the dielectric layer 30, the lower electrode layer 10 that functions as the other capacitance electrode of the thin film capacitor 1. The connection part 22 is connected to the lower electrode layer 10 through a through hole 30b formed in the dielectric layer 30 and thus has the same potential as the lower electrode layer 10. With this structure, electrical connection to the lower electrode layer 10 can be made from the upper electrode layer 20 side. In addition, since most part of the lower electrode layer 10 faces the electrode part 21 through the dielectric layer 30, a large capacitance can be obtained.

(17) FIG. 2 is a schematic cross-sectional view illustrating a contact portion between the connection part 22 and the lower electrode layer 10 in an enlarged manner.

(18) As illustrated in FIG. 2, the surface of the lower electrode layer 10 that contacts the connection part 22 through the through hole 30b includes an annular area A1 positioned along the inner wall surface (edge) of the through hole 30b and a center area A2 surrounded by the annular area A1. The annular area A1 has comparatively high flatness, while the center area A2 is roughened. That is, the annular area A1 is lower in surface roughness than the center area A2. Roughening the center area A2 enhances adhesion between the lower electrode layer 10 made of, e.g., Ni and the upper electrode layer 20 made of, e.g., Cu, and making the annular area A1 comparatively flat hardly causes local stress on the edge of the through hole 30b.

(19) FIG. 3 is a schematic cross-sectional view of a circuit board 2 incorporating the thin film capacitor 1 according to the present embodiment.

(20) In the circuit board 2 illustrated in FIG. 3, a plurality of insulating resin layers 41 to 43 are laminated, and the thin film capacitor 1 is embedded in the insulating resin layer 42. A semiconductor chip 50 is mounted on the upper surface of the circuit board 2. Further, the circuit board 2 is provided with power supply patterns 62V to 64V, ground patterns 62G to 64G, and signal patterns 62S to 64S. The power supply pattern 64V, ground pattern 64G, and signal pattern 64S each constitute an external terminal provided on the lower surface of the circuit board 2. The semiconductor chip 50, which is not particularly limited in type, has at least a power supply terminal 61V, a ground terminal 61G, and a signal terminal 61S. The terminals 61V, 61G, and 61S are connected to the power supply pattern 62V, ground pattern 62G, and signal pattern 62S, respectively.

(21) The power supply pattern 62V is connected to the power supply pattern 63V through a via conductor 65V. The power supply pattern 63V is connected to the power supply pattern 64V through a via conductor 66V and to the electrode part 21 of the thin film capacitor 1 through a via conductor 67V. The ground pattern 62G is connected to the ground pattern 63G through a via conductor 65G. The ground pattern 63G is connected to the ground pattern 64G through a via conductor 66G and to the connection part 22 of the thin film capacitor 1 through a via conductor 67G.

(22) With the above configuration, a power supply potential is given to one capacitance electrode (electrode part 21 of the upper electrode layer 20) of the thin film capacitor 1, and a ground potential is given to the other capacitance electrode (lower electrode layer 10), whereby a decoupling capacitor for the semiconductor chip 50 is constituted.

(23) The signal pattern 62S is connected to the signal pattern 63S through a via conductor 65S. The signal pattern 63S is connected to the signal pattern 64S through a via conductor 66S.

(24) The thin film capacitor 1 can be embedded in the circuit board 2 using a roll laminator. Specifically, as illustrated in FIG. 4, which is a schematic enlarged cross-sectional view, after formation of the insulating resin layer 41, the thin film capacitor 1 is laminated on the surface of the insulating resin layer 41 while rotating a roll 3. In mounting the thin film capacitor 1 using the roll laminator, a bending stress is applied to the thin film capacitor 1 at a portion where the weight of the roll 3 is applied. At this time, a highest stress is applied to an area denoted by symbol B, i.e., an area where the lower electrode layer 10, upper electrode layer 20, and dielectric layer 30 are in contact with one another, which may cause cracks or peeling in the dielectric layer 30 in some cases. Such a phenomenon is particularly noticeable when there is a large difference in Young's modulus between the lower electrode layer 10 and the upper electrode layer 20.

(25) However, in the thin film capacitor 1 according to the present embodiment, the surface roughness of the annular area A1 of the lower electrode layer 10 is reduced, which hardly allows generation of local stress concentration. Therefore, cracks or peeling is less liable to occur in the dielectric layer 30 in the process of embedding the thin film capacitor in the circuit board 2 and hence product reliability increases. Further, the center area A2 of the lower electrode layer 10 that is away from the inner wall surface of the through hole 30b is roughened, allowing enhancement of adhesion between the lower electrode layer 10 and the upper electrode layer 20.

(26) To prevent cracks or peeling in the dielectric layer 30, the surface roughness of the annular area A1 is preferably set to 0.1 nm or more and 3 nm or less, and the width thereof is preferably set to 0.1 μm or more and 10 μm or less. To sufficiently enhance adhesion between the lower electrode layer 10 and the upper electrode layer 20, the surface roughness of the center area A2 is preferably set to larger than 3 nm and 50 nm or less, and the area of the center area A2 is preferably larger than that of the annular area A1.

(27) The following describes a manufacturing method for the thin film capacitor 1 according to the present embodiment.

(28) FIGS. 5 to 10A and 10B are process views for explaining a manufacturing method for the thin film capacitor 1 according to the present embodiment.

(29) As illustrated in FIG. 5, the lower electrode layer 10 made of Ni and having a thickness of about 15 μm is prepared, and the dielectric layer 30 made of, e.g., barium titanate is formed on the surface of the lower electrode layer 10 and baked. Although the lower electrode layer 10 is subjected to high temperature at this time, it can endure the baking temperature due to being made of high-melting point metal such as Ni. Then, as illustrated in FIG. 6, the dielectric layer 30 is patterned to form the through hole 30b therein. The surface of the lower electrode layer 10 is exposed at the formation area of the through hole 30b.

(30) FIG. 9 is a plan view of the through hole 30b. In the example of FIG. 9, the through hole 30b has a circular planar shape, and the surface of the lower electrode layer 10 that is exposed through the through hole 30b includes the annular area A1 having a width of W and positioned along the inner wall surface of the through hole 30b and the center area A2 surrounded by the annular area A1. As described above, the annular area A1 is lower in surface roughness than the center area A2. There is no particular restriction on the method of forming the annular area A1 and center area A2 having such characteristics, and they can be formed as follows, for example.

(31) As illustrated in FIG. 10A, a mask R1 having an opening with a diameter of ϕ1 is formed on the surface of the dielectric layer 30, and then the dielectric layer 30 is wet-etched through the mask R1. The diameter ϕ1 of the opening of the mask R1 is designed smaller than the diameter of the through hole 30b to be finally formed. A usable etchant is a mixed solution of ammonium fluoride and hydrochloric acid. At this time, the composition and temperature of the etchant, etching time, a supply method of the etchant, and other conditions are adjusted so as to set the etching rate for the lower electrode layer 10 comparatively high. As a result, the surface of the lower electrode layer 10 that is exposed through the dielectric layer 30 has a high surface roughness. The part having a high surface roughness corresponds to the center area A2.

(32) Then, as illustrated in FIG. 10B, after removal of the mask R1, a mask R2 having an opening with a diameter of ϕ2 is formed on the surface of the dielectric layer 30, and the dielectric layer 30 is wet-etched once again through the mask R2. The diameter ϕ2 of the opening of the mask R2 is designed larger than the diameter ϕ1 of the opening of the mask R1 and substantially the same as or slightly smaller than the diameter of the through hole 30b to be finally formed. A usable etchant is a mixed solution of ammonium fluoride and hydrochloric acid. At this time, the composition and temperature of the etchant, etching time, a supply method of the etchant, and other conditions are adjusted so as to set the etching rate for the lower electrode layer 10 as low as possible. As a result, the surface of the lower electrode layer 10 that is newly exposed this time through the dielectric layer 30 has a low surface roughness. The part having a low surface roughness corresponds to the annular area A1.

(33) As described above, by performing the two-stage wet etching using the different masks R1 and R2, it is possible to reliably form the annular area A1 having a low surface roughness and the center area A2 having a high surface roughness.

(34) Alternatively, as illustrated in FIG. 11, a mask R3 having an opening with a diameter of ϕ3 is formed on the surface of the dielectric layer 30, and the dielectric layer 30 is wet-etched through the mask R3. The diameter ϕ3 of the opening of the mask R3 is designed smaller than the diameter of the through hole 30b to be finally formed. A usable etchant is a mixed solution of ammonium fluoride and hydrochloric acid. At this time, the composition and temperature of the etchant, a supply method of the etchant, and other conditions are adjusted so as to set the etching rate for the lower electrode layer 10 comparatively low and to set etching time long. Thus, side etching of the dielectric layer 30 progresses even at an area covered with the mask R3, making it possible to make the diameter of the through hole 30b larger than the diameter ϕ3 of the opening of the mask R3. Apart of the lower electrode layer 10 that overlaps the opening of the mask R3 is exposed to the etchant over a longer time period and thus becomes the center area A2 having a high surface roughness, while a part of the lower electrode layer 10 covered with the mask R3 is exposed to the enchant for a shorter time and thus becomes the annular area A1 having a low surface roughness.

(35) Thus, by side-etching the dielectric layer 30, it is possible to form the annular area A1 and the center area A2 by way of a less number of processes.

(36) FIG. 12A is a photograph of a sample including the actually formed through hole 30b, and FIG. 12B is an enlarged view of the sample. As illustrated in FIGS. 12A and 12B, the annular area A1, which constitutes a part of the surface of the lower electrode layer 10 and is positioned along the inner wall surface of the through hole 30b, is clearly lower in surface roughness than the center area A2.

(37) Then, as illustrated in FIG. 7, the upper electrode layer 20 is formed on the surface of the dielectric layer 30 including the through hole 30b. The upper electrode layer 20 can be obtained by forming the seed layer S in small thickness using sputtering or electroless plating and then by performing electrolytic plating using the seed layer S as a feeder. Thus, the upper electrode layer 20 composed of a laminated body of the thin seed layer S and thick electrolytic plating layer P is formed. Although the upper electrode layer 20 and the lower electrode layer 10 contact each other in the through hole 30b, sufficient adhesion is achieved between them since the surface of the lower electrode layer 10 has been roughened.

(38) Then, the lower electrode layer 10 is reduced in thickness to about 10 μm as illustrated in FIG. 8, and the upper electrode layer 20 is patterned to form the slit SL as illustrated in FIG. 1. As a result, the electrode part 21 and the connection part 22 are insulated and isolated from each other by the slit SL, whereby the thin film capacitor 1 according to the present embodiment illustrated in FIG. 1 is completed.

(39) As described above, in the present embodiment, wet-etching for forming the through hole 30b in the dielectric layer 30 is performed under the condition that the annular area A1, which constitutes a part of the surface of the lower electrode layer 10 that is exposed to the through hole 30b, is lower in surface roughness than the center area A2, so that it is possible to prevent cracks or peeling in the dielectric layer 30 which may occur at the mounting of the thin film capacitor 1 in the circuit board 2 while achieving sufficient adhesion between the lower electrode layer 10 and the upper electrode layer 20.

(40) It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.