POWER CONVERTER MONOLITHICALLY INTEGRATING TRANSISTORS, CARRIER, AND COMPONENTS

Abstract

A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

Claims

1. A power converter comprising: a semiconductor chip having a first and a parallel second surface, and through-silicon vias (TSVs) extending from the first to the second surface, the chip monolithically integrating an embedded high-side (HS) field-effect transistor (FET) and a low side (LS) FET together with the carrier, the transistors interconnected as a power converter; the first surface including first metallic pads as inlets of the TSVs, and an attachment site for an integrated circuit (IC) driver-and controller chip; the second surface including second metallic pads as outlets of the TSVs, and third metallic pads as terminals of the converter formed by the interconnected embedded HS FET and LS FET; and the IC chip attached to the site on the first surface, the terminals of the IC conductively connected to respective first pads.

2. The converter of claim 1 wherein the terminals of the IC are conductively attached to discrete metallic pads on the first surface, and the pads are connected by conductive surface traces to respective first pads.

3. The converter of claim 1 wherein the terminals of the IC are wire bonded to respective first pads, and the wires together with the IC chip are encapsulated in a packaging compound covering the first surface.

4. The converter of claim 1 wherein the third pads include a pad each for the inlet of the HS FET, the gate of the HS FET, the outlet of the LS FET, the gate of the LS FET, and for the common switch-node of the HS FET and LS FET.

5. The converter of claim 1 further including electronic components as thin film devices embedded in the semiconductor chip and connected to the FETs.

6. The converter of claim 5 wherein the thin film electronic components include a capacitor.

7. The converter of claim 1 further including on the first surface fourth metallic pads for attaching external electronic components.

8. The converter of claim 7 further including an external component attached to respective fourth pads.

9. The converter of claim 7 wherein the second, third, and fourth metallic pads have a solderable metallurgy.

10. A method for fabricating a power converter comprising: providing a semiconductor chip having a first and a parallel second surface, and through-silicon vias (TSVs) extending from the first to the second surface, the chip embedding monolithically a high-side (HS) field-effect transistor (FET) and a low side (LS) FET together with the carrier interconnected as a power converter, the first surface including first metallic pads as inlets of the TSVs and an attachment site for an integrated circuit (IC) driver- and controller chip, and the second surface including second metallic pads as outlets of the TSVs and third metallic pads as terminals of the converter formed by the HS FET and LS FET; and attaching the IC chip to the site on the first surface while conductively connecting the IC terminals to respective first pads.

11. The method of claim 10 wherein the process of attaching comprises the process of conductively attaching the terminals of the IC are to discrete metallic pads on the first surface while the pads are connected by conductive surface traces to respective first pads.

12. The method of claim 10 wherein the process of attaching comprises the process of wire bonding the terminals of the IC to respective first pads.

13. The method of claim 12 further including the process of encapsulating the wires together with the IC chip in a packaging compound covering the first surface.

14. The method of claim 10 wherein the third pads include a pad each for the inlet of the HS FET, the gate of the HS FET, the outlet of the LS FET, the gate of the LS FET, and for the common switch-node of the HS FET and LS FET.

15. The method of claim 10 further including electronic components as thin film devices embedded in the semiconductor chip and connected to the FETs.

16. The method of claim 10 wherein the semiconductor chip further includes fourth metallic pads on the first surface for attaching external electronic components.

17. The method of claim 16 further including the process of attaching an external component to respective fourth pads.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 depicts a circuit diagram of a power converter in accordance with various implementations.

[0012] FIG. 2 shows a perspective view of the top surface of an embodiment of the invention comprising a semiconductor monolith integrating a pair of transistors interconnected as a power converter, a plurality of through-silicon vias connected by surface traces to terminals of an integrated circuit chip, and a passive component.

[0013] FIG. 3 illustrates a perspective view of the bottom surface of the embodiment in FIG. 2.

[0014] FIG. 4 depicts a top perspective view of another embodiment of the invention.

[0015] FIG. 5 shows a diagram of the process flow of fabricating a converter monolithically integrating transistors, carrier and components.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] FIG. 1 shows the circuit diagram of a DC-DC power converter, or synchronous buck converter. A low-side (LS) field effect transistor (FET) 130 is coupled in series with a high-side (HS) FET 120 so that HS FET 120 has its drain 123 connected to the input voltage V.sub.IN (175) and its source 121 coupled to the drain 133 of the LS FET 130. The source 131 of FET 130 is at ground potential 176. The gate 122 of FET 120 and the gate 132 of transistor 130 are operated by a gate driver 150, which in turn is regulated by a controller (combined on the chip of 150). The common connection between drain 133 and source 121 operates as the switch V.sub.SW, designated 140. As mentioned, the HS FET is sometimes referred to as control FET, and the LS FET is sometimes referred to as sync FET.

[0017] In a DC-DC power supply circuit, common connection 140 is coupled to an inductor 170 serving as the energy storage of the power supply circuit; the inductor has to be large enough to reliably function for maintaining a constant output voltage V.sub.OUT (171). Output capacitor C.sub.OUT is designated 172. Additional components (such as input capacitor C.sub.IN and capacitor C.sub.VDD) may be employed. A pulse width modulated signal is provided to the PWM input of controller 150. The PWM input signal is used by controller 150 to control the voltage level of the output voltage V.sub.OUT so that the input voltage can be converted to the desired different output voltage.

[0018] FIG. 2 illustrates a perspective top view of an embodiment of the invention generally designated 100, and FIG. 3 shows the perspective bottom view of embodiment 100. In FIG. 2, semiconductor chip 101 has a first surface 101a, a parallel second surface 101b, and a plurality of through-silicon vias (TSVs) 110 extending from the first to the second surface. There are several known technologies to create TSVs. In one such fabrication method, holes of about 25 μm diameter and extending from the first to the second surface are etched into silicon. The sidewalls of the holes are coated with a dielectric layer (<1 μm thick) made of silicon dioxide, silicon nitride, or another suitable insulator. Then a thin seed metal layer (such as tantalum nitride) is deposited, before the hole is filled with copper or another metal of high electrical conductivity.

[0019] Chip 101 is a monolithic slab of single-crystal semiconductor (preferably silicon), which includes a heavily doped substrate semiconductor and a lightly doped epitaxial semiconductor. Chip 101 embeds a high-side (HS) field effect transistor and a low side (LS) FET, which are monolithically integrated, together with the carrier, in the single chip of single-crystalline semiconductor and electrically interconnected as a DC-DC power converter. First surface 101a may be covered by a thin layer 102, which may be a backmetal coating such as conductive metal like titanium-copper-titanium or titanium-nickel-silver-titanium, deposited by sputtering or evaporation; or layer 102 may be an insulating layer such as silicon nitride or silicon carbide.

[0020] One set of TSVs, designated 110a, connects the heavily doped semiconductor substrate of chip 101 underlying surface 101a to the parallel opposite surface 101b. FIG. 2 indicates two TSVs 110a; however, there may be multiple TSVs to route the substrate to the surface 101b in order to form on surface 101b the ground contact of the converter.

[0021] First surface 101a further includes one or more sets of first metallic pads suitable as attachment sites for bonding wires, solder compounds, or conductive polymeric compounds. FIG. 2 shows a set of first pads 111, which serves as inlets of the TSVs 110, and another set of first pads 113, which serves as attachment sites for an integrated circuit (IC) chip; in particular, pads 113 are configured to operate as attachment sites for the IC terminals of the driver-and controller chip 150. In the example of FIG. 2, chip 150 is flip-attached using solder balls.

[0022] In the embodiment of FIG. 2, the IC terminals of the driver-and-controller chip 150 are conductively attached to the discrete pads 113, and pads 113 are connected by conductive surface traces 112 to respective first pads 111. Conductive surface traces 112 are isolated from the layer 102 of backmetal or otherwise conductive substrate surface 101a, by a suitable insulating material such as a sufficiently thick layer of dielectric compound like silicon dioxide.

[0023] Surface 101a further includes a plurality of conductive surface traces 112, which are isolated from the layer 102 of backmetal or otherwise conductive substrate by insulating material such as a sufficiently layer of dielelctric or silicon dioxide. Traces 112 connect discrete metallic contact pads 113 to respective first pads 111, which are the inlets to the TSVs. Using the conductive vias, the terminals of the driver-and-control chip 150 are connected to second surface 101b of chip 101.

[0024] First surface 101a further includes a set of first metallic pads 114, referred to herein as fourth pads, which have a metallurgy suitable for attaching external electronic components by solder or a conductive adhesive. An example of an external electronic component is the capacitor 160 shown in FIG. 2.

[0025] FIG. 3 depicts a perspective view of the bottom surface 101b of chip 101. Included on surface 101b are metallic contact pads with a metallurgy suitable for attachment to a solder compound or a conductive adhesive compound. Among the pads are second metallic pads 115 as outlets of the TSVs 110, which originate on opposite parallel surface 101a, and pads 115 as outlets of the TSVs 110a.

[0026] Further among the pads are third metallic pads as the terminals of the converter formed by the interconnected embedded HS FET and LS FET. In actual devices, the HS and LS field effect transistors are realized as interdigitated source and drain structures and poly-silicon gate fingers. The gate contacts are gathered as gate busses. Collecting the finger structures and busses in to unified conductors enables the use of the singular terminals for the converter, as shown in FIG. 3. An example of the internal structure of interdigitated field effect transistors monolithically integrated into a power converter can be found in U.S. patent application Ser. No. 14/608391, filed Jan. 29, 2015 (Wang, Baiocchi, and Lin, “Monolithically Integrated Transistors for a Buck Converter Using Source Down MOSFET”).

[0027] The third pads of FIG. 3 include pad 123a of the drain 123 of the HS FET, which is to be tied to the input voltage V.sub.IN 175. Third pads further include pad 140a of the common connection V.sub.SW (switch node) 140, which is tied to the drain 133 of the LS FET as well as the source 121 of the HS FET. In addition, third pads include pad 131a of the source 131 of the LS FET, which is to be tied to ground 176. As stated above, pad 131a tied to ground potential is connected by multiple TSVs 110a to the opposite chip surface comprising heavily doped semiconductor substrate material.

[0028] Further included in the third pads are pad 122a of the gate bus for HS FET gate 122, and pad 132a of the gate bus for LS FET gate 132. As stated, pads 122a and 132a are the terminals of the gate busses.

[0029] It is a technical advantage that all terminals of the converter built by integrating a high-side FET and a low-side FET monolithically into a single silicon chip can be brought to a single surface with the help of TSVs, since in a board assembly process, these terminals can be attached to the board in a single step by using solder or a conductive adhesive. As a consequence, this simplified process not only saves time and cost, but also improves the thermal performance and speed of the converter by enhanced dissipation of operationally created heat.

[0030] FIG. 4 shows the top view of another embodiment of the invention generally designated 400. Semiconductor chip 401 has a first surface 401a, a parallel second surface 401b, and a plurality of TSVs 410 extending from the first to the second surface. The through-silicon vias have a diameter of about 25 μm, are metal-filled yet insulated from the semiconductor by a thin dielectric layer.

[0031] Chip 401 is a monolithic slab of single-crystal semiconductor (preferably silicon), which includes a heavily doped substrate semiconductor and a lightly doped epitaxial semiconductor. Chip 401 embeds a high-side (HS) field effect transistor and a low side (LS) FET, which are monolithically integrated in the single chip and interconnected as a DC-DC power converter. First surface 401a may be covered by a thin layer 402, which may be a backmetal coating such as conductive metal like titanium-copper-titanium or titanium-nickel-silver-titanium, deposited by sputtering or evaporation; or layer 402 may be an insulating layer such as silicon nitride or silicon carbide. In addition to TSVs 410, there are other TSVs, designated 410a, which are designed to connect the heavily doped semiconductor substrate of chip 401 directly under surface 401a to the parallel opposite surface 401b.

[0032] First surface 401a further includes first metallic pads suitable as attachment sites for bonding wires. FIG. 4 shows first pads 411, which serves as inlets of the TSVs 410. Pads 411 have a metallurgy suitable for forming reliable wire stitch bonds. Another pad 413 on surface 401a is suitable for attaching a semiconductor chip, preferably by conductive adhesive. In the embodiment of FIG. 4, the IC terminals of the driver-and-controller chip 150 are designed for wire ball bonding. As FIG. 4 shows, wire ball bonds 420 connect the chip terminals to the pads 411 as inlets to the TSVs 410.

[0033] For protection of the bonding wires, the wires and the first surface 401a are encapsulated in a packaging compound 470. The preferred encapsulation compound is an epoxy-based formulation and the preferred packaging technology is a molding process.

[0034] First surface 401a further includes a set of metallic pads 414, which have a metallurgy suitable for attaching external electronic components by solder or a conductive adhesive. An example of an external electronic component is the capacitor 460 shown in FIG. 4. On the other hand, electronic components may also be integrated into the circuitry embedded in the monolith 401 as thin film components; an example is a thin film capacitor.

[0035] It is a technical advantage that, in contrast to existing structures and methodologies, the monolithically integrated converter of FIGS. 2 and 3 does not have the physical package interconnects and intrinsic distances, which are prevalent in converters fabricated by existing technology. Clips and bonding wires and their associated parasitic resistances and inductances are avoided; other parasitic interconnects are at least reduced. Leadframes and molding compounds together with their time- and cost-intensive assembly and packaging processes are not needed.

[0036] The elimination of conventional converter parts without sacrificing their function also reduces the size of the converter and thus the space it consumes. As an example, size reduction enables the circuit loops between V.sub.IN and ground to be tighter, reducing the disturbing ringing phenomenon. In addition, the size reduction improves thermal dissipation from the converter to the board or to heat sinks. The improved thermal performance together with the reduced electrical parasitics increase converter performance, especially speed. Needless to state that the simplified assembly and packaging processes of the monolithically integrated converter reduce the high conventional converter manufacturing costs.

[0037] The method described above of fabricating a converter, which monolithically integrates transistors, carrier, and components, is summarized in the diagram of the process flow of FIG. 5. In process 501, a slab-like semiconductor chip is provided, which has a first and a parallel second surface, and a plurality of TSVs extending from the first to the second surface. The slab-like chip is embedding monolithically a high-side (HS) field-effect transistor (FET) and a low side (LS) FET together with their carrier; the transistors are interconnected as a power converter. The first surface of the slab-like chip includes first metallic pads as inlets of the TSVs, and further an attachment site for an integrated circuit (IC) driver-and-controller chip. The second surface of the slab-like chip includes second metallic pads as outlets of the TSVs, and further third metallic pads as terminals of the converter, which is formed by the HS FET and LS FET.

[0038] In process 502, the IC driver-and-controller chip is attached to the site on the first surface of the slab-like chip. When the IC chip is structured so that the IC terminals include solder balls, the IC chip is flipped and the solder balls attached to conductive traces leading to respective first metallic pads as inlets to the TSVs.

[0039] On the other hand, when the IC chip is structured so that the IC terminals require bonding wire connections, the IC chip is attached to the site on the first surface of the slab-like chip and then wires are spanned to respective first metallic pads as inlets to the TSVs. For protection of the wires, process 503 is needed to encapsulate the wires together with the IC chip in a packaging compound, which covers the first surface of the slab-like chip.

[0040] While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the invention applies not only to field effect transistors, but also to other suitable power transistors, to bipolar transistors, insulated gate transistors, thyristors, and others.

[0041] As another example, the above considerations for structure and fabrication method of power converters apply to regulators, multi-output power converters, applications with sensing terminals, applications with Kelvin terminals, and others.

[0042] It is therefore intended that the appended claims encompass any such modifications or embodiments.