Current generation architecture for an implantable stimulator device having coarse and fine current control

Abstract

A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

Claims

1. A method for producing stimulation using an implantable stimulator device (ISD), the ISD comprising a plurality of electrode nodes each configured to be electrically coupled to tissue to be stimulated; and a plurality of first stages, each first stage comprising a first current source configured to provide a first current, wherein each one of the first stages is controllable to source the first current in that first stage to any one of the plurality of electrode nodes, the method comprising: producing a first stimulation current at a first of the plurality of electrode nodes by controlling a first plurality of the first stages to source their first current to the first electrode node, whereby the first stimulation current is produced at the first electrode node as a sum of the first currents provided by the first plurality of the first stages.

2. The method of claim 1, wherein each of the first stages comprises switches, wherein each switch in each first stage is controllable to source the first current in that first stage to a different associated one of the electrode nodes, wherein the first stimulation current is produced at the first electrode node by closing the switch associated with the first electrode node in the first plurality of the first stages.

3. The method of claim 1, wherein the first currents are not adjustable.

4. The method of claim 1, further comprising converting a reference current into each of the first currents.

5. The method of claim 4, wherein the first currents comprise scalars of the reference current.

6. The method of claim 1, wherein the first currents are of equal magnitude in each of the first stages.

7. The method of claim 1, wherein a magnitude of the first currents varies across at least some of the first stages.

8. The method of claim 1, wherein the first current sources comprise current mirrors, wherein a scalar between a reference current and the first current in each first stage is set by a number of parallel output transistors in each current mirror.

9. The method of claim 1, wherein the ISD comprises N electrode nodes and L first stages.

10. The method of claim 9, wherein N equals L.

11. The method of claim 1, wherein a number of the first plurality of the first stages is less than L.

12. The method of claim 1, further comprising producing a second stimulation current at a second of the plurality of electrode nodes by controlling a second plurality of the first stages to source their first current to the second electrode node, whereby the second stimulation current is produced at the second electrode node as a sum of the first currents provided by the second plurality of the first stages.

13. The method of claim 12, wherein the first and second stimulation currents are produced at the same time.

14. The method of claim 1, wherein the ISD further comprises a plurality of second stages, each second stage comprising a second current source configured to source a second current only to a different associated one of the plurality of electrode nodes, wherein the method further comprises: controlling the second current source associated with the first electrode to produce the second current, whereby the first stimulation current is produced at the first electrode node as a sum of (i) the first currents provided by the first plurality of the first stages, and (ii) the second current produced by the second current source associated with the first electrode.

15. The method of claim 14, wherein a magnitude of the second currents is adjustable at each second current source.

16. The method of claim 14, further comprising converting a reference current into each of the second currents.

17. The method of claim 16, wherein the second currents comprise scalars of the reference current.

18. The method of claim 14, wherein the first currents are greater in magnitude than the second currents.

19. The method of claim 14, wherein the first and second current sources are coupled to a first power supply.

20. The method of claim 14, wherein the first current sources are coupled to a first power supply, and wherein the second current sources are coupled to a second power supply.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other aspects of the present invention will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings wherein:

(2) FIG. 1 shows an exemplary implantable pulse generator (IPG) and its associated electrode array in accordance with the prior art.

(3) FIG. 2 shows an exemplary prior art current source and a corresponding current sink for an IPG, each having current digital-to-analog converter (DAC) circuitry in series with a load.

(4) FIG. 3 shows a prior art architecture for coupling current sources and sinks to a plurality of electrodes using hard-wired dedicated circuitry at each electrode.

(5) FIG. 4 shows the layout complexity of one of the current sources of FIG. 3.

(6) FIG. 5 shows a prior art architecture for coupling current source and sinks to a plurality of electrodes using a switching matrix.

(7) FIG. 6 shows drawbacks relating to the architecture of FIG. 5 relating to unnecessary power consumption within the IPG.

(8) FIG. 7 shows a prior art modification to the architecture of FIGS. 3 and 4 in which a fractional amount of a reference current can be provided at an electrode.

(9) FIGS. 8A and 8B illustrates an improved current source/sink architecture having both coarse and fine current control in accordance with one embodiment of the invention.

(10) FIG. 9 shows the current mirror circuitry useable in the coarse circuitry portion of the architecture of FIGS. 8A and 8B.

(11) FIG. 10 shows the switch banks used in the coarse circuitry portion to distribute a coarse amount of current from any of the current mirrors to any of the electrodes.

(12) FIG. 11 shows the PDAC used in the fine circuitry portion of the architecture of FIGS. 8A and 8B which is dedicated at each electrode.

(13) FIGS. 12A and 12B illustrate an alternative embodiment to that shown in FIGS. 8A and 8B in which two different reference currents are used for the coarse and fine portions.

(14) FIG. 13 illustrates the control signals necessary to operate the disclosed embodiment of the current generation circuitry shown in FIGS. 8A and 8B.

(15) Corresponding reference characters indicate corresponding components throughout the several views of the drawings.

DETAILED DESCRIPTION

(16) The following description is of the best mode presently contemplated for carrying out the invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of describing the general principles of the invention. The scope of the invention should be determined with reference to the claims and their equivalents.

(17) At the outset, it is noted that the present invention may be used with an implantable pulse generator (IPG), or similar electrical stimulator and/or electrical sensor, that may be used as a component of numerous different types of stimulation systems. The description that follows relates to use of the invention within a spinal cord stimulation (SCS) system. However, it is to be understood that the invention is not so limited. Rather, the invention may be used with any type of implantable electrical circuitry that could benefit from efficient current source/sink circuitry. For example, the present invention may be used as part of a pacemaker, a defibrillator, a cochlear stimulator, a retinal stimulator, a stimulator configured to produce coordinated limb movement, a cortical and deep brain stimulator, or in any other neural stimulator configured to treat urinary incontinence, sleep apnea, shoulder sublaxation, etc.

(18) As noted earlier, exemplary embodiments of the present invention involve the architecture used in the current source and sink circuitry, which are sometimes respectively referred to as the PDAC and NDAC circuitry. Previous approaches were summarized in the Background section of this disclosure. But as noted, these architectures suffered from various drawbacks.

(19) A new and improved current generation architecture is illustrated in FIGS. 8-13. The new architecture, like previous architectures, employs current source and current sink circuitry, respectively labeled in FIGS. 8A and 8B as circuitry 400 and 401, which would logically be implemented for example on analog IC. As shown, the source circuitry 400 is in solid lines while the sink circuitry 401 is illustrated in mere dotted lines. However, the sink circuitry 401, while not specifically discussed, is similar in design and function to the source circuitry 400, although differing in polarity (e.g., connection to negative power supply V-, use of N-channel transistors, etc.). In other words, for simplicity, and to avoid redundancy, the source circuitry 400 is specifically discussed in this disclosure, although it should be understood that the sink circuitry 401 is similar in all material respects and of equal importance.

(20) As is unique to the new architecture, each of the source/sink circuitry 400/401 is divided into two parts: a coarse portion 402 (FIG. 8A) and a fine portion 403 (FIG. 8B). As its name suggests, the coarse portion 402 allows a coarse amount of current to be provided to a particular electrode. In other words, the amount of current which can be programmed to be source or sunk at a particular electrode by the coarse portion 402 is incrementable in relatively-large increments. By contrast, the amount of current which can be programmed to be sourced or sunk at a particular electrode by the fine portion 403 is incrementable in relatively-small increments. Having both coarse and fine portions 402 and 403 allows for efficient and dynamic control of the current at a particular electrode, as will be explained further below.

(21) Because they are different in their architecture and operation, the coarse and fine portions 402/403 of the current circuitry are separately discussed, with the coarse portion 402 discuss first.

(22) Unlike the prior art architecture of FIGS. 3 and 4, the coarse current circuitry 402 preferably does not involve dedicating or hard-wiring source and sink circuitry to each electrode E.sub.1 through E.sub.N on the IPG 100. Instead, the coarse portion 402 of the source and sink circuitry 400, 401 is shared or distributed amongst the various electrodes via a network of switch banks 405, as will be explained below.

(23) As shown, the source circuitry 400 comprises various current mirrors 410 and various switch banks 405. Specifically, there are L number of current mirrors 410 and switch banks 405. Each switch bank comprises N switches, which corresponds to the number of electrodes on the IPG 100. Thus, there are a total of N*L switches 417 in the switch banks 405, controlled by N*L control signals (C.sub.N,L). As shown in FIG. 10, the control signals to the switches 417 may need to be level shifted to DC values appropriate for the switches 417, which can easily occur via level shifters 415, as one skilled in the art will understand. The switches 417 are preferably single transistors of a logical polarity depending on whether they are present in the source circuitry 400 (P-channels) or the sink circuitry 401 (N-channels). However, other structures could also be used for the switches 417, such as pass gates or transmission gates, etc.

(24) The current mirrors 410 in the coarse portion 402 receive a reference current, I.sub.ref. Because it may be useful to set this reference current to a particular value, a PDAC 407 can be used to convert an initial reference current I.sub.1 to the true reference current I.sub.ref sent to each of the current mirrors 410. The PDAC 407 can comprise any structure known in the art for programming the amplification of a current on the basis of digital inputs. For example, the PDAC can be constructed as in FIG. 4. As shown, the PDAC 407 scales the initial reference current I.sub.1 by a factor of Z to produce the true reference current I.sub.ref. In this way, the currents ultimately sent to the electrodes can be further (and globally) varied by adjusting the gain of the PDAC 407. If smaller current resolutions are required in both the coarse and fine portions 402 and 403, Z can be reduced through appropriate digital control of the PDAC. If higher total currents are required, Z can likewise be increased. Additionally, because PDAC 407 is digitally controllable, it can be controlled to different values at different points in time. This being said however, PDAC 407 is not required in all embodiments of the invention, and the reference current I.sub.ref can be provided in different ways.

(25) The various current mirrors 410 take the reference current I.sub.ref and scale that current to produce currents of desired magnitudes in each of the L stages of the coarse portion 402. Thus, the first stage scales I.sub.ref by A.sub.1, the second by A.sub.2, and so on. The various scalars A.sub.1, A.sub.2, . . . A.sub.L, can be different or can be the same in each of the stages. For example the scalars can exponentially increase (A.sub.1=1, A.sub.2=2, A.sub.3=4, A.sub.4=8, etc.), or linearly increase (A.sub.1=1, A.sub.2=2, A.sub.3=3, etc.), or can stay the same. (In this sense, a current can be said to be “scaled” even if the scalar at the stage equals one).

(26) In an exemplary embodiment, each of the scalars A.sub.1 to A.sub.L are set to the same value of 5 and thus each of the L stages outputs the same amount of current (5 I.sub.ref) to their respective switch banks 405. To set this amount of gain at each of the L stages, five transistors 413 are placed in parallel with the balancing transistor 414 in the output stages of the current mirrors 410, as is shown in FIG. 9. However, it should be noted that current mirrors 410 are simply one example of a current converter, i.e., a circuit used to convert one current (I.sub.ref) to another current (A.sub.xI.sub.ref). Many other circuits capable of performing this function are known in the art, as thus the use of current mirrors in each stage should be understood as merely exemplary.

(27) In further distinction to the architecture of FIGS. 3 and 4, note that the current mirrors 410 in the coarse current circuitry 402 are not individually selectable in and of themselves, i.e., they do not have bit select transistors as in the DACs of FIGS. 3 and 4. They are always on and supplying current to the switch banks 405, with selection or not of a particular current mirror 410's current occurring in its given switch bank 405.

(28) As shown in FIGS. 8A and 10, and as noted previously, each of the L switch banks 405 contains N switches, SN, each of which is capable of routing the output current from its current mirror 410.sub.x (A.sub.xI.sub.ref) to any of the electrodes E.sub.X on the IPG 100, depending on the status of the coarse current control signals C.sub.N,L. Thus, in each stage X, control signal C.sub.Y,X can send that stage's current to E.sub.Y. In other words, each stage is controllable to send its output current to more than one of the electrodes and thus can affect the current at any given electrode, and multiple stages can work together to produce a current at a given electrode.

(29) For example, assume each current mirror 410 has a scalar A=5, such that each sends 5 I.sub.ref to its respective switch bank 405. Assume further that there are 19 stages, such that all current mirrors 410 together can supply a maximum current of 95 I.sub.ref. If a current of 50 I.sub.ref was desired at electrode E.sub.2, switches 417 could be closed in any 10 of the stages: the first 10 stages (C.sub.2,1 to C.sub.2,10); the last 10 stages, (C.sub.2,10 to C.sub.2,19); etc. Similarly, multiple electrodes can be stimulated at the same time. For example, suppose 50 I.sub.ref is desired at electrode E.sub.2; 10 I.sub.ref at electrode E.sub.5, and 15 I.sub.ref at electrode E.sub.8. This could be achieved by simultaneously activating the following coarse control signals: (C.sub.2,1 to C.sub.2,10), (C.sub.5,11 to C.sub.5,12), (C.sub.8,13 to C.sub.8,15). Of course, at some point the total amount of current that can be sourced from the source circuitry 400 (or sunk to the sink circuitry 401) at any given time will be dictated by the load that the compliance voltage V+ can handle.

(30) Not every stage L would necessarily require N switches. For example, a given stage might comprise less than N switches, foregoing the ability to send that stage's current to a particular electrode E.sub.X. Moreover, it is not necessary that every Xth switch in the switch banks 405 provide current to the Xth electrode, E.sub.X. In short, while FIG. 8A illustrates a preferred embodiment, other designs are possible that still achieve the benefits of the architecture disclosed herein.

(31) Because the gain in each of the current mirrors 410 in the exemplary embodiment is A=5, the minimum current resolution provided by any one of the L current mirrors 410 is 5 I.sub.ref, which can be considered as a coarse current resolution of the coarse portion 402 of the current source circuitry 400. Accordingly, to additionally provide the ability to make fine adjustments to the current provided at the electrodes, fine current source and sink circuitry 403 is also provided.

(32) As shown in FIG. 8B, and unlike the coarse portion 402, fine portion 403 is preferably hard-wired to each of the N electrodes. In this respect, the fine portion 403 is similar to architecture of FIGS. 3 and 4, which likewise used dedicated source and sink circuitry at each electrode. As noted in the discussion of the architecture of FIGS. 3 and 4, the use of dedicated source and sink circuitry at each electrode can be inefficient (guaranteed unused circuitry, etc.). However, any inefficiency in this regard is offset by the concurrent use of the coarse circuitry 402 to set the current at any given electrode, as will be explained below.

(33) In a preferred embodiment, and as shown in FIG. 8B, the fine portion 403 of the source circuitry 400 comprises a PDAC 409 at each electrode. (Additionally, each electrode will also preferably have a corresponding NDAC for sinking current, as shown in dotted lines in FIG. 8B, but not discussed for simplicity). Such PDACs 409 may be similar in design and architecture to the PDAC 407 used to set the reference current, I.sub.ref (see FIG. 8A), but again any current generation circuitry can be used.

(34) A preferred embodiment for the PDACs 409 used in the fine portion 403 of the source circuitry 400 is shown in FIG. 11. As can be seen both in FIGS. 8B and 11, each PDAC 409 receives the reference current from PDAC 407, I.sub.ref (see FIG. 8A), as well as fine current control signals (F.sub.J,N) used to set the amount of current output by each PDAC 409. As FIG. 11 shows, each PDAC 409 preferably constitutes a current mirror having a balancing transistor 424 and a plurality (J) of output transistors 422 (stages), each gated by one of J control signals (F.sub.1,X to F.sub.J,X). Each of the output transistors 422 are connected in parallel, and are allowed to contribute I.sub.ref (i.e., the input current) to the output current, depending on which of the selection transistors 431 are selected by fine current control signals F.sub.J,N.

(35) Because they are wired in parallel, the more fine current control signals enabled for any given stage, the higher the current output for that stage, which in effect sets the gain B for that stage. For example, if only F.sub.1,X is enabled for a given stage, then the current output from that stage equals I.sub.ref (i.e., B=1). If F.sub.1,X and F.sub.2,X are enabled, then the current output for stage (electrode) X equals 2 I.sub.ref (i.e, B=2), etc. In a preferred embodiment, J=4, such that there are four output transistors 431 in each stage, and therefore each stage (PDAC) 409 can output a maximum current of 4 I.sub.ref, which of course requires that all fine current control signals (i.e., F.sub.1,X thought F.sub.J,X) for a given stage (electrode) be activated. If necessary, level shifters 430 can be used to convert the fine control signals to appropriate levels to control the switches 431.

(36) In other words, depending on the status of the control signals F.sub.J,N for each electrode, a minimum of 0 I.sub.ref and a maximum of 4 I.sub.ref, in increments of I.sub.ref, can be sourced by the fine portion 403 of the current source circuitry 400 for any given electrode E.sub.X. (Again, the sink circuitry 401 would be similar). Note therefore that the fine portion 403 have a current resolution, I.sub.ref, which is smaller than the current resolution of the coarse portion 402, 5 I.sub.ref. Because of this different in resolution, both portions can be used simultaneously to set a particular current at a given electrode. For example, and returning to the example illustrated in the Background, assume that it is desired to source a current of 53 I.sub.ref at electrode E.sub.2. In such an embodiment, any ten of the current sources 410 can be activated via the coarse control signals corresponding to electrode E.sub.2 (C.sub.X,2) to provide 50 I.sub.ref to electrode E.sub.2. Likewise, any of three fine current control signals corresponding to electrode E.sub.2 (F.sub.X,2) can be activated to provide an additional 3 I.sub.ref worth of current in addition to the 50 I.sub.ref provided by the coarse portion, resulting in the desired total current of 53 I.sub.ref.

(37) Of course, the electrode-dedicated PDACs 409 can provide a fine current resolution using other designs, and the particular design of the PDACs is not critical to embodiments of the invention.

(38) As one skilled in the art will appreciate, it is a matter of design choice as to how many coarse stages L are used, and how many fine stages J are used, and these values may be subject to optimization. However, if it is assumed that J stages are used in the fine portion 403, then the number of stages L used in the coarse portion 402 is preferably equal to (100/(J+1))−1. Thus, if J equals 4, the number of stages L will be equal to 19, thereby allowing the coarse portion 402 to supply approximately 95% of the current range to any electrode E.sub.X with a resolution of approximately 5%. In this case, the fine portion 403 supplies approximately the remaining 5% of the current to any electrode E.sub.X at the higher resolution of approximately 1%. However, these values are merely exemplary.

(39) As shown in the Figures, it is preferred to use the same reference current, I.sub.ref, as the input to the current mirrors 410 in the coarse portion 402 and the PDACs 409 in the fine portion. However, this is not strictly necessary. For example, in FIGS. 12A and 12B, two PDACs 407c and 407f are used to respectively set different reference currents, I.sub.ref1 and I.sub.ref2, in the coarse and fine portions 402 and 403. By programming the PDACs 407c and 407f accordingly, these two reference currents can be a scalar of each other (i.e., I.sub.ref1=Q*I.sub.ref2). Assume that I.sub.ref1 is 5 times the value of I.sub.ref2 (Q=5). Assume further that only a single output transistor 413 (FIG. 9) is used in the current mirrors 410 in the coarse portion 402. Using these assumptions, the circuitry would operate as discussed earlier: each PDAC 409 in the fine portion 403 outputs a current with a fine resolution, I.sub.ref2, while each stage in the coarse portion 402 outputs a current with a coarse resolution, I.sub.ref1=5 I.sub.ref2. However, in such an embodiment, it would be necessary to isolate the coarse and fine portions 402 and 403 and to provide isolated compliance voltages (power supplies), V1+ and V2+, to each as shown.

(40) Several benefits are had with the new current source/sink architecture of FIGS. 8-13.

(41) First, by splitting the source 400 and sink 401 circuitry into coarse 402 and fine 403 portions, the number of control signals is reduced versus schemes which offer only a unified resolution. The control signals necessary to operate and control the disclosed current source/sink circuitry are shown in FIG. 13. Shown are the coarse (C.sub.N,L) and fine (F.sub.J,N) control signals for both the source circuitry (PDACs; designated with a “+”) and the sink circuitry (NDACs; designated with a “-”). These control signals are ultimately generated by a microcontroller 570, which can be the microcontroller otherwise used to implement the logic functions in the IPG. Alternatively, the current source/sink circuitry can be implemented on an analog integrated circuit, which receives the control signals from a digital integrated circuit. Again, the specific details concerning the integration of the current source/sink circuitry with the logic can occur in any number of ways, as one skilled in the art will readily recognize.

(42) Second, and unlike the prior art architectures discussed earlier, circuitry is kept to a minimum through reduction of the use of dedicated circuitry which otherwise might be guaranteed to go unused at particular points in time. In large part, this benefit is the result of the distributed nature of the coarse portion 402 of the circuitry across all of the electrodes. While the disclosed design does rely on the use of some dedicated circuitry—specifically, the fine portion 403—such circuitry is preferably kept to a minimum. In any event, such additional dedicated circuitry amounts to a good trade off when it is recognized that this reduces the number of necessary control signals.

(43) Third, as compared to the prior art switch matrix approach of FIGS. 5 and 6, the new architectures of FIGS. 8-12 comprise one less component in the output path, which reduces unwanted voltage drops in the output path and results in power savings. As can be seen with brief reference to FIGS. 9 and 10, which shows the circuitry in the coarse portion 402, only two components intervene between the power supply V+ and a given electrode: the current mirror output transistor(s) 413 and the selection switches 417 from the switch banks 405. Moreover, as concerns the fine portion 403, shown in FIG. 11, again only two components intervene between the power supply V+ and a given electrode: the current mirror output transistors 422 and the selection switches 431. In addition to reducing the series resistance in the circuit by eliminating the series switch matrix, the selection switches 417 linearize the current sources 410 by reducing the Vds voltage drop across the current mirrors on electrodes that require less compliance voltage than the difference of V+ to V−. If it were not for the switches 417, the entire excess compliance drop would be across the current mirror 410 and the current would tend to be a little higher than programmed on electrodes requiring less compliance voltage.

(44) It should be understood that the direction in which current flows is a relative concept, and different conventions can be used to define whether currents flow to or from various sources. In this regard, arrows showing the directions of current flows in the Figures, references to current flowing to or form various circuit nodes, references to currents being sunk or sourced, etc., should all be understood as relative and not in any limiting sense.

(45) It should also be understood that reference to an electrode implantable adjacent to tissue to be stimulated includes electrodes on the implantable stimulator device, or associated electrode leads, or any other structure for stimulating tissue.

(46) Moreover, it should be understood that an electrode implantable adjacent to tissue to be stimulated is to be understood without regard to any output capacitance, such as coupling capacitances C.sub.N included in the header connector 192 or elsewhere (see FIG. 7). This is so because it should be understood that nodes on both sides of such a coupling capacitor or other output impedance are, in the context of this invention, not materially different from an architectural standpoint, such that either node would be considered as the electrode node implantable adjacent to tissue to be stimulated. The same would be true for other impedances, e.g., if an output resistor was used in addition to or in lieu of a coupling capacitor.

(47) While the invention herein disclosed has been described by means of specific embodiments and applications thereof, numerous modifications and variations could be made thereto by those skilled in the art without departing from the literal and equivalent scope of the invention set forth in the claims.