Weak power supply operation and control

Abstract

Power monitoring circuitry is provided, comprising a capacitor configured to receive a current, so as to charge the capacitor and a switching device, connected to the capacitor. The switching device is configured to periodically discharge the capacitor in response to receipt of a clock signal from a circuit being monitored. The power monitoring circuitry also comprises a comparator, configured to perform a comparison of a voltage developed by the capacitor with a threshold voltage, and to output an indication of a change in power supplied to the circuit in response to the comparison. Other embodiments are also described.

Claims

1. Apparatus comprising: a power supply; and power monitoring circuitry, configured to monitor the power supply, and comprising: a clock configured to generate a clock signal using power supplied by the power supply; a capacitor configured to receive a current, so as to charge the capacitor; a switching device, connected to the capacitor, configured to discharge the capacitor at fixed time intervals in response to receipt of the clock signal; and a comparator, configured (a) to perform the monitoring of the power supply by performing a comparison of a voltage developed by the capacitor with a threshold voltage, and (b) to output an indication of a reduction in power supplied by the power supply when the switching device ceases to discharge the capacitor at the fixed time intervals due to the reduction in power.

2. The circuitry according to claim 1, wherein the current comprises a fixed charging current, and wherein the circuitry comprises a constant current generator supplying the fixed charging current.

3. The circuitry according to claim 1, wherein the threshold voltage is determined in response to a level attained by the capacitor if the capacitor is not discharged.

4. The circuitry according to claim 1, wherein the comparator is configured to output the indication if a voltage of the power supply is less than a lower threshold.

5. The circuitry according to claim 4, wherein the comparator is configured to output the indication if the voltage of the power supply is less than the lower threshold, the lower threshold being less than 1.5 volts.

6. The circuitry according to claim 5, wherein the comparator is configured to output the indication if the voltage of the power supply is less than the lower threshold, the lower threshold being between 0.2 volts and 0.6 volts.

7. A method for monitoring a power supply, the method comprising: configuring a capacitor to receive a current, so as to charge the capacitor; discharging the capacitor at fixed time intervals in response to receipt of a clock signal from a clock that uses power supplied by the power supply; and performing a comparison of a voltage developed by the capacitor with a threshold voltage, and outputting an indication of a reduction in power supplied by the power supply in response to a ceasing of the discharging of the capacitor at the fixed time intervals due to the reduction in power.

8. The method according to claim 7, wherein the current comprises a fixed charging current supplied by a constant current generator.

9. The method according to claim 7, wherein the threshold voltage is determined in response to a level attained by the capacitor if the capacitor is not discharged.

10. The method according to claim 7, wherein outputting the indication comprises outputting the indication if a voltage of the power supply is less than a lower threshold.

11. The method according to claim 10, wherein outputting the indication comprises outputting the indication if the voltage of the power supply is less than the lower threshold, the lower threshold being less than 1.5 volts.

12. The method according to claim 11, wherein outputting the indication comprises outputting the indication if the voltage of the power supply is less than the lower threshold, the lower threshold being between 0.2 volts and 0.6 volts.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a schematic, pictorial illustration of a retinal prosthesis implanted in an eye, according to an embodiment of the present invention;

(2) FIG. 1B is a schematic number line illustrating different voltage ranges for an element in the retinal prosthesis, according to an embodiment of the present invention;

(3) FIG. 2A is a block diagram that schematically illustrates conversion circuitry, according to an embodiment of the present invention;

(4) FIG. 2B is a schematic graph of the performance of a current to frequency converter, according to an embodiment of the present invention;

(5) FIG. 3 is a block diagram that schematically illustrates alternative conversion circuitry, according to an embodiment of the present invention;

(6) FIG. 4A is a block diagram that schematically illustrates further alternative conversion circuitry, according to an embodiment of the present invention;

(7) FIGS. 4B and 4C are graphs illustrating the operation of the circuitry of FIG. 4A, according to embodiments of the present invention;

(8) FIG. 5 is a block diagram that schematically illustrates yet further alternative conversion circuitry, according to an embodiment of the present invention;

(9) FIG. 6A is a block diagram that schematically illustrates disclosed conversion circuitry, according to an embodiment of the present invention;

(10) FIG. 6B illustrates examples of voltage vs. time graphs of pulses used by the circuitry of FIG. 6A, according to an embodiment of the present invention;

(11) FIG. 7 is a block diagram that schematically illustrates alternative disclosed conversion circuitry, according to an embodiment of the present invention;

(12) FIG. 8 is a schematic circuit diagram of a memory, according to an embodiment of the present invention; and

(13) FIG. 9 is a schematic block diagram of data loading circuitry, according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

(14) An embodiment of the present invention comprises a power supply which is configured to deliver low amounts of electrical energy. The power supply, unless it is recharged by receiving energy from an external source, is only able to deliver the energy for short periods of time. Such a power supply is herein also termed a weak power supply. A typical weak power supply is able to deliver of the order of microwatts up to a few watts, and the voltage might drop within a fraction of a second when the external source is halted. Alternatively, a weak power supply may be characterized by unstable behavior, wherein it changes from delivering full power to delivering no power, or vice versa, within a fraction of a second. In addition to comprising a weak power supply, the embodiments described herein comprise circuitry which is able to detect when the weak power supply is unable to supply a required power level, typically when a parameter of the weak power supply is beyond a specified range of values for the parameter. The embodiments also describe different sets of apparatus which provide “graceful” solutions for handling conditions when the weak power supply is in such a “beyond-specified-range” state. Typically, the weak power supply is used in place of a battery, and the supply may derive its energy from energy harvesting elements or remote power transfer elements, such as coils which convert alternating magnetic fields to electrical signals. The weak power supply provides energy to a device which is typically an implantable medical device.

(15) By way of example, in the following description the weak power supply is assumed to be used to power a retinal prosthesis, and the sets of apparatus providing the solutions when the power supply is in a beyond-specified-range state are assumed to be configured for a retinal prosthesis. However, use of a retinal prosthesis in the description is purely exemplary, and those having ordinary skill in the art will be able to adapt the description, mutatis mutandis, for other devices using a weak power supply, such as a cochlear prosthesis or a pacemaker.

System Description

Detection of Power Supply Out of Specification

(16) Reference is now made to FIG. 1A, which is a schematic, pictorial illustration of a retinal prosthesis 20 implanted in an eye 22, according to an embodiment of the present invention. In the pictured embodiment, which schematically illustrates a horizontal cross-section of eye 22, prosthesis 20 is implanted epiretinally, typically in proximity to an optic nerve 21, and the rear side of the prosthesis comprises an array of electrodes 26, which protrude into or otherwise contact retinal tissue 24.

(17) Alternatively, prosthesis 20 may be implanted subretinally.

(18) The front side of prosthesis 20 comprises an array 28 of light-sensing elements 30, typically photodiodes, which output signals in response to light that is focused onto them by optical elements of the eye, such as a lens 23. Retinal prosthesis components similar to those described herein, as well as other retinal prosthesis components, are described, for example, in PCT International Publication WO 2010/089739 and in U.S. patent application Ser. No. 12/852,218 (issued as U.S. Pat. No. 8,428,740), whose disclosures are incorporated herein by reference.

(19) Within prosthesis 20 conversion circuitry 32 receives and processes the output signals from elements in order to generate pulses to drive electrodes 26. The circuitry typically comprises a number of generally similar channels 34, each channel 34 receiving the signal from one element 30, and driving one electrode 26. Each channel 34 uses a set 36 of circuit elements, and in the following description, where necessary, the elements of a given channel 34 and its component elements are differentiated from each other by appending a letter and/or a numeral to the channel and to the set identifying numeral. For example, in a first embodiment a given channel 34M may comprise a set 36M of elements, the set in turn comprising a trans-impedance amplifier (TIA) 36M1, a voltage to frequency converter (V2F) 36M2, and an electrode driver 36M3. In a second embodiment, a given channel 34N comprises a set of elements 36N, the set comprising a current to frequency (I2F) converter 36N1 and an electrode driver 36N2.

(20) Functionality and properties of circuitry similar to circuitry 32 and its component elements are described in US patent application Ser. No. 13/034,516 filed Feb. 24, 2011(issued as U.S. Pat. No. 8,571,669), which is incorporated herein by reference. As described therein, the frequency of the pulses driving electrodes similar to electrodes 26 varies from a minimum frequency typically less than 10 Hz to a maximum frequency in the order of tens or hundreds of Hz.

(21) Elements of prosthesis 20, including array 28 and circuitry 32, are powered by a weak power supply 38, which by way of example is assumed to be incorporated into circuitry 32. A typical weak power supply is able to deliver up to hundreds of microwatts, and the voltage might drop within a fraction of a second when an external energy source is halted. Alternatively, a weak power supply may be characterized by unstable behavior, wherein it changes from delivering full power to delivering no power, or vice versa, within a fraction of a second. Such unstable behavior occurs, for example, for a power supply used in an eye that harvests light energy incident on the eye. Blinking and eye motion, for example, cause rapid reduction and return in the energy harvested.

(22) Because of dimensional constraints on prosthesis 20, power supply 38 is usually small, and, unless it is recharged, the power supply may only be able to deliver a small amount of power to the prosthesis elements for a relatively short time. One suitable power supply, comprising an energy receiver and a voltage regulator, is described in PCT Application WO 2010/089739 referenced above. However, embodiments of the present invention may use any other suitable weak power supply, and such other supplies will be apparent to those having ordinary skill in the art.

(23) Typically, circuitry 32 together with power supply 38 comprise one or more semiconductor chips, in which analog and/or digital circuit elements are fabricated, using methods of integrated circuit production that are known in the art. Alternatively, circuitry 32 may be fabricated at least partially using discrete circuit components, rather than integrated circuits. Array 28 of light-sensing elements 30 may be integrated into the same chip (or chips) as circuitry 32. Alternatively, array 28 may be fabricated on a separate substrate, and elements 30 may be coupled to the processing channels of circuitry 32 using methods that are known in the art.

(24) The elements of prosthesis 20, including elements of sets 36, typically operate correctly only when the voltage supplying a given element is within an operating voltage range specified for the element. The operating voltage range for a particular element depends on the type of element, and different types of elements may be more or less constrained as to their operating voltages. For example, the specification for a digital device may provide for a relatively wide operating voltage range, whereas the specification for an analog device may indicate that the operation of the device may degrade significantly outside a relatively narrow operating range. In addition, the valid operating range for any particular device may be a function of how the device is implemented and/or of the function being performed by the device. For example, a digital logic device using CMOS (complementary metal-oxide-semiconductor) technology typically has a wider operating voltage range than an analog circuit.

(25) FIG. 1B is a schematic number line 40 illustrating different voltage ranges for an element in prosthesis 20, according to an embodiment of the present invention. Number line 40 plots the element supply voltage, i.e., the voltage between the two voltage rails supplying electrical power to the element. On receipt of an appropriate voltage level, typically a few tenths of a volt, the element is configured to perform according to a prescribed specification. A lowest voltage V.sub.ABSMIN is a low voltage below which the element performs none of the functions of the specification. A highest voltage V.sub.ABSMAX is a high voltage above which the element also performs none of the functions. (Subjecting the element to voltages above V.sub.ABSMAX may irreversibly damage the element, while subjecting the element to voltages below V.sub.ABSMIN typically causes no permanent damage.)

(26) Within a voltage range R1, between V.sub.ABSMIN and V.sub.ABSMAX is a smaller voltage range R2, between a lower voltage V.sub.MIN and a higher voltage V.sub.MAX. In range R2 the element is able to correctly operate according to the specification of the element. In the description herein, if an element is not within its range R2, it may be referred to as being out of specification.

(27) Two further ranges may be considered for the element: a range R3 between V.sub.ABSMIN and V.sub.MIN, and a range R4 between V.sub.MAX and V.sub.ABSMAX. Within ranges R3 and R4 the element typically operates partially according to the element specification. For an analog device the partial operation may typically be manifested as a reduced dynamic range and/or introduction of distortion and/or clipping into the output of the device. For a digital device the partial operation may manifest itself as unstable signals. In some cases, range R4 does not exist, since the R2 range is defined up to the maximum supplied voltage V.sub.ABSMAX.

(28) It will be understood that for any given element the range bounds described above, V.sub.ABSMIN, V.sub.ABSMAX, V.sub.MIN and V.sub.MAX, may be adaptive, i.e., they may depend on a number of parameters applicable to the element. The parameters include, but are not limited to, a temperature at which the element is operating, an impedance of a component driving the element, and an impedance of a component being driven by the element. The parameters also include functions required of the element, such as whether the element is quiescent, is providing a clock signal of a given frequency, or is amplifying an incoming signal. Other adaptive parameters affecting the range bounds will be apparent to those having ordinary skill in the art, and all such parameters are included in the scope of the present invention.

(29) Embodiments of the present invention detect if an element is within partial operating ranges such as those described above, e.g., within ranges R3 or R4. The embodiments also provide solutions for handling the reduced operating characteristics of an element when it is within such partial operating ranges.

(30) A typical range for V.sub.ABSMIN is approximately 0.05V to approximately 0.3V; a typical range for V.sub.MIN is approximately 0.2V to approximately 0.7V; and a typical range for V.sub.MAX is approximately 0.7V to approximately 1.5V. V.sub.ABSMAX is greater than or equal to the respective value of V.sub.MAX, and is bounded by the limitations of the voltage of the devices of the selected process technology. In a first disclosed embodiment values of V.sub.ABSMIN, V.sub.MIN, and V.sub.MAX are respectively approximately equal to 0.2V, 0.4V, and 1.5V; in a second disclosed embodiment V.sub.ABSMIN, V.sub.MIN, and V.sub.MAX are respectively approximately equal to 0.1V, 0.7V, and 1.1V, and in a third disclosed embodiment values of V.sub.ABSMIN, V.sub.MIN, and V.sub.MAX are respectively approximately equal to 0.1V, 0.4V, and 1.5V. Other sets of values of V.sub.ABSMIN, V.sub.MIN, and V.sub.MAX will be apparent to those having ordinary skill in the art, and all such sets are assumed to be within the scope of the present invention.

(31) The description above referring to detecting if an element is within a partial operating range, and providing solutions for such cases, may be applied, mutatis mutandis, to a group of such elements, or to a device comprising a number of separate elements, such as prosthesis 20 or power supply 38. All such applications are considered to be within the scope of the present invention.

(32) FIG. 2A is a block diagram that schematically illustrates conversion circuitry 32, according to an embodiment of the present invention. Conversion circuitry comprises channels 34, each given channel 34A comprising an I2F converter 36A1. A processing unit (PU) controls the operation of channels 34, and the combination of PU 60 and channels 34 is also referred to herein as operating circuitry 62. Power supply 38 supplies power to operating circuitry 62.

(33) Conversion circuitry 32 comprises a power supply monitoring circuit 64, which is itself powered by power supply 38 and which monitors the voltage difference between a power rail 66, supplying a voltage V.sub.DD, and a ground (GND) rail 68 of the power supply. The monitoring circuit measures the voltage difference between the two rails, and provides one or more out-of-range levels to PU according to a difference from a preset range of values within which operating circuitry 62 can operate correctly.

(34) For the first disclosed embodiment referred to above, monitoring circuit 64 may check that the voltage difference between the power and ground rails of power supply 38 lies typically between 0.4V, corresponding to V.sub.MIN, and 1.5V, corresponding typically to V.sub.MAX. If the difference is less than 0.4V, a low out-of-range level is output, and if the difference is greater than 1.5V a high out-of-range level is output.

(35) Monitoring circuit 64 may perform a similar check for other voltages. For example, for the second disclosed embodiment referred to above, the circuit may check that the voltage difference between the rails of power supply 38 lies between about 0.7V, V.sub.MIN, and about 1.1V, V.sub.MAX. If in this case, the difference is less than 0.7V the low out-of-range level is output, and if the difference is greater than 1.1V the high out-of-range level is output.

(36) In some embodiments, an out-of-range level is output as a threshold-crossing indication to PU 60 if a voltage of the power supply is less than a lower threshold. In a further disclosed embodiment the lower threshold is set to be less than 1.5 volts. In an alternative further disclosed embodiment, the lower threshold is in a range of 0.4 volts to 0.7 volts, or in a range of 0.4 volts to 0.8 volts.

(37) FIG. 2B is a schematic graph 70 of the performance of a system component, showing a measured performance parameter of the component, according to an embodiment of the present invention. By way of illustration and not limitation, the component may be I2F converter 36A1, as described in the following example. Graph 70 is derived from the specification of the I2F converter, and plots frequencies generated by the converter, on a vertical axis 72, vs. supply voltages applied to the converter on a horizontal axis 74. Axis 74 is generally similar to number line 40 (FIG. 1B), so that supply voltages V.sub.ABSMIN, V.sub.ABSMAX, V.sub.MIN, and V.sub.MAX, as well as ranges R2, R3, and R4, are as defined above with respect to line 40, and apply to I2F converter 36A1. Graph 70 illustrates other parameters that are relevant to the performance of the I2F converter.

(38) Within the bounds defined by V.sub.MIN and V.sub.MAX, i.e., in range R2 wherein the voltage powering the converter enables the converter to operate to its complete specification, the frequency output by the converter is able to vary between a low frequency F.sub.L and a high frequency F.sub.H for given respective low and high currents received by the converter. It is noted that another parameter besides frequency may be used, as well.

(39) As the supply voltage decreases and enters range R3, the low and high frequencies generated by the converter (for the given received currents) change, as shown by lines 76 and 78.

(40) Referring back to the description of prosthesis 20 and to FIG. 1A, there is a minimum pulse frequency, typically of a few Hertz, and in a disclosed embodiment less than 10 Hz. There is also a maximum pulse frequency, typically up to a few hundred Hertz and in a disclosed embodiment greater than 200 Hz. The pulse frequency drives electrodes 26.

(41) The voltage V.sub.DATA, which is lower than V.sub.ABSMIN, is described below, and is shown on graph 70 for simplicity. Voltage V.sub.OSC, also shown on graph 70 and described below, is typically equal to V.sub.ABSMIN, but may be lower than V.sub.ABSMIN. (It is noted that V.sub.OSC is shown in FIG. 2B, although in general the figure is intended to apply to any monitored parameter, and not only to frequency.)

(42) Returning to FIG. 2A, monitoring circuit 64 comprises a reference current generator 80 which supplies a preset fixed reference current I.sub.REF to a circuit element 82 (e.g., I.sub.REF representing the minimum current input to the I2F converter for complying with the specification requirements). Element 82 is assumed, by way of example, to comprise an I2F converter which is typically, but not necessarily, a replica of I2F converter 36A1. Element 82, herein also referred to as I2F converter 82, generally emulates the performance and transfer function of converter 36A1. In response to reference current I.sub.REF, converter 82 generates a frequency F.sub.I2F, according to the transfer function of the converter. Frequency F.sub.I2F is a first input of a frequency detector 84.

(43) Circuit 64 also comprises a reference clock 86, which provides a reference clock frequency F.sub.CL as a second input to the frequency detector. Clock 86 is typically configured to be more stable than the frequency generated by the combination of current generator 80 and I2F converter 82. Using frequency F.sub.CL as a reference, detector 84 determines if frequency F.sub.I2F is within preset acceptable limits, and so effectively checks if the voltage applied to I2F converter 82 from power supply 38 is within range R2 (FIG. 2B). If frequency F.sub.I2F is within the preset limits, detector 84 is configured to provide a signal to PU 60 indicating that the voltage from the power supply enables I2F converter 82 to operate according to the complete specification of the converter. Alternatively, the detector provides no signal, which provides the same indication to the processing unit.

(44) If frequency F.sub.I2F is outside the preset limits, detector 84 is configured to provide an “out-of-range” signal to PU 60, indicating that the voltage provided to I2F converter 82 is in range R3, so that the converter is out of specification but is able to partially operate. In some embodiments, detector 84 is configured to provide respective different out-of-range signals, according to sub-ranges of range R3.

(45) Typically, except for I2F converter 82, the components of monitoring circuit 64, i.e., generator 80, detector 84, and clock 86 are configured to operate acceptably at voltages below V.sub.ABSMIN. For example, clock 86 is able to provide its clock signals so long as power supply 38 generates a voltage greater than or equal to V.sub.ABSMIN. A voltage V.sub.DATA, which is less than V.sub.ABSMIN, is a voltage below which data stored in volatile memory elements of prosthesis 20 may be lost.

(46) As explained above, monitoring circuit 64 may evaluate the performance of a replica of an element of one of channels 34 (in operating circuitry 62) in order to determine a range of the voltage supplied by power supply 38 to the operating circuitry.

(47) FIG. 3 is a block diagram that schematically illustrates conversion circuitry 132, according to an alternative embodiment of the present invention. Apart from the differences described below, the operation of circuitry 132 is generally similar to that of circuitry 32 (FIGS. 2A and 2B), and elements indicated by the same reference numerals in both circuitry 32 and 132 are generally similar in construction and in operation.

(48) In the alternative embodiment illustrated in FIG. 3, respective sets 36 of channels 34 comprise TIAs and V2Fs, so that set 36M of elements of a particular channel 34M comprises TIA 36M1 and V2F 36M2. (The TIA and V2F of each specific channel may be connected in series so as to have generally the same performance as an I2F.)

(49) In circuitry 132, a monitoring circuit 164 performs a similar function to that of monitoring circuit 64, in order to evaluate the voltage supplied by power supply 38. However, monitoring circuit 164 assesses the performance of an element 134. Element 134 is configured to have a performance that emulates that of TIA 36M1. Element 134 is typically, although not necessarily, a replica of TIA 36M1, and the element is herein also referred to as TIA 134. In order to make its assessment, circuit 164 comprises two similar comparators 166 and 168, as well as reference voltage generators 170 and 172. Generator 170 outputs a predetermined fixed constant voltage V.sub.HIGH, and generator 172 outputs a predetermined fixed constant voltage V.sub.LOW; V.sub.HIGH>V.sub.LOW. The values of V.sub.HIGH and V.sub.LOW are selected so that, as described hereinbelow, an output of a NOR gate 174 is indicative as to whether the voltage supplied by power supply 38 to TIA 134 is within limits that allow the TIA to operate correctly.

(50) Comparator 166, which is used only if V.sub.ABSMAX 22 V.sub.HIGH, receives constant voltage V.sub.HIGH and an output V.sub.O from TIA 134, and compares the two inputs. If V.sub.O>V.sub.HIGH, the comparator outputs a ‘1’. If V.sub.O≦V.sub.HIGH the comparator outputs a ‘0’.

(51) Comparator 168 receives constant voltage V.sub.LOW and output V.sub.O, and compares the two inputs. If V.sub.O<V.sub.LOW, the comparator outputs a ‘1’. If V.sub.O≧V.sub.LOW comparator 168 outputs a ‘0’.

(52) When V.sub.ABSMAX>V.sub.HIGH, the outputs of the two comparators are input to NOR gate 174. If either V.sub.O<V.sub.LOW or V.sub.O>V.sub.HIGH, then NOR gate 174 outputs a ‘0’. PU 60 is configured to interpret a ‘0’ from the NOR gate as an out-of-range indication, i.e., that the voltage supplied to TIA 134 is within a range, corresponding to one of ranges R3 and R4 (FIG. 2B), wherein TIA 134 operates partially according to its specification. Those having ordinary skill in the art will be able to adapt the circuit of FIG. 3 to monitor the output of TIA with respect to just one bound V.sub.LOW or V.sub.HIGH, rather than the two bounds described above.

(53) When V.sub.ABSMAX=V.sub.HIGH, comparator 166 is not used, and NOR gate 174 is replaced by an inverter, or the polarity of comparator 168 is inverted.

(54) As described above with reference to monitoring circuit 64, in the embodiment illustrated in FIG. 3, circuit 164 evaluates the performance of a replica of an element, herein a TIA, of one of channels 34 in operating circuitry 62 in order to determine a range of the voltage supplied by power supply 38 to the operating circuitry.

(55) Alternatively, circuit 164 may be reconfigured to evaluate the performance of a replica of a different element, such as V2F converter 36M2. The reconfiguration, mutatis mutandis, is generally as described for monitoring circuit 64 (FIG. 2A), except that current generator 80 is replaced by a voltage source, and I2F converter 82 is replaced by a V2F converter.

(56) FIG. 4A is a block diagram that schematically illustrates conversion circuitry 232, and FIGS. 4B and 4C are graphs illustrating the operation of the circuitry, according to alternative embodiments of the present invention. The purpose of this circuitry is to monitor the operation of the oscillator that generates clock pulses from a clock circuit 272, and to verify that it is within a specific limit. Apart from the differences described below, the operation of circuitry 232 is generally similar to that of circuitry 132 (FIG. 3), and elements indicated by the same reference numerals in both circuitry 132 and 232 are generally similar in construction and in operation. Thus, for example, circuitry 232 may be used to monitor voltage levels corresponding to those of the first, second, and third disclosed embodiments referred to above.

(57) In a power supply monitoring circuit 264, reference current generator 80 is configured as a current generator which provides a fixed current I.sub.CH to charge a capacitor 266. In some embodiments generator 80 comprises a resistor. The generator is connected to a first conductor or plate of the capacitor, and a second plate of the capacitor is connected to ground rail 68. A comparator 268 is connected to the first plate of capacitor 266.

(58) A switch 270 is connected across capacitor 266 in a configuration that enables the switch to short the capacitor when the switch is closed. In one embodiment, switch 270 is an NMOS transistor having its source connected to the first plate of the capacitor and its drain connected to the capacitor second plate.

(59) FIG. 4B illustrates graphs of the behavior of circuitry 232 when power supply 38 is generating its specified voltage levels (V.sub.DD and GND). As shown in FIG. 4B, a clock circuit 272 produces clock pulses, illustrated by a graph 274A, and the circuit is connected so that the pulses drive the gate of switch 270. In periods 276 when there are no clock pulses, switch 270 is open. Thus, in periods 276 capacitor 266 charges up so that, as shown by a graph 278A of the voltage input to comparator 268, the voltage on the comparator increases. The comparator typically has some internal switching threshold, causing the output to change when the input exceeds this threshold. An example of such a comparator is a simple CMOS inverter. Implementing the comparator with hysteresis is an optional embodiment of comparator 268.

(60) In periods 280 when there are clock pulses, switch 270 is closed and so acts as a short circuit. Thus, in periods 280, capacitor 266 discharges, i.e., the capacitor is periodically discharged. In these periods the voltage on comparator 268 falls to a value close to zero.

(61) Graph 278A illustrates that the input voltage to the comparator periodically reaches a maximum level 282, then falls to zero. In embodiments of the present invention, comparator 268 is configured to compare its received input voltage with a preset voltage level 284, corresponding to V.sub.ref in FIG. 4A, greater than maximum level 282. If maximum 282 is less than level 284, then the comparator outputs a ‘0’ to PU 60. This is illustrated in a graph 286A of the output of comparator, showing that the comparator output is ‘0’.

(62) FIG. 4C illustrates graphs of the behavior of circuitry 232 when power supply 38 is not generating its specified voltage levels, i.e., the supply is out of specification so that clock circuit 272 has ceased to provide pulses, as shown in a graph 274B. The cessation of pulses prevents transistor 270 from discharging the capacitor. The capacitor thus charges to a voltage higher than preset voltage 284, as shown in a graph 278B. At the time when the capacitor reaches this higher voltage, the comparator outputs a ‘1’, as shown in a graph 286B. PU 60 is configured to interpret the ‘1’ as an out-of-range signal. The level ‘1’ output by the comparator continues as long as clock 272 does not generate clock pulses.

(63) FIGS. 4B and 4C illustrate two extremes of a range of possible states of circuitry 232—a first state wherein power supply 38 supplies power to clock circuit 272 so that comparator 268 never outputs an out-of-range signal, and a second state wherein the comparator outputs an out-of-range signal continuously. It will be understood that if the clock pulses generated by clock circuit 272 change from those described above, for example, if the pulse frequency decreases and/or if the period when there is no pulse increases, the comparator may output an out-of-range signal intermittently. Such an intermittent situation may occur if power supply 38 supplies a voltage less than that specified, but greater than zero, to clock circuit 272. Typically, PU 60 is configured to interpret an intermittent out-of-range signal as indicative of power supply 38 being in range R3 (FIG. 2B).

(64) As for circuitry 232, in some embodiments of circuitry 232 an out-of-range level is output as a threshold-crossing indication to PU 60 if a voltage of the power supply is less than a lower threshold, which is typically less than 1.5 volts. For example, the lower threshold may be set to be within a range of 0.2 volts to 0.6 volts.

Circuitry Operation when the Power Supply is Out of Specification

(65) FIG. 5 is a block diagram that schematically illustrates conversion circuitry 332, according to an embodiment of the present invention. Apart from the differences described below, the operation of circuitry 332 is generally similar to that of circuitry 232 (FIGS. 4A-C), and elements indicated by the same reference numerals in both circuitry 232 and 332 are generally similar in construction and in operation. For clarity, in the description of circuitry 332, the circuitry is assumed by way of example to comprise monitoring circuit 264. Those having ordinary skill in the art will be able to adapt the description, mutatis mutandis, for other circuits monitoring power supply 38.

(66) For simplicity, channels 34 are assumed to be grouped as an operating module 334. During operation of circuitry 332, the channels of the module are able to communicate with a circuit element 336. Hereinbelow, except as otherwise indicated, element 336 is assumed to comprise a volatile memory, so that the channels read from and write to volatile memory 336. In some embodiments, at least part of volatile memory 336 is incorporated into channels 34. Operating circuitry 62 is configured so that module 334 and memory 336 independently receive power from power supply 38, via respective switching circuits 338 and 340, which each typically comprise one or more transistors. Switching circuits 338 and 340 are controlled by PU 60.

(67) If PU 60 receives an out-of-range signal from monitoring circuit 264, the processing unit may be configured to reduce or cut off the power to the channels of module 334, while maintaining the power to volatile memory 336, using switching circuits 338 and 340, or in an alternative implementation, by stopping the switching or DC power consumption of some or all of the operation circuits. Such a procedure reduces or completely stops the operation of the channels of module 334, while maintaining the data in the volatile memory.

(68) Typically, as described above, the out-of-range signal is output as a threshold-crossing indication to PU 60 if a voltage of the power supply is less than a lower threshold, which is typically less than 1.5 volts. For example, the lower threshold may be a value that is between 0.2 volts and 0.6 volts.

(69) In one embodiment the reduction in the power level is performed smoothly. In an alternative embodiment, the reduction in the power level is performed in a stepwise fashion. Typically, the reduction in power level is configured to avoid instability and/or ringing in a circuit being energized by the power supply.

(70) By controlling which elements of circuitry 332 continue to receive adequate power (in this case the volatile memory) when the available power is reduced, typically when the voltage driving circuitry 332 reduces to a few tenths of a volt, the processing unit ensures that when the available power enables the channels of module 334 to resume full operation, the data in the memory is effectively instantly available for the operation of the channels.

(71) Thus, in circuitry 332, PU 60 and monitoring circuit 264 effectively act together as a power monitoring module that maintains the data in memory 336 valid even under reduced power situations.

(72) In an alternative embodiment, rather than circuit element 336 comprising a volatile memory, the element comprises other circuitry such as control logic.

(73) FIG. 6A is a block diagram that schematically illustrates conversion circuitry 432, and FIG. 6B illustrates examples of voltage vs. time graphs of current pulses used by the circuitry, according to embodiments of the present invention. Apart from the differences described below, the operation of circuitry 432 is generally similar to that of circuitry 232 (FIGS. 4A-C), and elements indicated by the same reference numerals in both circuitry 232 and 432 are generally similar in construction and in operation.

(74) During typical operating conditions, current pulses delivered by channels 34 to their respective electrodes are configured to be balanced, i.e. to comprise pulses which over a period of time generate no net charge transfer. FIG. 6B illustrates examples of voltage vs. time graphs of balanced pulses. If power is reduced to channels 34 by power supply 38 operating out of its specification, then, unless there are safeguards in place, the channels may deliver unbalanced pulses, i.e., pulses having a net charge transfer, to their electrodes. Such unbalanced pulses may, inter alia, induce electrochemical corrosion, leading to dissolution of the metal of the electrodes. Circuitry 432 safeguards against the delivery of unbalanced pulses.

(75) Each channel 34 is assumed to have a respective electrode driver, so that channel 34M has a driver 36M3 in its set of elements 36M. Driver 36M3 is connected to an electrode 434 which, by way of example, is assumed to be coupled to retinal tissue 24 and to be in proximity to optic nerve 21 (FIG. 1).

(76) Each channel 34 also typically comprises a switch which is operated by PU 60 (or by an alternative power reduction circuit), and which is normally closed and opens by PU 60 only when driver 36M3 is active. In a power shortage situation switch 36M4 may be closed at all times by a signal from PU 60 to ensure no imbalanced pulses are delivered. In its closed state, switch 36M4 connects electrode 434 to a local, human body, ground electrode 436. By way of example, ground electrode 436 is assumed to be connected to the outside of the optic nerve, which acts as a local ground. However, electrode 436 may be connected to any other convenient location which is able to act as a local human body ground.

(77) Alternatively or additionally, in some embodiments, electrode 436 may be connected to ground rail 68. If PU 60 receives an out-of-range signal from monitoring circuit 264, the processing unit may be configured to transmit a PU CTRL signal to one or more channels 34. The out-of-range signal may be output as a threshold-crossing indication to PU 60 if a voltage of the power supply is less than a lower threshold, which is typically less than 1.5 volts. For example, the lower threshold may be set to be within a range of 0.4 volts to 0.8 volts.

(78) Receipt of the PU CTRL causes the switch of the respective channel to close, so clamping the potential of the electrode connected to the channel to the local ground potential. In the example illustrated in FIG. 6A, signal PU CTRL cause electrode 434 to be clamped to the local ground.

(79) By clamping electrodes to the local ground potential, circuitry 432 prevents the possibility of unbalanced pulses being transmitted to the electrodes.

(80) Alternatively, instead of the channels comprising a switch such as switch 36M4, the channels may be configured to have power down circuitry that reduces the current consumption of the module significantly. In one embodiment, the reduced current consumption maintains a reduced number of active channels at, for example, less than 40% of the total number of channels. In an embodiment the reduced current consumption maintains a reduced number of active channels at less than 15% of the total number of channels. In this manner, for example, even though there may be insufficient power available to drive all of the electrodes of a retinal prosthesis to apply pulses to a patient's retina, at least a small number of the electrodes continue to operate and apply pulses to the retina.

(81) FIG. 7 is a block diagram that schematically illustrates conversion circuitry 532, according to an embodiment of the present invention. Apart from the differences described below, the operation of circuitry 532 is generally similar to that of circuitry 232 (FIGS. 4A-C), and elements indicated by the same reference numerals in both circuitry 232 and 532 are generally similar in construction and in operation.

(82) If power is reduced to circuitry 532 by power supply going out of specification, some components or circuits of the circuitry may oscillate in behavior. For example, a clock circuit may cease generating pulses due to a lowered voltage from power supply 38. However, because of the reduced current demand from the clock circuit, the voltage provided by supply 38 may then rise. Such an increase in voltage might cause the oscillator to re-start oscillating, which will increase the current and drop the supply voltage. This behavior might repeat again and again, causing oscillations of the power supply voltage.

(83) In circuitry 532, channels 34 of operating circuitry are assumed to be divided into two sets of channel operating modules: a first operating module set 534 having channels such as channel 34C, and a second operating module set 536 having channels such as channel 34D. The two modules are controlled by PU 60, so are effectively coupled together. Each operating module is assumed to be powered separately, via respective power controls 538 and 540 which are operated by PU 60, from power supply 38. A division of channels in such a manner may be implemented for central and peripheral light sensing elements 30 and their respective channels 34 (FIG. 1). By way of example, in the case of power supply providing a voltage which is out of specification, first set 534 is assumed to have its power reduced by PU 60 before second set 536. However, the division into two operating modules of operating circuitry 62 is by way of example, and those having ordinary skill in the art will be able to adapt the description herein, mutatis mutandis, for the division of circuitry, such as conversion circuitry 532, into other operating modules powered separately by power supply 38.

(84) Circuitry 62 typically comprises a time delay module 542 which incorporates a preset time interval. On receipt of an out-of-range signal from monitoring circuit 264, indicating that the voltage supplied by power supply 38 is out of specification, PU 60 accesses the time delay module to retrieve the preset time interval. The processing unit waits the preset time interval before activating power control 538 to reduce the power to module 534, but maintains the power to module 536, via control 540, during the time interval and after the interval has elapsed. The same mechanism may be applied when the out-of-range signal is de-asserted, enabling stabilization time during power-up. Thus, for example, after the de-assertion of the out-of-range signal, the processing unit may wait a second preset time interval, prior to activating power control 538 to increase power to module 534. (The second time interval is typically but not necessarily longer than the preset time interval that precedes power reduction to module 534.)

(85) The out-of-range signal may be output as a threshold-crossing indication to the processing unit if a voltage of the power supply is less than a lower threshold, which is typically less than 1.5 volts. For example, the lower threshold may be between 0.2 volts to 0.6 volts, or 0.4 volts to 0.8 volts.

(86) In some embodiments, PU 60 may be configured to reduce the power to power module 534 gradually in steps. Typically in such embodiments, module 534 may be divided into subsets of channels, and the graduated reduction in power may be implemented by reducing power to increasing numbers of subsets.

(87) Some embodiments of the present invention may apply a similar delay, or a hysteresis of comparator 268, to that described above for the case wherein power supply 38 reverts from an out of specification state to being within specification. For example, supply 38 may initially generate a low voltage causing monitoring circuit 264 to output an out-of-range signal. After the preset time interval provided by delay module 542, PU 60 reduces the power to module 534. Supply 38 may then increase its voltage to within specification, so that circuit 264 no longer outputs the out-of-range signal. The processing unit may again access delay module 542 to retrieve a further preset time interval, which PU 60 applies before restoring power to module 534. In some embodiments the further preset time interval, applied for increasing the power to module 534, may be different from the time interval used for reducing the power to the module. Alternatively, the two time intervals may be the same.

(88) From a review of the description above it is apparent that PU 60 and monitoring circuit 264 act as a power monitoring module which applies hysteresis to power changes introduced into circuitry 532, by incorporating the one or more time delays described above into the actions of the processing unit. The applied hysteresis eliminates any tendency of the elements of 532 to oscillate, during periods when the voltage supplied by power supply 38 fluctuates.

(89) FIG. 8 is a schematic circuit diagram of a memory 600 that may be used in any of the conversion circuitries described herein, as well as in other circuits comprising a memory, according to an embodiment of the present invention. Memory 600 is a modified version of a standard SRAM (static random access memory) cell. For clarity, in the following description of the operation of memory 600, the memory is assumed to be powered by power supply 38 (FIG. 2A), but those having ordinary skill in the art will be able to adapt the description, mutatis mutandis, for any other convenient power supply powering the memory.

(90) Typically a plurality of memories generally similar to memory 600 are formed into a memory module, such as volatile memory 336 (FIG. 5).

(91) Memory 600 (FIG. 8) comprises a p-type and an n-type field effect transistor (FET), p1 and n1, which are connected to form a first inverter. The gates of p1 and n1 are connected to each other and to a “Q” data line. The source of n1 is connected to the drain of p1 and to a “Q” data line, the source of p1 is connected to power rail V.sub.DD, and the drain of n1 is connected to ground rail GND.

(92) Memory 600 also comprises a p-type FET p2 and an n-type FET n2 which are connected to form a second inverter. The gates of p2 and n2 are connected to each other and to the Q line. The source of n2 is connected to the drain of p2 and to the “Q” line, the source of p2 is connected to power rail V.sub.DD, and the drain of n2 is connected to ground rail GND.

(93) Two n-type FETs, n3 and n4, are respectively connected to the Q and Q data lines. A WL line is connected to gates of n3 and n4, and enables the values of Q and Q to be read from and written to via respective lines BL and BLB.

(94) A p-type FET p3 has its drain connected to the Q line, and its source connected via a floating line 602 to a first plate 604 of a capacitor c1. A second plate 606 of the capacitor is connected to ground. The gate of p3 is connected to the Q line. As explained below, capacitor c1 acts as an electrical energy storage device, supplying the voltage required to memory 600 for a limited period of time (e.g., during an eye blink, saccade, or short period up to 30, 200, or 1000 ms, c1 typically having a value of about 100-1000 femtofarads). However, capacitor c1 is only one possible example of a suitable electrical energy storage device for the memory, and other suitable storage devices that are capable of supplying voltage and that may substitute for capacitor c1 will be apparent to those having ordinary skill in the art. Such other devices include, but are not limited to, chemical batteries or photovoltaic cells, and all such devices are assumed to be comprised within the scope of the present invention.

(95) A p-type FET p4 has its drain connected to the Q line, and its source connected via line 602 to first plate 604. The gate of p4 is connected to the Q line.

(96) While power supply 38 supplies its specified voltage VDD to memory 600, FETs p1, n1, p2, n2, n3, and n4 act as a single bit memory, the values of lines Q and Q taking the values of 1 or 0, depending on the values input on lines BL and BLB. In addition, one of FETs p3 or p4 conducts while the other FET does not conduct. The conduction maintains plate 604 in a charged state.

(97) If power supply 38 changes so that the voltage V.sub.DD supplied is low, typically below the threshold voltage of transistors p1 and p2 (and even if V.sub.DD is zero), then capacitor c1 begins to discharge through the FET, p3 or p4, conducting at the time when the power supply is below the voltage in floating line 602. The out of specification situation typically occurs when V.sub.DD is a few tens or hundreds of millivolts. The out of specification situation may occur when V.sub.DD is below V.sub.MIN (FIG. 1B and FIG. 2B), for example below the value of V.sub.MIN of the first, second or third disclosed embodiments described above in reference to FIG. 1B. The discharge maintains the potential of the line Q or Q which is receiving the charge from plate 604, until the capacitor has completely discharged.

(98) Without the presence of capacitor c1 and FETs p3 and p4, data loss may be caused once V.sub.DD drops below a predetermined voltage, which is proportional to an offset voltage created by any mismatch between the first and second invertors. While the mismatch may be theoretically limited, in practice processing variations may generate an offset. Applying the combination of capacitor c1 with FETs p3 and p4 allows data to be maintained in memory 600 even when voltage V.sub.DD is extremely low or even zero, for a limited period of time (e.g., tens or hundreds of milliseconds).

(99) The length of time for which the data may be maintained is dependent on the capacitance of c1, and on the resistance offered by FETs p3 and p4. Thus for a high capacitance and resistance the time over which the data may be maintained is of the order of tens or more milliseconds after a complete power down of VDD. Capacitor c1 may be implemented by any convenient method, such as by separating two polysilicon layers by a silicon dioxide dielectric (a poly-poly capacitor) or by separating two metal layers by a dielectric. Alternatively or additionally, capacitor c1 may be at least partially implemented using the gate of a transistor, by methods well known in the art.

(100) The description above has assumed that capacitor c1 supplies charge to a single memory, memory 600. In alternative embodiments of the present invention a single capacitor is configured to supply charge to a plurality of memories, substantially similar to memory 600, each having eight transistors as illustrated in FIG. 8. In the alternative embodiments, line 602 is connected as a shared floating power supply line to the sources of the respective FETs p3, p4 in each of the plurality of memories.

(101) FIG. 9 is a schematic block diagram of data loading circuitry 650 that may be used in any of the conversion circuitries described herein, according to an embodiment of the present invention. Typically, during powering up of a circuit, data is loaded into volatile memory comprised in the circuit. Once the data has been loaded into the volatile memory, the circuit is able to function correctly. Usually, while the circuit is functioning, the data in the volatile memory is updated as circuit conditions change.

(102) Data loading circuitry 650 applies a condition to the data loading that may be implemented during powering up of a circuit. For clarity and by way of example, in the following description of circuitry 650, the data loading circuitry is assumed to be comprised in conversion circuitry 332 (FIG. 5). The data loading circuitry comprises a volatile configuration register 652 (which is typically part of volatile memory 336) as well as default configuration code data 654 and default error correction code data 656 which are typically stored in a non-volatile manner in operating circuitry 62. Configuration code data 654 defines a configuration of the circuit being powered up.

(103) Circuitry 650 is implemented so that when power supply 38 powers up, a RESET signal is applied to a first input of an AND gate 658. The RESET signal may be derived by monitoring a clock activity, such as by an adaptation of monitoring circuit 264 (FIG. 4A), or by monitoring a voltage level such as by an adaptation of monitoring circuit 164 (FIG. 3). Such adaptations, mutatis mutandis, will be apparent to those having ordinary skill in the art. Alternatively, the RESET signal may be derived from any other convenient monitoring system known in the art.

(104) In addition to applying the RESET signal, once power supply 38 has powered up an error detection logic module 660 checks the data values stored in register 652. Module 660 typically comprises parity checking or error detection logic, which may be implemented by CMOS logic circuits. If module 660 detects an error in the data values it outputs an ERROR signal to a second input of AND gate 658.

(105) If AND gate 658 receives both the RESET and the ERROR signals, it outputs a LOAD signal. However, no LOAD signal is output if only one of, or if neither of, the RESET and the ERROR signals are received by the AND gate. The LOAD signal is used, typically by PU 60 in conversion circuitry 332, to load default configuration data 654 and default error correction code data 656 into register 652.

(106) It will be understood that data loading circuitry 650 only allows necessary loading of data into register 652, as illustrated by broken arrows 662 and 664, and that loading only occurs if there is an error detected in the checked data. The data loading circuitry prevents unnecessary loading of data into the register, reduces demands on power supply 38, and typically only permits new configuration data to be loaded into the configuration register if the voltage supplying the circuit being powered up is equal to or above a preset limit.

(107) Furthermore, the circuitry prevents the configuration register from accepting and using wrong or incorrect configuration data. Such incorrect data could be loaded, absent circuitry 650, if the voltage powering the circuit is low enough, for example below the value of V.sub.MIN of the first, second or third disclosed embodiments described above in reference to FIG. 1B. In these cases, the wrong configuration data would adversely affect the configuration of the circuit being powered up. The unnecessary loading prevented by the data loading circuitry has no negative effects on the circuitry, such as conversion circuitry 332, in which it is implemented.

(108) It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.