DIGITAL FREQUENCY CONVERTER AND METHOD OF PROCESSING IN A DIGITAL FREQUENCY CONVERTER

Abstract

A frequency converter comprising a frequency transposition block for samples (11.sub.Q.sub._.sub.1, 11.sub.Q.sub._.sub.2), a filtering block (12.sub.Q.sub._.sub.1, 12.sub.Q.sub._.sub.2), the filtered samples y(n) verifying y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2)+ . . . +c(p−1).Math.x(n−p+1)+c(p).Math.x(n−p)+c(p−1).Math.x(n−p−1)+ . . . + . . . +c(1).Math.x(n−2.Math.p+1)+c(0).Math.x(n−2.Math.p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0).Math.x(n), c(1).Math.x(n−1), c(2).Math.x(n−2), . . . , c(p).Math.x(n−p) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p−1).Math.x(n−p−1), . . . , c(1).Math.x(n−2.Math.p+1), c(0).Math.x(n−2.Math.p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(n−m); and determining y(n) by summation of the first and second terms.

Claims

1. A frequency converter adapted for receiving signal samples and comprising: at least one frequency transposition block adapted for transposing in frequency said received samples; at least one filtering block adapted for filtering said transposed samples and for delivering filtered samples y(n) verifying the formula y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2)+ . . . +c(p−1).Math.x(n−p+1)+c(p).Math.x(n−p)+c(p−1).Math.x(n−p−1)+ . . . + . . . +c(1).Math.x(n−2.Math.p+1)+c(0).Math.x(n−2.Math.p), wherein x( ) are transposed samples and c(0), . . . c(p) are real coefficients of the filter; and a set of memories; said frequency converter being adapted for, during a cycle for determining the value of the filtered sample y(n), carrying out operations for calculating the first terms c(0).Math.x(n), c(1).Math.x(n−1), c(2).Math.x(n−2), . . . , c(p).Math.x(n−p) by multiplying the respective coefficients and transposed samples, and storing at least certain of said first calculated terms in the set of memories; reading, in the set of memories, at least certain of the second terms c(p−1).Math.x(n−p−1), . . . , c(1).Math.x(n−2.Math.p+1), c(0).Math.x(n−2.Math.p), calculated and stored during the previous cycles for determining the value of filtered samples y(n−m), with m being a strictly positive integer; and determining y(n) by summation of the first and second terms.

2. The frequency converter according to claim 1, adapted for receiving sampled real signal samples and for delivering complex signals I/Q, from the filtering by the filtering block after transposition with the transposition block of said sampled real samples, said converter including parallel chains for processing of the signals I and of the signals Q, at least one of said processing chains I, Q comprising V parallel routes each adapted for carrying out frequency transposition, said power converter being adapted for selectively distributing the real samples between said routes, each (V.Math.n+i−1).sup.th real sample being provided to the i.sup.th route, i=1 to V, n being a positive integer.

3. The frequency converter according to claim 2, adapted for operating in a way clocked by a clock frequency signal, a so called operating frequency, and adapted for receiving the real samples sampled according to a sampling frequency, V being equal to the quotient of the sampling frequency by the operating frequency.

4. The frequency converter according to claim 3, wherein the frequency transposition comprises a multiplication of the samples with a sine or cosine of frequency equal to F.sub.e/4, V/2 routes thereby delivering always zero transposed samples.

5. The frequency converter according to claim 2, wherein at least the k.sup.th and j.sup.th parallel routes of said processing chain (V.sub.Q), k≠j and k, j integers between 1 and N, comprising a filtering sub-block adapted for determining the filtered signal y(N.Math.n+i−1)=c(0).Math.x(N.Math.n+i−1)+c(1).Math.x(N.Math.n+i−1−1)+c(2).Math.x(N.Math.n+i−1−2)+ . . . +c(p−1).Math.x(N.Math.n+i−p)+c(p).Math.x(N.Math.n+i−1−p)+c(p−1).Math.x(N.Math.n+i−1−p−1) . . . +c(1).Math.x(N.Math.n+i−1−2.Math.p+1)+c(0).Math.x(N.Math.n+i−1−2.Math.p), wherein x( ) are signals from the transposition in said processing chain, with i=j on the j.sup.th route, and i=k on the k.sup.th route, the filtering sub-block of the k.sup.th route, respectively of the j.sup.th route, being adapted for calculating the first terms c(0).Math.x(N.Math.n+i−1), . . . ,c(p).Math.x(N.Math.n+i−1−p) by multiplying the respective coefficients and transposed samples, in order to store at least certain of said first terms calculated in the set of memories and for reading, in the set of memories, at least certain of the second terms c(p−1).Math.x(N.Math.n+i−1−p−1), . . . , c(0).Math.x(N.Math.n+i−1−2.Math.p), calculated and stored during previous cycles for determining the value of filtered samples y(n−m), with m being a strictly positive integer, certain of said second terms having been calculated by the filtering sub-block of the j.sup.th route, respectively of the k.sup.th route.

6. The processing method in a frequency converter adapted for receiving signal samples, the method comprising the following steps: receiving the signal samples; transposing in frequency said received samples; filtering said transposed samples, the filtered samples y(n) verifying the formula y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2)+ . . . +c(p−1).Math.x(n−p+1)+c(p).Math.x(n−p)+c(p−1).Math.x(n−p−1)+ . . . + . . . +c(1).Math.x(n−2.Math.p+1)+c(0).Math.x(n−2.Math.p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; said processing method comprising the following steps, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0).Math.x(n), c(1).Math.x(n−1), c(2).Math.x(n−2), . . . , c(p).Math.x(n−p) by multiplying the respective coefficients and transposed samples, and storing at least certain of said first terms calculated in a set of memories; reading, in the set of memories, at least certain of the second terms c(p−1).Math.x(n−p−1), . . . , c(1).Math.x(n−2.Math.p+1), c(0).Math.x(n−2.Math.p), calculated and stored during previous cycles for determining the value of filtered samples y(n−m), with m being a strictly positive integer; and determining y(n) by summation of the first and second terms.

7. The processing method according to claim 6, for a frequency converter adapted for receiving sampled real signal samples and delivering complex I/Q signals from the filtering after transposition of said sampled real samples, said method comprising the steps: processing in parallel the real samples on a processing chain I for signals I and a Q processing chain for signals Q (V.sub.I, V.sub.Q); on at least one of said parallel processing chains comprising V parallel routes, selective distribution of the real samples among said routes, each real (V.Math.n+i−1).sup.th sample being provided to the i.sup.th route, i=1 to V, n being a positive integer.

8. The processing method according to claim 7, according to which the processing operation is clocked by a clock frequency signal, a so called operating frequency, and according to which the sampled real samples are received according to a sampling frequency, and V is equal to the quotient of the sampling frequency by the operating frequency.

9. The processing method according to claim 8, according to which the frequency transposition comprises a multiplication of the samples by a sine or cosine of frequency equal to F.sub.e/4, V/2 routes thereby delivering always zero transposed samples.

10. The processing method according to claim 7, comprising, on at least the k.sup.th and j.sup.th parallel routes of said processing chain (V.sub.Q), k≠j and k, j integers between 1 and N, the determination of the filtered signal y(N.Math.n+i−1)=c(0).Math.x(N.Math.n+i−1)+c(1).Math.x(N.Math.n+i−1−1)+c(2).Math.x(N.Math.n+i−1−2)+ . . . +c(p−1).Math.x(N.Math.n+i−p)+c(p).Math.x(N.Math.n+i−1−p)+c(p−1).Math.x(N.Math.n+i−1−p−1) . . . +c(1).Math.x(N.Math.n+i−1−2.Math.p+1)+c(0).Math.x(N.Math.n+i−1−2.Math.p), wherein x( ) are signals from the transposition in said processing chain, with i=j on the j.sup.th route, and i=k on the k.sup.th route, and comprising on the k.sup.th route, respectively the j.sup.th route, the calculation of the first terms c(0).Math.x(N.Math.n+i−1), . . . ,c(p).Math.x(N.Math.n+i−1−p) by multiplying the respective coefficients and transposed samples, the storage of at least certain of said first calculated terms in the set of memories and the reading in the set of memories, of at least certain of the second terms c(p−1).Math.x(N.Math.n+i−1−p−1), . . . , c(0).Math.x(N.Math.n+i−1−2.Math.p), calculated and stored during previous cycles for determining the value of filtered samples y(n−m), with m being a strictly positive integer, on the j.sup.th route, respectively the k.sup.th route.

Description

[0027] These features and advantages of the invention will become apparent upon reading the description which follows, only given as an example, and made with reference to the appended drawings, wherein:

[0028] FIG. 1 represents a graph illustrating the relationship between the sampling frequency and the processing frequency in the prior art on the one hand and according to the invention on the other hand;

[0029] FIG. 2 is a view of a frequency converter of the down type in an embodiment of the invention;

[0030] FIG. 3 is a detailed view of a frequency converter of the down type in an embodiment of the invention;

[0031] FIG. 4 is a flow chart of steps applied in an embodiment of the invention.

[0032] FIG. 2 is a view of a frequency converter of the down type 10 in an embodiment of the invention.

[0033] The frequency converter of the digital down type 10 or DDC (<<Digital Down Converter>>) 10 is adapted for receiving as an input real samples z(n) in a transposed band.

[0034] The DDC (“Digital Down Converter”) 10 is adapted for delivering at the output complex samples Z(n) in a base band, i.e. for which the spectrum is centered on 0.

[0035] z(n) is the sample corresponding to the sampling time t.sub.n=n/F.sub.e and Z(n) is the sample delivered at T.sub.init+n/F.sub.e wherein n is a positive integer and the initial sampling instant.

[0036] Each complex sample is written as Z(n)=1(n)+i.Math.Q(n), wherein 1(n) is the in-phase component and Q(n) is the quadrature component.

[0037] The spectrum of these samples z(n) is thus centered around the carrier frequency f.sub.0.

[0038] The sampling frequency F.sub.e of these samples z(n) is for example the sampling frequency of an analogue/digital converter located upstream from the DDC 10.

[0039] The DDC 10 is an integral part of a FPGA and its operations are clocked by a clock signal of the FPGA having a frequency equal to F.sub.FPGA, designated as a processing frequency.

[0040] DDC 10 is adapted for continuously processing in real time the received samples z(n). The DDC 10 includes a processing route V.sub.I and a processing route V.sub.Q.

[0041] The DDC 10 is adapted for providing each real sample z(n) at the input of each processing route V.sub.I and V.sub.Q.

[0042] The DDC 10 comprises, on the route V.sub.I, a base band transposition block 11.sub.I, a low pass filter 12.sub.I and a decimating block 13.sub.I.

[0043] The DDC 10 comprises, on the route V.sub.Q, a base band transposition block 11.sub.Q, a low pass filter 12.sub.Q and a decimating block 13.sub.Q.

[0044] The frequency transposition block 11.sub.I si adapted for multiplying a real sample z(n) received at the input with a cosine function at the frequency f.sub.0: cos(2π f.sub.0t.sub.n).

[0045] The frequency transposition block 11.sub.Q is adapted for multiplying a real sample z(n) with the sine function at the frequency f.sub.0: −sin(2π f.sub.0t.sub.n).

[0046] Each decimating block 13.sub.I, 13.sub.Q is adapted for reducing the number of samples, in the relevant case, the number of samples is reduced by a factor 2. This decimation reduces the clocking on the route I, respectively Q, from 800 MHz to 400 MHz.

[0047] In the relevant case, each filter 12.sub.I, 12.sub.Q is a finite impulse response filter, a so called FIR (“Finite Impulse Response”) filter.

[0048] The output y(n) of each of these filters 12.sub.I, 12.sub.Q is written in the form of a same linear combination function of the input signal x(n) of the filter:

y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2) . . . +c(M−1).Math.x(n−M+1)  (formula 1)

[0049] wherein M is a positive integer.

[0050] In the described embodiment, each filter is a symmetrical filter, with the following properties: [0051] the number M of coefficients is odd: M=2.Math.p+1 with p being a positive integer; [0052] the coefficients are real numbers and are symmetrical c(i)=c(2.Math.p−i) i=0 to p; [0053] the odd coefficients are zero except if the odd coefficient is from among c(p) and c(p+1).

[0054] In the described embodiment, each filter is further normalized by the value of the central coefficient c(p).

[0055] The formula giving y(n) may therefore be written as:

y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2)+ . . . +c(p−1).Math.x(n−p+1)+c(p).Math.x(n−p)+c(p−1).Math.x(n−p−1) . . . +c(1).Math.x(n−2.Math.p+1)+c(0).Math.x(n−2.Math.p).

[0056] It is noted that the last p terms of the linear combination, starting from the term c(p−1).Math.x(n−p−1) until the term c(0).Math.x(n−2.Math.p) are terms used for determining previous outputs of the filter:

[0057] c(0).Math.x(n−2.Math.p) enters the calculation of y(n−2.Math.p),

[0058] c(1).Math.x(n−2.Math.p+1) enters the calculation of y(n−2.Math.p+2),

[0059] c(p−1).Math.x(n−p−1) enters the calculation of y(n−2); and

[0060] more generally c(i).Math.x(n−2p+i) enters the calculation of y(n−2p+2i), i=0 to p−1.

[0061] Similarly, the first p terms of the linear combination, from the term c(0).Math.x(n) up to the term c(p−1).Math.x(n−p+1) are terms used for determining the subsequent outputs of the filter.

[0062] According to an aspect of the invention, the number of multiplications to be performed, and therefore the number of multipliers to be set into place will be reduced by setting into place, during the calculation of an output y(n) of the filter, the storage in memory of the first p terms of the linear combination following their calculation, called hereafter intermediate results, and extraction and reuse of the intermediate results stored in memory previously during the calculation of the preceding outputs, in order to determine the last p terms of the linear combination.

[0063] The DDC 10 according to the invention is adapted for producing processing operations on each route parallel to the frequency F.sub.FPGA and delivering at the output a flow I and a flow Q, each flow being a continuous flow and in real time of samples at F.sub.e/2.

[0064] In the relevant particular case: [0065] p is selected to be equal to 27, the number of coefficients is therefore equal to 55; [0066] the coefficients are the following: c(0), c(1), c(2), . . . , c(25), c(26), c(27), c(28), c(29), . . . , c(52), c(53), c(54); [0067] c(0), c(2), . . . , c(52), c(54) have a value between −1 and 1 after normalization with the central coefficient c(27); [0068] the odd coefficients are zero c(1)=c(3)= . . . =c(25)=c(29)= . . . =c(51)=c(53)=0 except if c(27) is equal to 1 following the normalization of the coefficients; [0069] the transposed frequency f.sub.0 is equal to 200 MHz, the sampling frequency F.sub.e is equal to 800 MHz, the processing frequency F.sub.FPGA of the FGPA is equal to 200 MHz.

[0070] But the invention may of course be applied with other values for p and these frequencies.

[0071] Successive samples y(n), y(n+1) on the route I at the output of the filter 12.sub.I are therefore written as depending on the samples x(i) at the input of the filter 12.sub.I because the transposition gives rise to a sample equal to 0 every two samples because of the value of the 2π f.sub.0t.sub.i:

[00001]$y\left(n\right)=c\left(0\right)*x\left(n\right)+0*0+c\left(2\right)*x\left(n-2\right)+0*0+\mathrm{.Math.}+0*0+c\left(26\right)*x\left(n-26\right)+1*0+c\left(28\right)*x\left(n-28\right)+0*0+\mathrm{.Math.}+c\left(52\right)*x\left(n-52\right)+0*0+c\left(54\right)*x\left(n-54\right)$

as the zero samples at the input following the transposition and the zero coefficients are superposed and y(n) is a sum of 28 terms; and

[00002]$y\left(n+1\right)=c\left(0\right)*0+0*x\left(n\right)+c\left(2\right)*0+0*x\left(n-2\right)+\mathrm{.Math.}+c\left(26\right)*0+1*x\left(n-26\right)+c\left(28\right)*0+\mathrm{.Math.}+0*x\left(n-52\right)+c\left(54\right)*0$

[0072] Because of the canceling out of the terms except for one term, either with zero samples or with zero coefficients, y(n+1)=x(n−26). Therefore there is no calculation to be done, just a delay is applied.

[0073] Successive samples y(n), y(n+1) on the route Q at the output of the filter 12.sub.Q are therefore written similarly depending on the samples x(i) at the input of the filter 12.sub.Q because the transposition gives rise to a sample equal at every two samples because of the value of the 2π f.sub.0t.sub.i: y(n)=x(n−27) and y(n+1) is written as a sum of 28 terms.

[0074] The decimation of the samples by 2 amounts to only retaining one sample out of 2, i.e. according to the embodiments either y(n) or y(n+1).

[0075] In the relevant case described below, it is considered that the samples y(n) are suppressed and the samples y(n+1) are retained, which induces the application of a delay on the route I and of an FIR filter with 28 coefficients as described below.

[0076] As the coefficients are symmetrical (c(0)=c(54), c(1)=c(53)=0, c(2)=c(52), . . . ), this therefore implies 14 multiplications.

[0077] FIG. 3 illustrates a particular embodiment of the DDC 10 illustrated in FIG. 2.

[0078] The DDC 10 in this embodiment comprises a distributor 15 adapted for receiving the samples z(n) at the frequency F.sub.e=800 MHz and for processing the samples N by N, with N=F.sub.e/F.sub.FPGA, here N=4.

[0079] The processing of this distributor 15 comprises the provision in parallel of each of these N samples at the input of the route V.sub.I and the provision in parallel of each of these N samples at the input of the route V.sub.Q.

[0080] The route V.sub.I of the DDC 10 thereby comprises N sub-routes V.sub.I.sub._.sub.0, V.sub.I.sub._.sub.N-1.

[0081] Each sub-route V.sub.I.sub._.sub.i i=0 to N−1, selectively receives the samples z(kN+i), with k being a natural integer.

[0082] Each sub-route V.sub.I.sub._.sub.i is adapted for carrying out in parallel the other sub-routes of the route V.sub.I, frequency transposition in a base band by multiplication with cos(2π f.sub.0t.sub.n) in a transposition block in a base band 11.sub.I.sub._.sub.i and the FIR filtering by a filtering block 12.sub.I.sub._.sub.i.

[0083] Similarly, the route V.sub.Q of the DDC 10 thereby comprises N sub-routes V.sub.Q.sub._.sub.0, . . . , V.sub.Q.sub._.sub.N-1.

[0084] Each sub-route V.sub.Q.sub._.sub.i i=0 to N−1, selectively receives the samples z(kN+i), with k being a natural integer.

[0085] Each sub-route V.sub.Q.sub._.sub.i is adapted for carrying out in parallel the other sub-routes of the route V.sub.Q, the frequency transposition in a base band by the multiplication by −sin(2π f.sub.0t.sub.n) in a transposition block in a base band 11.sub.Q.sub._.sub.i, and the FIR filtering by a filtering block 12.sub.Q.sub._.sub.i.

[0086] The filtering blocks 12.sub.Q.sub._.sub.1 and 12.sub.Q.sub._.sub.3 are further adapted for calculating and storing in memory the intermediate results, for example in shift registers and communicating between them these intermediate results, for example via input/output means of said access registers.

[0087] In the relevant particular case with the values indicated above for p and the frequencies, because F.sub.e/f.sub.0=4, it is found that the base band transposition on the sub-routes V.sub.I.sub._.sub.1, V.sub.I.sub._.sub.3, V.sub.Q.sub._.sub.0, and V.sub.Q.sub._.sub.2 always delivers a zero value. Accordingly, in the relevant particular case, the DDC 10 only includes in reality in each of the routes V.sub.I and V.sub.Q N/2=2 sub-routes: V.sub.I.sub._.sub.0 and V.sub.I.sub._.sub.2 in the route V.sub.I and V.sub.Q.sub._.sub.1 and V.sub.Q.sub._.sub.3 in the route V.sub.Q.

[0088] In the relevant embodiment, because F.sub.e/f.sub.0=4, t.sub.n=n/F.sub.e and signals received on each sub-route: [0089] on route V.sub.I.sub._.sub.0, multiplication by cos(2π f.sub.0t.sub.n) in the transposition block in a base band 11.sub.I.sub._.sub.0 is equivalent to the multiplication by a factor 1; [0090] on route V.sub.I.sub._.sub.2, the multiplication by cos(2π f.sub.0t.sub.n) in the transposition block in a base band 11.sub.I.sub._.sub.2 is equivalent to the multiplication by a factor −1; [0091] on the route V.sub.Q.sub._.sub.1, the multiplication by −sin (2π f.sub.0t.sub.n) in the transposition block in a base band 11.sub.Q.sub._.sub.1 is equivalent to the multiplication by a factor −1; [0092] on the route V.sub.Q.sub._.sub.3, the multiplication by −sin(2π f.sub.0t.sub.n) in the transposition block in a base band 11.sub.Q.sub._.sub.3 is equivalent to multiplication by a factor 1.

[0093] On the sub-routes V.sub.I.sub._.sub.0 and V.sub.I.sub._.sub.2, application of the filtering is equivalent to the application of a delay by applying the transfer function z.sup.−13: if the output of the filter on the sub-route V.sub.I.sub._.sub.0 is called I.sub.0 and the output of the filter on the sub-route V.sub.I.sub._.sub.2 is called I.sub.2: I.sub.0(n=4k)=z(n−14) and I.sub.2(n=4k+2)=z(n−12). Indeed, the theoretical delay corresponds to p−1 (=26) as indicated earlier divided by two subsequent to the decimation operation, i.e. (p−1)/2 (=13); as the filtering calculation on the route Q lasts for a longer time than 13 clock cycles, the route I is further delayed so as to be synchronized with the route Q.

[0094] The samples from the passing in the base band of route V.sub.Q.sub._.sub.1 and of the route V.sub.Q.sub._.sub.3 are provided at the input of each FIR filtering block 12.sub.Q.sub._.sub.1 and 12.sub.Q.sub._.sub.3.

[0095] The filtering block 12.sub.Q.sub._.sub.1 on the sub-route V.sub.Q.sub._.sub.1 is adapted for determining the result of the linear combination; if the output of the filter on the sub-route V.sub.Q.sub._.sub.1 is called Q.sub.1 I:

Q.sub.1(n=4k+1)=−c(0)z(4k+1)+c(2)z(4k−1)−c(4)z(4k−3) . . . +c(26)z(4k−25)−c(26)z(4k−27) . . . −c(0)z(4k−53).

[0096] To do this, it is adapted for calculating each term of the first half of the linear combination, i.e. the terms c(0)z(4k+1), c(2)z(4k−1), c(4)z(4k−3) . . . , c(26)z(4k−25) depending on the coefficients of the filter c(0), c(26) and on the received base band samples z(4k+1), +z(4k−1) . . . , z(4k−25), and for storing in memory as an intermediate result the result of each of these terms. Each of these intermediate results stored in memory is made accessible additionally to the filtering block 12.sub.Q.sub._.sub.3.

[0097] The filtering block 12.sub.Q.sub._.sub.1 is further adapted for extracting from the memories in which they were stored previously, the terms of the second half of the linear combination, i.e. c(26)z(4k−27), c(24)z(4k−29), . . . ,c(0)z(4k−53), and for determining the sum of the terms of the first half and of the terms of the second half in return for taking into account the signs of these terms.

[0098] Similarly, the filtering block 12.sub.Q.sub._.sub.3 on the sub-route V.sub.Q.sub._.sub.3 is adapted for determining the result of the linear combination; if the output of the filter on the sub-route V.sub.Q.sub._.sub.3 is called Q.sub.3:

Q.sub.3(n=4k+3)=c(0)z(4k+3)−c(2)z(4k+1)+c(4)z(4k−1) . . . −c(26)z(4k−23)+c(26)z(4k−25) . . . +c(0)z(4k−51).

[0099] To do this, it is adapted for calculating each term of the first half of the linear combination, i.e. the terms c(0)z(4k+3), c(2)z(4k+1), c(4)z(4k−1) . . . , c(26)z(4k−23) depending on the coefficients of the filter c(0), . . . , c(26) and on the received base band samples z(4k+3), z(4k+1) . . . , −z(4k−23), and for storing in memory as an intermediate result the result of each of these terms. Each of these intermediate results stored in memory is made further accessible to the filtering block 12.sub.Q.sub._.sub.1.

[0100] The filtering block 12.sub.Q.sub._.sub.3 is further adapted for extracting from the memories in which they were stored previously, the terms of the second half of the linear combination, i.e. c(26)z(4k−25), c(24)z(4k−27), . . . ,c(0)z(4k−51), and for determining the sum of the terms of the first half and of the terms of the second half in return for the taking into account of the signs of these terms.

[0101] The DDC 10 thus delivers simultaneously at the output of the route I, the samples I.sub.0(n=4k) et I.sub.2(n=4k+2), and, at the output of the route Q, the samples Q.sub.1(n=4k+1) and Q.sub.3(n=4k+3).

[0102] It is considered that the even samples I of the DDC 10 are provided by the sub-route I.sub.0, that the odd samples I of the DDC 10 are provided by the sub-route I.sub.2, that the even samples Q of the DDC 10 are provided by the sub-route Q.sub.1, that the odd samples Q of the DDC 10 are provided by the sub-route Q.sub.3.

[0103] The invention proposes, according to an aspect, a processing method in a frequency converter.

[0104] In an embodiment, with reference to FIG. 4, the following steps are applied.

[0105] In a step 101, the samples z(n) at the frequency F.sub.e=800 MHz are received in the DDC 10 and provided in parallel, N per N, as an input to the route V.sub.I and as an input to the route V.sub.Q.

[0106] In a step 102, in each sub-route V.sub.P.sub._.sub.i in parallel with the other sub-routes of the route V.sub.I, the base band frequency transposition by multiplication by cos(2π f.sub.0t.sub.n) in a base band transposition block 11.sub.I.sub._.sub.i is carried out, P=I or Q and i=0 to N−1.

[0107] Each sub-route V.sub.P.sub._.sub.i selectively receives the samples z(kN+i), with k being a natural integer.

[0108] The samples from the transposition carried out in a sub-route V.sub.P.sub._.sub.i are provided to the other sub-routes of the same route V.sub.P.

[0109] In a step 103, in each sub-route V.sub.P.sub._.sub.i in parallel with the other sub-routes of the route V.sub.P, the filtered samples P(kN+i) are determined by means of the formula P(kN+i)=c(0).Math.x(kN+i)+c(1).Math.x(kN+i−1)+c(2).Math.x(kN+i−2)+ . . . −c(p).Math.x(kN+i−p)+c(p).Math.x(kN+i−p−1) . . . +c(1).Math.x(kN+i−2.Math.p+1)+c(0).Math.x(kN+i−2.Math.p), wherein x(n) is the result of the frequency transposition of the sample z(n).

[0110] The intermediate results determined in each sub-route are stored in memory and communicated and/or accessible between sub-routes of a same route for reuse in steps for determining the values of the filtered samples of a higher rank.

[0111] In step 104, the samples I.sub.0(n=4k) and I.sub.2(n=4k+2) and, at the output of the route Q, the samples Q.sub.1(n=4k+1) and Q.sub.3(n=4k+3) are simultaneously delivered at the output of the DDC 10.

[0112] Of course, the specific embodiments described above with reference to FIG. 3 may also be implemented by the method according to the invention.

[0113] The converter according to the present invention therefore gives the possibility of processing in a continuous flow the sampled real samples at F.sub.e, here 800 MHz, at the frequency F.sub.FPGA for processing FGPA, here 200 MHz, delivering a continuous flow and in real time of samples I at F.sub.e/2, here 400 MHz, and delivering a continuous and real time flow of samples Q to F.sub.e/2.

[0114] Again with reference to the graph of FIG. 1, the area covered by points Z2 is the area which may be utilized in continuous and real time processing according to the invention. The limitation brought by the sampling frequency which may be used for continuous and real time processing corresponds to the maximum sampling rate of the analogue/digital converter upstream from the frequency converter and is no longer limited by the FPGA.

[0115] The parallelization of the processing operations on several sub-routes I and several sub-routes Q, the utilization of the properties of the filter and of the storage in memory and reuse of the intermediate results give the possibility both of carrying out the processing operations at reduced rates, which the FPGAs may support, and of limiting the number of required resources.

[0116] It will be noted that the parallelization of the processing operations on several sub-routes I and several sub-routes Q may be applied in a converter according to the invention, and this without applying storage in memory and reuse of the intermediate results.

[0117] Conversely, the storage in memory and reuse of the intermediate results making use of the properties of the symmetrical filters may be applied in a frequency converter according to the invention without applying parallelization of the processing operations on several sub-routes I and several sub-routes Q. In particular, an application was described above to a frequency converter of the down type, but the utilization of the properties of the symmetrical filters according to the invention may in another embodiment be applied in a up type frequency converter.

[0118] In the particular embodiment described above as a reference, a transposed frequency f.sub.0 of 200 MHz, a sampling frequency F.sub.e of 800 MHz and a processing frequency F.sub.FPGA of 200 MHz were considered. However, the invention may be applied for other values of these frequencies.

[0119] As N is equal to the quotient F.sub.e/F.sub.FPGA, the processing will be typically parallelized on N routes for the route I, and on N routes for the route Q. The processing frequency F.sub.FPGA thus sets the number N of parallel routes to be set into place, which may thus be equal notably to a power of 2: 2, 4, 8, 16 etc.

[0120] In embodiments, the value of the transposed frequency f.sub.0, will further be set equal to F.sub.e/4, like in the particular embodiment described, so that all the samples delivered by certain of these parallel routes are systematically zero, so as to thus achieve in a simple way decimation and reduce the number of parallel sub-routes.

[0121] Moreover the relevant FIR filter had normalized coefficients relatively to the central coefficient and was symmetrical. The proposed implementation gives the possibility of easily modifying the number of its coefficients. The value of the latter depends on the sampling frequency F.sub.e and is therefore to be adapted accordingly. In other embodiments, the coefficients are not normalized, the reuse of the intermediate results may of course be also applied in this case.

[0122] In the case of an embodiment of the invention with a non-symmetrical FIR filter, the intermediate results may not be reused. In this case, the number of multipliers required for applying the filtering is doubled.