AN ARRAY SUBSTRATE, ITS MANUFACTURING METHOD THEREOF AND A LIQUID CRYSTAL DISPLAY PANEL

Abstract

A manufacturing method of an array substrate is provided in this invention, a protective layer for the channel is formed by magnetron sputtering and thermal annealing treatment with the oxygen concentration greater than 21%, at a temperature of 300˜400° C. and the material of the protection layer includes Al.sub.2O.sub.3. The present invention further includes an array substrate and a liquid crystal display panel with the array substrate. The present invention prevents the impurity such as hydrogen atom into the channel, and the quality of the protective layer prepared by the present invention is higher to ensure the electrical properties of the channel and process easy to be achieve and conducive to industrialization.

Claims

1. A manufacturing method for an array substrate comprising: forming a first metal layer, an insulation layer and a semiconductor pattern layer subsequently; forming a second metal layer on the insulation layer and the semiconductor pattern layer, wherein the region of the second metal layer is an Al layer that corresponding to the semiconductor pattern layer, and the Al layer is formed by magnetron sputtering process; performing a thermal annealing treatment with the oxygen concentration greater than 21%, at a temperature of 300˜400° C., to make the Al layer have an oxidation reaction into a Al.sub.2O.sub.3 layer; etching the second metal layer with Al.sub.2O.sub.3 layer to obtain a protective layer having a predetermined size on the semiconductor pattern layer; and forming a third metal layer on the Al.sub.2O.sub.3 layer, the third metal layer is formed with a recess, and the recess exposed the corresponding Al.sub.2O.sub.3 layer.

2. The manufacturing method according to claim 1, wherein the first metal layer is the gate electrode of the thin film transistor of the array substrate, the third metal layer is the source and drain electrode layer of the thin film transistor, and the source electrode and a drain electrode are located on both sides of the protective layer.

3. The manufacturing method according to claim 1, further comprising forming a passivation layer on the exposed Al.sub.2O.sub.3 layer and the third metal layer.

4. The manufacturing method according to claim 3, wherein the passivation layer is formed on the exposed Al.sub.2O.sub.3 layer and the third metal layer by the method of chemical vapor deposition, atomic layer epitaxy, coating, sputtering, evaporation and any combination thereof.

5. The manufacturing method according to claim 4, wherein the material of the passivation layer and the second metal layer is different.

6. The manufacturing method according to claim 4, wherein the material of the passivation layer and the second metal layer is the same.

7. An array substrate comprising: a base substrate; a first metal layer, an insulation layer and a semiconductor pattern layer subsequently formed; a protective layer formed on the semiconductor pattern layer, wherein the surface of the protective layer is an Al.sub.2O.sub.3 layer, wherein the Al.sub.2O.sub.3 layer is formed by a magnetron sputtering made Al layer, and into the Al.sub.2O.sub.3 layer by thermal annealing treatment with the oxygen concentration greater than 21%, at a temperature of 300˜400° C.; and a third metal layer formed on the Al.sub.2O.sub.3 layer, the third metal layer is formed with a recess, and the recess exposed the corresponding Al.sub.2O.sub.3 layer.

8. The array substrate according to claim 7, wherein the first metal layer is the gate electrode of the thin film transistor of the array substrate, the third metal layer is the source and drain electrode layer of the thin film transistor, and the source electrode and a drain electrode are located on both sides of the protective layer.

9. A liquid crystal display panel comprising an array substrate, a color filter substrate disposed opposite to the array substrate and a liquid crystal interposed between the array substrate and the color filter substrate wherein the array substrate comprising: a base substrate; a first metal layer, an insulation layer and a semiconductor pattern layer subsequently formed; a protective layer formed on the semiconductor pattern layer, wherein the surface of the protective layer is an Al.sub.2O.sub.3 layer, wherein the Al.sub.2O.sub.3 layer is formed by a magnetron sputtering made Al layer, and into the Al.sub.2O.sub.3 layer by thermal annealing treatment with the oxygen concentration greater than 21%, at a temperature of 300˜400° C.; and a third metal layer formed on the Al.sub.2O.sub.3 layer, the third metal layer is formed with a recess, and the recess exposed the corresponding Al.sub.2O.sub.3 layer.

10. The liquid crystal display panel according to claim 9, wherein the first metal layer is the gate electrode of the thin film transistor of the array substrate, the third metal layer is the source and drain electrode layer of the thin film transistor, and the source electrode and a drain electrode are located on both sides of the protective layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following detailed descriptions accompanying drawings and the embodiment of the present invention make the aspect of the present invention and the other beneficial effect more obvious.

[0015] FIG. 1 illustrates the manufacturing process flow of the array substrate according to the first embodiment of the present invention;

[0016] FIG. 2 illustrate the schematic diagram according to the manufacturing method of FIG. 1 of the first embodiment of the present invention;

[0017] FIG. 3 illustrate the schematic diagram according to the manufacturing method of FIG. 1 of the first embodiment of the present invention;

[0018] FIG. 4 illustrate the schematic diagram according to the manufacturing method of FIG. 1 of the first embodiment of the present invention;

[0019] FIG. 5 is a cross-sectional view of the liquid crystal display apparatus in the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The specific components or items are used in the specification and claims. Those skilled in the art can use other possible modifications and variations in the same components or items. The specification and claim will not distinguish the different terms to the items or components but by the functions. Following is the detail description illustrated by the figures and the embodiments.

[0021] FIG. 1 illustrates the manufacturing process flow of the array substrate according to the first embodiment of the present invention. The manufacturing method is used to form the protective layer on the IGZO channel of the TFT. The primary role of the protective layer is to prevent water molecules and oxygen molecules into the channel and contacts IGZO channel to ensure the electrical properties of the IGZO channel, and therefore the protective layer may also be referred to as an aqueous oxygen barrier layer or an etch stop layer, ESL. Referring to FIGS. 1-5, the manufacturing method steps includes:

[0022] S11: a first metal layer, an insulation layer and a semiconductor pattern layer are formed subsequently on the base substrate.

[0023] Referring to FIG. 2, the base substrate 21 is used to form an array substrate. So the material of the base substrate 21 can be glass, transparent plastic material or a flexible substrate.

[0024] The first metal layer 22 can be formed on the base substrate 21 by sputtering, to form a gate electrode of the TFT with a predetermined pattern. Due to the source electrode and drain electrode of the TFT is subsequent formed, the insulation layer 23 is formed on a base substrate 21 such as Gate Insulation Layer, GI.

[0025] The semiconductor pattern layer 24 formed on the insulation layer 23 is an amorphous oxide semiconductor layer having a predetermined pattern. The material of the semiconductor pattern layer 24 includes, but not limited to IGZO, ITZO (InSnZnO). Embodiments of the present invention can be used includes, but not limited to, phosphoric acid, nitric acid, acetic acid and deionized water solution for etching the entire layer of the semiconductor pattern layer on the insulation layer 23, to thereby obtain a semiconductor pattern layer 24 having a predetermined pattern, of course, in other embodiments, dry etching may be used, but not limited thereto.

[0026] S12: a second metal layer is formed on the insulation layer and the semiconductor pattern layer.

[0027] The area of the second metal layer corresponding to the semiconductor pattern layer is an Al layer, and the Al layer is formed by magnetron sputtering.

[0028] As illustrated in FIG. 3, the second metal layer 25 is used to obtain the protective layer of the IGZO channel in this embodiment. In a preferred embodiment, the second metal layer 25 is formed by magnetron sputtering at a temperature of 300˜400° C. to form the Al layer. Of course, in other embodiments, the second metal layer 25 may be provided only on the surface of the Al layer with a predetermined thickness, or only provide an Al layer corresponding on the surface of the semiconductor pattern layer 24 in a predetermined thickness, a base layer is formed below the Al layer using a predetermined manner, the material of the base layer in the present invention is not to be limited.

[0029] The impurity such as hydrogen atom and the like will not produce during forming the Al layer by magnetron sputtering process, so comparing to the chemical vapor deposition method or a Plasma Enhanced Chemical vapor deposition, PECVD, the embodiment of the present invention not only can reduce the damage of the IGZO channel, but can also avoid the incorporation of impurities, a hydrogen atom and the like into the semiconductor pattern layer 24, such as the IGZO channel, so as to ensure the electrical properties of the IGZO channel.

[0030] Besides, the magnetron sputtering process is simple and easy to achieve, and the efficiency is higher than the chemical vapor deposition methods and/or the plasma enhanced chemical vapor deposition, and is conducive to industrialization.

[0031] S13: a thermal annealing treatment is performed with the oxygen concentration greater than 21%, in an atmosphere and at a temperature of 300˜400° C., to make the Al layer have an oxidation reaction into a Al.sub.2O.sub.3 layer.

[0032] Referring to FIG. 3, the Al atoms of the Al layer such as the second metal layer 25 have an oxidation reaction in the oxygen O.sub.2 concentration greater than 21% of the oxygen-enriched atmosphere, it is possible to generate the greatest degree of Al.sub.2O.sub.3 layer 26, while 300 to 400° C. temperature can promote the oxidation reaction, to the greatest degree to assure the density of the Al.sub.2O.sub.3 layer 26 is formed, by the high film quality to further ensure the electrical properties of the channel IGZO.

[0033] In the embodiment of this invention, the three function of the thermal annealing treatment in an oxygen-rich atmosphere are as followed: First, to reduce the defect density of the IGZO active layer such as IGZO channel, by mainly reduce the oxygen vacancy concentration, to obtain a good electrical characteristics of the active layer. the second is to repair the damage of the second metal layer 25 during deposition and patterning process, magnetron sputtering and etching process on the channel active layer. The third is to oxide the Al layer to Al.sub.2O.sub.3 layer 26 with higher quality, to form a channel protective layer.

[0034] S14: etching the second metal layer with Al.sub.2O.sub.3 layer to obtain a protective layer having a predetermined size on the semiconductor pattern layer.

[0035] Continuing referring to FIG. 3, the Al.sub.2O.sub.3 layer 26 is etched, an embodiment of the present invention may be employed include, but not limited to wet etching, dry etching, etc. The predetermined size is the size of the IGZO TFT channel, protective layer as shown as Al.sub.2O.sub.3 layer 26 with the predetermined size is a protective layer of the IGZO channel.

[0036] S15: a third metal layer is formed on the Al.sub.2O.sub.3 layer, the third metal layer is formed with a recess, and the recess is exposed Al.sub.2O.sub.3 layer of the corresponding region.

[0037] Referring to FIG. 4, the third metal layer 27 is the source and drain electrode layer of the TFT, including a source electrode 271 and a drain electrode 272, the source electrode 271 and a drain electrode 272 are located on both sides of the protective layer.

[0038] Further, the manufacturing method of the present embodiment of the invention further including: forming a passivation layer 28 on the exposed Al.sub.2O.sub.3 layer, the Al.sub.2O.sub.3 layer 26 in a predetermined size and on the third metal layer 27. Wherein, the passivation layer 28 can be formed on the exposed Al.sub.2O.sub.3 layer and the third metal layer 27 by the method of chemical vapor deposition, atomic layer epitaxy, coating, sputtering, evaporation and any combination thereof. Further, the material of the passivation layer 28 and the second metal layer 25 can be the same or different.

[0039] Embodiments of the present invention also includes to provide an array structure shown in FIG. 4 by the manufacturing method mentioned above. The manufacturing method of the other structures on the array substrate can be found in the conventional technology.

[0040] A liquid crystal display panel is also provided in the embodiments of the present invention, as shown in FIG. 5, the liquid crystal display panel 50 including the above array substrate 10, a color filter substrate 51 disposed opposite to the array substrate 10 and a liquid crystal 52 interposed between the array substrate 10 and the color filter substrate 51.

[0041] It will be apparent to those having ordinary skill in the art that various modifications and variations can be made to the devices in accordance with the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

[0042] Although the drawings and the illustrations above are corresponding to the specific embodiments individually, the element, the practicing method, the designing principle, and the technical theory can be referred, exchanged, incorporated, collocated, coordinated except they are conflicted, incompatible, or hard to be put into practice together.

[0043] Although the present invention has been explained above, it is not the limitation of the range, the sequence in practice, the material in practice, or the method in practice. Any modification or decoration for present invention is not detached from the spirit and the range of such.