Methods to Deal with Insufficient Memory Protection Unit (MPU) Regions

Abstract

This invention presents methods to utilize more regions for tasks than the number of slots in a memory protection unit and to efficiently distribute regions between multiple tasks within a partition.

Claims

1. Methods to utilize more regions for tasks than the number of slots in a memory protection unit and to efficiently distribute said regions between multiple tasks within a partition, consisting of: offsetting said memory protection arrays from said memory protection unit such that lower memory protection unit slots are static and the upper memory protection unit slots are active, wherein static means loaded one time during initialization and active means loaded from a task memory protection array whenever said task starts running and where the sum of static and active slots is the number of memory protection array slots; defining regions to satisfy the requirements for code and data in said partition then putting said regions into an array of regions called a partition template where such partition template may have more regions than the number of slots in said memory protection unit; defining child tasks to perform subfunctions for said partition, each said child task requiring a subset of said partition regions for which said memory protection unit has sufficient slots; creating a main partition task, which creates said child tasks; creating said memory protection arrays by using bit masks to select regions from said partition template for all said tasks.

2. The method of claim 1 wherein there is no said static region if said active region utilizes the whole said memory protection unit.

3. The method of claim 1 wherein said memory protection arrays may have auxiliary slots and the number of said slots may vary from task to task.

4. The method of claim 3 wherein a said auxiliary slot may contain an expansion region and wherein a region load function is provided to load said region into a said active slot of said memory protection unit and into said memory protection array, thus allowing said current task to access said expansion region.

5. The method of claim 4 wherein multiple expansion regions are present in said auxiliary slots of said memory protection array and one of said expansion regions is loaded ahead of said task code that requires it, and this process can be repeated for a multiplicity of said expansion regions, as needed, thereby increasing the number regions that said current task can access beyond the number of said memory protection unit slots.

6. The method of claim 5 used for input/output regions, which tend to be small and used only in small sections of code, yet said partition may need to access several said input/output regions at different times.

7. The method of claim 5 wherein said expansion regions used in ptasks make the transition to utasks easier since said utasks usually require less regions.

8. The method of claim 5 wherein the places in said source code where said expansion regions must be loaded into said memory protection unit and said memory protection array can be found from memory manage faults occurring when said task runs.

9. The method of claim 5 wherein said current task may be preempted and will resume with the said expansion region in said memory protection unit because said expansion region was also loaded into said memory protection array of said current task.

10. The method of claim 3 wherein said auxiliary slot may contain a phantom region, which is a subregion of a region in said active slot of said memory protection unit and thus accessible by said current task and said phantom region is shared with a task in another partition which loads said subregion into an active slot in its memory protection array in order to exchange data between said tasks.

11. The method of claim 1 wherein said bit mask has a bit for each region of said partition template, and each time said bit mask is shifted right, if a 1 is shifted out, the corresponding region in said partition template is loaded into the current slot of said memory protection array and each time a 0 is shifted out said template region is skipped and after each said shift, said partition template pointer is incremented and if said memory protection array slot was loaded, its pointer is incremented and if said bit mask becomes 0, remaining said memory protection array slots are loaded with a NULL region.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1 shows the preferred embodiment of the inventive material herein.

[0022] FIG. 2 illustrates MPU operation. Each region in the MPU allows access to a specific memory region with attributes, as shown.

[0023] FIG. 3 illustrates one possible relationship between an MPU and a Memory Protection Array (MPA) and shows the resulting static, active, and auxiliary slots.

[0024] FIG. 4 illustrates an MPA for a ptask.

[0025] FIG. 5 illustrates the equivalent MPA for a utask that has the same code as the ptask.

[0026] FIG. 6 shows a partition with a partition template, a parent or main task and three child tasks.

[0027] FIG. 7 shows loading two task MPAs from a partition template.

DETAILED DESCRIPTION

[0028] The following information describes a simple embodiment of the invention sufficient to explain how it works. The term “application” is understood to mean the software in an embedded device that performs the functions of that device. FIGS. 1 and 2 illustrate the structure and operation of the preferred embodiment. They are for reference, only, and not part of the inventive material.

[0029] FIG. 1 shows the preferred embodiment of this invention consisting of processor 101 sending a memory address 102 to a Memory Protection Unit (MPU) 103. The MPU 103 compares the address 102 to its regions and passes the address on to the system address bus 105 if it is ok. Otherwise, MPU 103 sends a Memory Mange Fault (MMF) exception 106 back to processor 101 and no access to memory nor FO occurs.

[0030] If ok, address 102 is sent to Read/Write Memory 108, Read-Only Memory 109, and I/O Device 110 and any other memories or devices connected to address bus 105. Whichever of these devices recognizes the address then receives data from processor 101 via system data bus 107 or sends data to processor 101 via system data bus 107.

[0031] FIG. 1 also shows that MPU 103 is loaded from Memory Protection Array (MPA) 112 at the time that its task 111 starts running on processor 101. Each task 111 has its own MPA 112, which contains the regions that it is allowed to access.

[0032] It should be apparent, to one skilled in the art, that other embodiments are possible, such as: multiple processors (either multiple cores on the same chip or multiple processors on different chips), multiple MPUs each connecting to the same or to different system buses, multiple system buses, and other types of memory.

[0033] FIG. 2 illustrates typical MPU operation. It shows task 201 sending an address to MPU 211 having 4 regions, as follows: Region 202 addresses task code read-only region 207 in memory 212. Region 203 addresses common code read-only region 208. Region 204 addresses data read/write, execute-never region 209. Region 205 addresses stack read/write, execute-never Region 210. An address that does not fall into one of these regions or does not have the correct attributes goes to the Memory Manage Fault Handler (MMF) 206. Otherwise, task 201 is allowed to read or write the desired data.

[0034] For simplicity, FIG. 2 shows 4 MPU regions. However, it should be apparent, to one skilled in the art, that it applies equally to MPUs with 8, 16, or any other number of regions.

[0035] FIG. 3 Shows how MPU 301 and MPA 302 line up in one possible case. Here MPU slots 310 and 311 are static slots, which are not loaded from MPA 302 when a task switch occurs. Instead, they are loaded once by initialization code and typically contain system regions that are accessible only in pmode. MPU 301 active slots 304 thru 309 line up with MPA 302 slots 315 thru 320 and are loaded from them when a new task starts or resumes running.

[0036] Every task has its own MPA, which governs the regions that it can access. MPU 301 slot 304 is dedicated for the task stack region (every task has its own stack), slot 305 is dedicated for multiple IO regions, and slots 306 to 309 are used for current task regions. The small numbers in MPA 302 slots 315 to 320 are the corresponding MPU 301 slot numbers. This is required by the Cortex v7M MPU and is not generally needed by other MPUs.

[0037] MPA 302 slots 312 thru 314 are auxiliary slots. Slots 312 and 313 contain IO expansion regions. Either IO1 region in slot 312 or IO2 region in slot 313 can be selected 303 and loaded into MPU 301 slot 305 and into MPA 302 slot 316, depending upon which IO region is needed at a particular place in the code of the current task. MPA 302 slot 314 contains a phantom region. It contains region pmsg, which is a subregion of one of the regions in MPU 301 slots 304 to 309. Hence, the current task can access it. This subregion is made available to other partitions as a region that they are allowed to access for the purpose of exchanging data. It is the basis for tunnel partitions discussed in a concurrent application by this author.

[0038] Hence, in this particular example, the current task is able to access three more regions than MPU 301 would normally permit. It should be apparent to one skilled in the art that the foregoing is just one example of regions for a particular task and that other tasks may have different regions that suit their requirements.

[0039] FIG. 4 shows MPA 401 for a ptask. Slots 402 and 403 contain privileged system regions. Unlike FIG. 3, MPA 401 is not offset from the MPU, hence slots 402 and 403 are active slots corresponding to MPU slots 0 and 1, respectively. Similarly to FIG. 3, slots 411 and 413 contain IO expansion regions, either of which can be selected 413 to be loaded into IO slot 404, as needed. Slots 405 thru 408 are for ptask regions. Slot 409 has the task stack region. It corresponds to the top MPU slot 7. Slot 410 contains a phantom region, the pmsg region.

[0040] FIG. 5 shows MPA 501 for the equivalent utask. MPA 501 is the utask equivalent of MPA 401 for a ptask. The utask is the same as the ptask, except that it is now running in umode. Note that sys_code in slot 402 had been replaced with svc_code in slot 502. svc_code contains functions necessary in umode, whereas sys_code contains functions necessary in pmode. Note that sys data in slot 403 is not necessary in umode. Hence slot 503 contains IO1 and slot 504 contains IO2. These regions have been moved from auxiliary slots 411 and 412, respectively, which are no longer needed. Slots 505 thru 509 contain the same regions as slots 405 thru 409, respectively. Now there is only one auxiliary slot 510 for pmsg. This figure illustrates how temporary auxiliary slots can be used for a ptask that become active slots when it is converted to a utask.

[0041] FIG. 6 Shows how child task A 605 and child task B 604 are spawned from parent task 603, all three using the partition template 602. In addition child task C 606 is spawned form its parent task 605 also using partition template 602. All tasks in partition 601 must use partition template 602, each with its own template mask, msk_, to select the regions that it needs.

[0042] FIG. 7 illustrates how partition template 701 loads MPA1 704 using mask M1 702 and loads MPA2 705 using mask M2 703. In the first case, template 701 regions 706 thru 709 are loaded into MPA1 704 regions 714 thru 717, respectively, because the corresponding mask M1 702 bits are 1's. The remaining mask bits are 0's so no further loading is done for MPA1 704. In the second case, template 701 regions 706 and 707 are loaded into MPA2 705 regions 718 and 719, respectively, because those bits in mask M2 703 are 1's. The next two bits in mask M2 703 are 0's so template 701 regions 708 and 709 are skipped. The template 701 regions 710 thru 713 are loaded into MPA2 regions 720 thru 723, respectively, because those bits in mask M2 703 are 1's. Note that template 701 has a mixture of active slots and auxiliary slots. As shown in FIG. 7, the hexadecimal value for mask M1 702 is 0x0F and for mask M2 703 it is 0xF3.

[0043] For simplicity, FIG. 7 shows MPAs with only 4 active slots. It should be apparent, to one skilled in the art, that the concept shown applies equally to larger numbers of active slots.

CONCLUSIONS, RAMIFICATIONS, AND SCOPE

[0044] As presented in the foregoing detailed descriptions, an MPU may be divided into static slots and active slots, if it has enough slots. The static slots are loaded during initialization and normally contain common regions and privileged regions used in pmode. The active slots correspond to the lower slots of the MPA from which the MPU is loaded when a new task starts or resumes. Thus the active slots contain regions specific to the current task, which is running. This structure improves performance and is appropriate for MPUs with a large number of slots, such as 16.

[0045] If the MPU has a moderate number of slots, such as 8, not only may there not be enough slots for static regions, there may not be enough slots for all active regions. As a consequence, it may be necessary to create larger regions or to share regions between partitions. Neither of these solutions is attractive because they reduce isolation between partitions and thus reduce system security. Unfortunately, the vast majority of MCUs in use have only 8-slot MPUs and some MCUs have only 4-slot MPUs. Hence, methods to employ more regions than available MPU slots are of great importance to achieve good security for MCU-based systems.

[0046] This invention adds auxiliary slots to a task's MPA. These can contain expansion regions and phantom regions that are specific to each task. Several expansion regions can share a single active MPU slot. When needed, the appropriate expansion region is loaded into the active MPU slot. Where in the code to place these region loads can be determined from Memory Management Faults (MMFs) when the task runs. Hence, neither redesign nor deep understanding of the code are necessary. Phantom regions are subregions of active regions. They are used to share data with other partitions and they do not require an active slot in the MPA of task of origin. This is the foundation for the tunnel portal presented in a concurrent application by this author.

[0047] An additional method of this invention to overcome insufficient MPU slots is to create a single partition template containing all regions needed by the partition code. These regions are based solely upon the code. The resulting template may be much larger than the available number of MPU slots. If so, special-purpose tasks are defined, each to execute a portion of the partition code, such that each task needs no more regions than there are MPU slots for it to use. These tasks are child tasks that are created by the main partition task, which becomes their parent task. A child task cannot do anything that its parent task cannot do, hence it is a proxy for the parent that is designed to reduce the regions needed by the parent.

[0048] Tasks are usually defined to perform certain functions, then writing the code follows. The unique idea here is that the partition code comes first, then the partition template that includes all regions needed by the code, then the tasks are defined to run the code such that the needed regions of each will fit into the MPU.