METHOD FOR DYNAMICALLY ASSIGNING MEMORY BANDWIDTH

Abstract

A method for dynamically assigning memory bandwidth to multiple processor units, which are connected via a data connection to a shared memory unit. In an initialization phase, each of the multiple processor units are assigned an initial value of a usable memory bandwidth, and a permissible range for a mean usage of the memory bandwidth is determined. Subsequently, the assigned memory bandwidths are checked repeatedly and adjusted if needed, a present value of a mean usage of the memory bandwidth by the multiple processor units being determined, and, if this present value is outside the permissible range, the values of the usable memory bandwidth are adjusted for at least a part of the multiple processor units.

Claims

1-12. (canceled)

13. A method for dynamically assigning memory bandwidth to multiple processor units which are connected via a data connection to a shared memory unit, the method comprising the following steps: in an initialization phase, assigning a respective initial value of a usable memory bandwidth to each of the multiple processor units and determining a permissible range for a mean usage of the memory bandwidth for each of the multiple processing units; subsequent to the initialization phase, repeatedly checking and, if needed, adjusting the assigned memory bandwidths, including determining a present value of the mean usage of the memory bandwidth by the multiple processor units, and, based on the present value being outside the permissible range, adjusting the respective values of the usable memory bandwidth for at least a part of the multiple processor units.

14. The method as recited in claim 13, wherein at least two of the multiple processor units are part of a processor unit group and are connected via a shared interface to the data connection.

15. The method as recited in claim 14, wherein at least one further one of the multiple processor units is individually connected via an interface to the data connection.

16. The method as recited in claim 13, further comprising: determining, within the scope of checking the memory bandwidths, the present value of a usage of the memory bandwidth by each of the processor units, and, when the present value of the usage of the memory bandwidth by a processor unit of the processor units exceeds the respective initial value and the processor unit is not used for a real-time calculation, stopping operation of the processor unit.

17. The method as recited in claim 16, further comprising: detecting one or multiple indicators for the usage of the memory bandwidth by each of the processor units and determining the present value of the usage of the memory bandwidth by each processor unit based on the one or multiple indicators.

18. The method as recited in claim 13, further comprising: adjusting, based om the present value of the mean usage of the memory bandwidth by the multiple processor units being outside the permissible range, adjusting the respective values of the memory bandwidth usable by processor units, which are not used for a real-time calculation, and maintaining the respective values of the memory bandwidth usable by processor units which are usable for a real-time calculation.

19. The method as recited in claim 13, further comprising, in the initialization phase, predefining at least one quality parameter for at least one of the multiple processor units and subsequently, based on the present value of the mean usage being outside the permissible range, adjusting the at least one quality parameter for the at least one of the multiple processor units.

20. The method as recited in claim 13, further comprising, in the initialization phase, assigning in each case a maximum required value including an initial buffer, as the initial value of the usable memory bandwidth to those of the processor units which are used for a real-time calculation.

21. The method as recited in claim 13, further comprising, in the initialization phase, assigning in each case a mean required value as the initial value of the usable memory bandwidth to those of the processor units which are not used for a real-time calculation.

22. A processing unit configured to dynamically assigning memory bandwidth to multiple processor units which are connected via a data connection to a shared memory unit, the processing unit configured to: in an initialization phase, assign a respective initial value of a usable memory bandwidth to each of the multiple processor units and determine a permissible range for a mean usage of the memory bandwidth for each of the multiple processing units; subsequent to the initialization phase, repeatedly check and, if needed, adjust the assigned memory bandwidths, including determining a present value of the mean usage of the memory bandwidth by the multiple processor units, and, based on the present value being outside the permissible range, adjusting the respective values of the usable memory bandwidth for at least a part of the multiple processor units.

23. A non-transitory machine-readable memory medium on which is stored a computer program for dynamically assigning memory bandwidth to multiple processor units which are connected via a data connection to a shared memory unit, the computer program, when executed by a processing unit, causing the processing unit to perform the following steps: in an initialization phase, assigning a respective initial value of a usable memory bandwidth to each of the multiple processor units and determining a permissible range for a mean usage of the memory bandwidth for each of the multiple processing units; subsequent to the initialization phase, repeatedly checking and, if needed, adjusting the assigned memory bandwidths, including determining a present value of the mean usage of the memory bandwidth by the multiple processor units, and, based on the present value being outside the permissible range, adjusting the respective values of the usable memory bandwidth for at least a part of the multiple processor units.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG. 1 schematically shows a system including processor units and memory units in which a method according to an example embodiment of the present invention may be carried out.

[0048] FIG. 2 schematically shows a sequence of a method according to the present invention in one preferred specific embodiment.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0049] FIG. 1 schematically shows a system in which a method according to the present invention may be carried out. System 100 includes processor units 122, 124, 126, 128, and 130, which are connected to a data connection 140, for example, a data bus. System 100 also includes a memory unit 142, for example, a DRAM, as a working memory, which is also connected to data connection 140. In this way, the processor units have access to the memory unit and may write data therein and read data therefrom. Memory unit 142 may also include a memory controller, which is used for activating the memory unit, moreover a QoS module 144 is provided. QoS module 144 is seated, for example, in the interconnect (partially also distributed to the masters) and not directly on the memory controller.

[0050] Processor units 122, 124, 126, and 128 together form a processor unit group 120 or are part of such a group. For example, processor unit group 120 may be a CPU (multicore CPU) or a CPU cluster, in which processor units 122, 124, 126, and 128 are processor cores. For example, processor units 122, 124 are to be provided or used for real-time calculations (so-called RTC), but not processor units 126, 128. Processor units 130 may be a GPU, for example. GPU 130 is also connected to data connection 140 via an interface 131, and CPU 120 is connected via an interface 121 shared by processor cores 122, 124, 126, 128. As already mentioned at the outset, GPU 130 may be used as a master, as may CPU 120 as a whole.

[0051] Furthermore, a processing unit 110 is shown as an example, on which a method according to the present invention is executed or implemented. As already mentioned, this may be a special processing unit, but the method—also referred to as a dynamic regulator—may also be implemented in an operating system or a hypervisor.

[0052] Furthermore, a hardware performance counter 150 is provided in each of processor units 122, 124, 126, 128, and 130 and in data connection 140 and memory unit 142, with the aid of which, for example, write and read accesses—typically also individually per source—are counted. Data acquired for this purpose may be transferred to processing unit 110 or read thereby.

[0053] FIG. 2 schematically shows a sequence of a method according to the present invention in one preferred specific embodiment. For this purpose, first an initialization phase 200 is shown, in which, in a step 202, an initial value U.sub.I of a usable memory bandwidth is determined and then assigned for each of the multiple or all processor units, for example, as shown in FIG. 1. By way of example, only one initial value U.sub.I is shown. In addition, various quality parameters P, for example, a number of the outstanding requirements, may be predefined.

[0054] In a step 204, a lower limiting value U.sub.min and an upper limiting value U.sub.max are then determined for a mean usage of the memory bandwidth, which together form a range for the mean usage of the memory bandwidth. In a step 206, a duration Δt.sub.1 for subsequent supervision phases may be determined and in a step 208, a duration Δt.sub.2 for subsequent regulating phases may be determined.

[0055] After the end of initialization phase 200, the operation of the system may take place in a regular way and checks and possibly changes of assigned memory bandwidths take place repeatedly. As already mentioned, this may take place by way of alternating supervision phases 220 and regulating phases 240.

[0056] In a supervision phase 220, in a step 222, initially indicators I or values thereof are detected, on the basis of which, in a step 224, a present value U.sub.A of the usage of the memory bandwidth is calculated, specifically individually for each processor unit. It is possible that this only takes place for non-real-time processor units. Nonetheless, however, these may also be incorporated. This may be of interest, for example, if they are soft real-time processor units and a minimal quality of the non-real-time cores does not necessarily have to be or should not be maintained. For example, the number of the read and/or write processes, which the individual processor units carry out on the memory unit, comes into consideration as indicators I. Counters 150 shown in FIG. 1 may be used for this purpose.

[0057] In a step 226, it is checked whether present value U.sub.A is greater than initial value U.sub.I for the (assigned) usage of the memory bandwidth. If this is so, the affected processor unit is stopped in step 228, otherwise it is still left in operation according to step 230. It is ensured in this way that the memory bandwidth, as intended, is no longer utilized. However, this also applies in particular only for processor units which do not have to carry out real-time calculations. Carrying out real-time calculations thus remains ensured. However, as already mentioned, soft real-time processor units may possibly be taken into consideration here, which possibly do not have to be operated further.

[0058] In subsequent regulating phase 240, a mean or average value U.sub.M is ascertained in a step 242. Individual values U.sub.A from step 224 may be used for this purpose, for example. The arithmetic mean value may be formed for this purpose, for example. It is then checked whether present mean value U.sub.M is outside the permissible range.

[0059] For this purpose, in step 244, initially a comparison to lower limiting value U.sub.min is carried out. If present mean value U.sub.M is less than U.sub.min, in step 246, the values for the processor units (if this is the first adjustment, these are the initial values) may be increased, thus each adjusted to new values U*.

[0060] If this does not apply, in step 248, a comparison to upper limiting value U.sub.max is carried out. If present mean value U.sub.M is greater than U.sub.max, in step 250, the values for the processor units (if this is the first adjustment, these are the initial values) may be reduced, thus each adjusted to new values U*.

[0061] If this also does not apply, the values thus remain unchanged according to step 252. The adjustment of the values may take place similarly as in the initialization phase during the determination of the initial values, however, an adjustment by a predefined amount or also an amount dependent on a difference of the mean value from lower or upper limiting value is also possible.

[0062] The supervision phase may subsequently begin again. However, it is also possible to wait a certain duration until it is carried out again. In this way, the individual memory bandwidths for the processors are dynamically adjusted and the entire memory bandwidth is efficiently utilized.