A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.

Methods, systems, and devices for adjusting a granularity associated with read disturb tracking are described. In some examples, a memory system may receive a set of read commands from a host system instructing the memory system to read data stored at a memory array. The memory system may track a quantity of executed read commands corresponding to a first portion of the memory array according to a first granularity and determine whether the quantity of read commands satisfies a threshold. If the quantity of read commands satisfies the threshold, the memory system may adjust the granularity for tracking executed read commands for the first portion from the first granularity to a second granularity. For example, the memory system may increase or decrease the granularity for tracking executed read commands for the first portion. The memory system may use the tracked quantities of executed read commands for read disturb remediation.

Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.

Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

Implementations disclosed describe methods and systems to perform the methods of optimizing a size of memory used for accumulation of neural node outputs and for supporting multiple computational paths in neural networks. In one example, a size of memory used to perform neural layer computations is reduced by performing nodal computations in multiple batches, followed by rescaling and accumulation of nodal outputs. In another example, execution of parallel branches of neural node computations include evaluating, prior to the actual execution, the amount of memory resources needed to execute a particular order of branches sequentially and select the order that minimizes this amount or keeps this amount below a target threshold.

A method for computational storage may include storing, at a storage device, a first portion of data, wherein the first portion of data may include a first fragment of a record, and a second portion of data may include a second fragment of the record, and appending the second fragment of the record to the first portion of data. The method may further include performing, at the storage device, an operation on the first and second fragments of the record. The method may further include determining that the first portion of data may include a first fragment of a record, and a second portion of data may include a second fragment of the record, wherein appending the second fragment of the record to the first portion of data may include appending, based on the determining, the second fragment of the record to the first portion of data.

One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.

A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.