METHOD FOR MANUFACTURING A CARRIER SUBSTRATE ON A SEMICONDUCTOR WAFER AND DEVICE INCLUDING A SEMICONDUCTOR WAFER

Abstract

A method for manufacturing a carrier substrate on a semiconductor wafer that includes a front side and a rear side, the front side being situated opposite the rear side, the front side representing a structured semiconductor wafer side including contact areas. The method includes the following steps: applying at least one first layer to the front side with the aid of printing technology, the at least one first layer including a first material that is water-insoluble, and curing the at least one first layer with the aid of UV radiation, thermally or with the aid of sintering.

Claims

1-10. (canceled)

11. A method for manufacturing a carrier substrate on a semiconductor wafer that includes a front side and a rear side, the front side being situated opposite the rear side, the front side representing a structured semiconductor wafer side including contact areas, the method comprising the following steps: applying at least one first layer to the front side using printing technology, the at least one first layer including a first material which is water-insoluble; and curing the at least one first layer using UV radiation or thermally or using sintering.

12. The method as recited in claim 11, further comprising: producing, using a laser, n openings of the at least one first layer, which partially expose the contact areas.

13. The method as recited in claim 11, wherein the at least one first layer includes a second material, which is applied to the front side above the contact areas using printing technology, openings of the at least one first layer, which partially expose the contact areas, being produced by removing the second material.

14. The method as recited in claim 11, further comprising: applying a structured planarizing layer to the front side, the structured planarizing layer filling in recesses of the front side.

15. The method as recited in claim 11, wherein a media-soluble layer or a thermally soluble layer or an optically soluble layer is applied directly to areas on the front side.

16. The method as recited in claim 11, wherein the application of the at least one first layer takes place repeatedly, the at least one first layer having a layer thickness of at least 5 μm.

17. The method as recited in claim 16, wherein the layer thickness is between 5 μm and 40 μm.

18. The method as recited in claim 11, wherein the application of the at least one first layer takes place using inkjet technology or LIFT technology or DLP technology or stereolithography, so that the at least one first layer includes a coating layer.

19. A device, comprising: a semiconductor wafer that includes a front side and a rear side, the front side being situated opposite the rear side, and the front side representing a structured semiconductor wafer side including contact areas; and at least one first layer situated on the front side, the at least one first layer including a first material that is media-insoluble and the at least one first layer functioning as a carrier substrate.

20. The device as recited in claim 19, wherein the at least one first layer includes openings that at least partially expose the contact areas.

21. The device as recited in claim 19, wherein the at least one first layer has a layer thickness of at least 5 μm.

22. The device as recited in claim 21, wherein the layer thickness is between 5μ and 40 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention is explained below with reference to preferred specific embodiments and the figures.

[0026] FIG. 1 shows a method for manufacturing a carrier substrate on a semiconductor wafer, according to an example embodiment of the present invention.

[0027] FIG. 2 shows one exemplary embodiment of a device that includes a semiconductor wafer, according to an example embodiment of the present invention.

[0028] FIG. 3 shows a further exemplary embodiment of a device that includes a semiconductor wafer, according to an example embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0029] FIG. 1 shows a method 100 for manufacturing a carrier substrate on a semiconductor wafer, the semiconductor wafer including a front side and a rear side and the front side being situated opposite the rear side. The front side represents a structured semiconductor wafer side including contact areas. Method 100 starts with a step 130, in which at least one first layer is applied to the front side with the aid of printing technology and the at least one first layer is applied fully or includes openings, which partially uncover or expose the contact areas, the at least one first layer including a first material that is water-insoluble. In other words, a carrier layer or a carrier substrate is produced on the semiconductor wafer once the front side has been fully processed. To produce a thick carrier substrate, step 130 may be carried out multiple times in succession. This first layer may either be removed from the actual semiconductor substrate by a suitable liquid, thermally, or by an optical excitation, or may be dissolved itself as a result. In a following step 150, the at least one first layer is cured with the aid of UV radiation, thermally or with the aid of sintering. With repeated application of the first layer, a final hardening step or sintering step optionally takes place, so that a complete cross-linking of the first material is achieved, which improves the mechanical properties of the carrier substrate. Optionally, the at least one first layer is planarized with the aid of a doctor blade in a step 140, which is carried out between step 130 and step 150. The filling in of the topology precisely at the wafer edge and between metallization and passivation layers, including the organic passivation, for example, poly-IMID and the dicing path, achieves the goal of implementing a completely planar surface on the carrier substrate after the printing process.

[0030] Method 100 optionally starts with a step 120, which is carried out prior to step 130, a structured planarizing layer being applied to the front side. In the process, recesses of the front side are backfilled or filled in. Alternatively, method 100 optionally starts with a step 110, which is carried out prior to optional step 120 and prior to step 130, a water-soluble layer being applied to areas directly on the front side.

[0031] In a first exemplary embodiment, the at least one first layer is applied in a structured manner to the front side, so that openings above the contact areas are directly produced.

[0032] In a second exemplary embodiment, the at least one first layer is applied over the entire surface. The openings are subsequently produced with the aid of laser. Alternatively, the openings are produced using further lithographic processes and subsequent etching.

[0033] In a third exemplary embodiment, the at least one first layer includes a second material that is applied simultaneously with the first material, the second material being situated on the front side above the contact areas. The second material may be both media-soluble as well as thermally or optically soluble. The openings are produced as a function of the second material with the aid of a liquid medium in the event the second material is media-soluble and with the aid of optical or thermal excitation in the event the second material is media-insoluble.

[0034] The application of the at least one first layer takes place, for example, with the aid of inkjet technology, laser induced forward transfer (LIFT) technology, digital light processing (DLP) technology or stereolithography. The first material is media-insoluble and includes, for example, an inorganic polymer-based printing medium. The at least one first layer encompasses a layer thickness of at least 5 μm, in particular, a layer thickness of between 5 μm and 40 μm.

[0035] The carrier substrate may either be removed again immediately after the mechanical grinding process of the rear side of the wafer or it remains on the semiconductor wafer until the final manufacturing process step, the chip separation, and is removed from the wafer during the separation process with the aid of a process liquid such as a solvent bath and/or by the addition of additives and/or with the aid of optical radiation and/or by the addition of heat. Alternatively, two processes may be combined, for example, irradiation and solvent bath or addition of heat. In this way, it is possible to dispense with an abrasive film or protective film during laser annealing of the rear side. The carrier substrate offers an additional protection during the separation process, so that a protective coating is not required. The critical lamination and delamination in the case of very thin wafers is thus eliminated.

[0036] FIG. 2 shows an exemplary embodiment of a device 200 including a semiconductor wafer 201, which includes a front side 202 and a rear side 203. Front side 202 is situated opposite rear side 203. Active areas of semiconductor components, which include contact areas 204, are situated on front side 202. A structured planarizing layer 205 is optionally situated on front side 202, which offsets recesses on front side 202. At least one first layer 206 functioning as a carrier substrate is situated on contact areas 204. The at least one first layer 206 includes openings 207. Alternatively, first layer 206 is applied to entire contact areas 204. In this way, the carrier substrate may entirely or partially cover or overlie the semiconductor chip.

[0037] FIG. 3 shows a further exemplary embodiment of a device 300 including a semiconductor wafer 301. Identical rear positions of the reference numerals in FIG. 3 denote the same features as those in FIG. 2. Device 300 also includes a water-soluble layer 308 on front side 302, which serves as a sacrificial layer for removing the carrier substrate after completion of the rear side processes.

[0038] The carrier substrate is temperature-stable, high vacuum-suitable and does not warp.

[0039] Semiconductor wafer 201 and 301 has, for example, a diameter of 150 mm, 200 mm or 300 mm and includes, for example, silicon, silicon carbide, sapphire or QST for gallium nitride components.

[0040] Semiconductor wafer 201 and 301 is rounded off in the edge area. The rounded area is planarized and is topologically filled by the printing medium, so that a planar carrier substrate is formed. The planarization takes place with the layer applied directly to the front side. This may be both the planarizing layer as well as the at least one first layer 206 and 306. In other words, the front side of the semiconductor wafer is planarized before a closed layer is applied. In this case, the optional organic or inorganic planarizing layer 205 and 305 serves to reduce the wafer bow.

[0041] The at least one first layer 206 and 306 is a printing medium, i.e., is produced with the aid of printing technology. The printing medium includes organic or inorganic, for example mineral or ceramic, fillers. In other words, the printing medium includes a coating material, which is applied in liquid or paste-like form and becomes a solid layer as a result of the subsequent curing process.

[0042] The printing medium including the inorganic components in this case is polymer-based, for example. The layer thickness of the at least one first layer 206 and 306 is 5 μm to 40 μm with a one-time application. The carrier substrate may have a layer thickness of up to 1000 μm as a result of repeated applications of first layers 206 and 306.

[0043] The contact areas 204 and 304 are exposed by openings 207 and 307 in the at least one first layer 206 and 306 in such a way that the resulting semiconductor components are able to be tested during the further finishing processes. The at least one first layer 206 and 306 in this case functions as an insulator, so that multiple test heads may be used in the measurements and the risk of an electrical flashover in the case of breakdown voltages >1 kV is reduced.

[0044] Device 200 and 300 is used in the manufacturing of power semiconductor components and power semiconductor modules, which have a chip thickness of less than 180 μm during the processing.