CERAMIC MATERIAL FOR CAPACITOR

Abstract

The present invention relates to a ceramic material for a multilayer capacitor. The ceramic material has a composition according to the following general formula:

Pb.sub.(y−1.5a−0.5b+c+0.5d−0.5e−f)Ca.sub.aA.sub.b(Zr.sub.1−xTi.sub.x).sub.(1−c−d−e−d)E.sub.cFe.sub.dNb.sub.eW.sub.fO.sub.3,

where
A is one or more of the group of Na, K and Ag;
E is one or more of the group of Cu, Ni, Hf, Si and Mn; and
0<a<0.14,
0.05≤x≤0.3,
0≤b≤0.12,
0<c≤0.12,
0≤d≤0.12,
0≤e≤0.12,
0≤f≤0.12,
0.9≤y≤1.5 and
0.001<b+c+d+e+f
applies.

Further, the invention includes a capacitor comprising the described ceramic material.

Claims

1. A ceramic material for capacitors in multilayer technology of the general formula:
Pb.sub.(y−1.5a−0.5b+c+0.5d−0.5e−f)Ca.sub.aA.sub.b(Zr.sub.1−xTi.sub.x).sub.(1−c−d−e−d)E.sub.cFe.sub.dNb.sub.eW.sub.fO.sub.3, wherein A is one or more of the group of Na, K and Ag; E is one or more of the group of Cu, Ni, Hf, Si and Mn; and 0<a<0.14, 0.05≤x≤0.3, 0≤b≤0.12, 0<c≤0.12, 0≤d≤0.12, 0≤e≤0.12, 0≤f≤0.12, 0.9≤y≤1.5 and 0.001<b+c+d+e+f applies.

2. The ceramic material according to claim 1, wherein 0.001<a<0.14.

3. The ceramic material according to claim 1, wherein 0.001<b<0.12.

4. The ceramic according to claim 1, wherein 0.001<c<0.12.

5. The ceramic according to claim 1, wherein 0.001<d<0.12.

6. The ceramic according to claim 1, wherein 0.001<e<0.12.

7. The ceramic according to claim 1, wherein 0.001<f<0.12.

8. The ceramic according to claim 1, wherein 0.005<b+c+d+e+f.

9. The ceramic according to claim 1, wherein the ceramic material is an anti-ferroelectric dielectric.

10. The ceramic according to claim 1, wherein the sintering temperature of the ceramic material is between 900° C. and 1200° C.

11. The ceramic material according to claim 10, wherein the sintering temperature of the ceramic material is between 980° C. and 1080° C.

12. The ceramic material according to claim 10, wherein the sintering temperature of the ceramic material is below the melting point of copper.

13. The ceramic material according to claim 12, wherein the sintering temperature of the ceramic material is below the melting point of silver.

14. A capacitor comprising dielectric layers made of a ceramic material, and electrode layers disposed therebetween and stacked in a layer order, wherein the electrode layers comprise at least first and/or second electrodes, and wherein the ceramic material has the following general formula:
Pb.sub.(y−1.5a−0.5b+c+0.5d−0.5e−f)Ca.sub.aA.sub.b(Zr.sub.1−xTi.sub.x).sub.(1−c−d−e−d)E.sub.cFe.sub.dNb.sub.eW.sub.fO.sub.3, wherein A is one or more of the group of Na, K and Ag; E is one or more of the group of Cu, Ni, Hf, Si and Mn; and 0<a<0.14, 0.05≤x≤0.3, 0≤b≤0.12, 0<c≤0.12, 0≤d≤0.12, 0≤e≤0.12, 0≤f≤0.12, 0.9≤y≤1.5 and 0.001<b+c+d+e+f applies.

15. The capacitor according to claim 14, wherein the ceramic material fulfills 0.001<c<0.12.

16. The capacitor according to claim 14 comprising two segments, wherein each segment comprises dielectric layers of the ceramic material and electrode layers arranged in between, wherein the outermost dielectric layers of two segments form a connection region in which the segments are firmly connected to one another parallel to the layer planes, wherein the connection region includes a relief region in which the segments are not firmly connected to each other.

17. The capacitor according to claim 14, wherein two separate external contacts for contacting the first and second electrodes are applied to exit surfaces on the outside of the capacitor, on which electrodes exit from the capacitor.

18. The capacitor according to claim 14 comprising at least one third electrode not contacted by any of said outer contacts, said third electrode overlapping with said first and second electrodes.

19. The capacitor according to claim 14, comprising further electrodes which do not overlap with any electrodes of a different polarity.

20. The capacitor according to claim 14, wherein the external contacts comprise a multilayer sputter layer comprising layers of chromium, nickel and at least one of silver or gold, the layers being deposited on the exit surfaces in that order.

21. The capacitor according to claim 20, wherein the external contacts comprise metal sheets deposited on the sputter layer by means of a sintered silver layer.

22. The capacitor according to claim 21, wherein the metal sheets comprise two copper layers and an invar layer disposed therebetween.

23. The capacitor according to claim 17, wherein the capacitor comprises separable capacitor units, which can be assembled and disassembled as desired at a contact surface, the contact surface being arranged perpendicular to the layer planes and the outer contacts.

24. The capacitor according to claim 14, wherein the ceramic material fulfills 0.001<a<0.14.

25. The capacitor according to claim 14, wherein the ceramic material fulfills 0.001<b<0.12.

26. The capacitor according to claim 14, wherein the ceramic material fulfills 0.001<d<0.12.

27. The capacitor according to claim 14, wherein the ceramic material fulfills 0.001<e<0.12.

28. The capacitor according to claim 14, wherein the ceramic material fulfills 0.001<f<0.12.

29. The capacitor of claim 14, wherein the ceramic material fulfills 0.005<b+c+d+e+f.

30. The capacitor according to claim 14, wherein the ceramic material is an anti-ferroelectric dielectric.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0128] The invention is described in detail below with reference to figures.

[0129] It show:

[0130] FIG. 1: Phase diagram of PbZrO.sub.3—PbTiO.sub.3 solid solution series with variation of temperature.

[0131] FIG. 2: Phase diagram of the PbZrO.sub.3—PbTiO.sub.3 solid solution series when doped with lanthanum at room temperature.

[0132] FIG. 3: Comparison of hysteresis curves at positive values of the electric field of anti-ferroelectric ceramics of compositions

1. Pb.sub.0.9Ca.sub.0.1Zr.sub.0.891Ti.sub.0.099Cu.sub.0.005W.sub.0.005O.sub.3.
2. Pb.sub.0.9Ca.sub.0.1Zr.sub.0.8865Ti.sub.0.0985Cu.sub.0.005Nb.sub.0.01O.sub.3 and
3. Pb.sub.0.9Ca.sub.0.1Zr.sub.0.8865Ti.sub.0.985Ni.sub.0.005Nb.sub.0.01O.sub.3.

[0133] The sample thickness is 180 μm in each case. The diameter of the measured area is 5 mm in each case.

[0134] FIG. 4: Hysteresis curves at positive electric field values of a multilayer ceramic capacitor comprising a ceramic of composition Pb.sub.0.9Ca.sub.0.1Zr.sub.0.891Ti.sub.0.099Cu.sub.0.005W.sub.0.005O.sub.3 and copper electrodes.

[0135] FIG. 5: Cross-sectional side view of a first embodiment of a multilayer capacitor.

[0136] FIG. 6: Cross-section from the top view of the first embodiment of a multilayer capacitor.

[0137] FIG. 7: Cross-sectional side view of a second embodiment of a multilayer capacitor.

[0138] FIG. 8: Cross-section from the top view of the second embodiment of a multilayer capacitor.

DETAILED DESCRIPTION

[0139] FIGS. 1 and 2 show the phase diagrams of the PbZrO.sub.3—PbTiO.sub.3 solid solution series at different temperatures (FIG. 1) and at room temperature and doping with La (FIG. 2), respectively, which were introduced earlier. FT and FR are ferroelectric tetragonal and rhombohedral phases, respectively. PC denotes the paraelectric cubic phase. AO and AT stand for anti-ferroelectric orthorhombic and tetragonal phases, respectively. HT stands for high temperature phase, LT stands for low temperature phase. MPB stands for morphotropic phase boundary.

[0140] FIG. 3 shows hysteresis measurements of sintered samples based on a Ca.sup.2+-doped PZT ceramic and further doped with W.sup.6+—, Nb.sup.5+—, Cu.sup.2+— and Ni.sup.2+-ions. The samples are disk-shaped compacts which were debonded under air atmosphere at 150° C. and sintered at 1150° C. for 4 h. The samples have a diameter of 5.5 mm. The compacts have a diameter of 5 mm and a sample thickness of 180 μm.

[0141] In the exemplary hysteresis measurements shown, different values are obtained for the polarization at a defined electric field strength. In particular, the third measured composition Z3 is significantly less polarized than the first two compositions Z1 and Z2 at the same electric field strength.

[0142] In general, a high polarizability of the ceramic is desirable when an electric field is applied, as this allows a higher capacitor charge to be achieved. The integral of the polarization over the electric field strength gives the energy stored in the ceramic.

[0143] Furthermore, the area enclosed by the hysteresis should be as small as possible, since this is a measure of the energy loss during the charging and discharging process of the capacitor.

[0144] The fact that these ceramics are also suitable for sintering at temperatures below the melting point of copper has been demonstrated by multilayer capacitors with copper electrodes. FIG. 4 shows the hysteresis curve of such a multilayer capacitor for one of the materials from FIG. 3.

[0145] The low polarization field strength hysteresis indicates only small energetic losses during the charging and discharging process of the capacitor.

[0146] FIGS. 5 and 6 show an example of a first embodiment of a multilayer capacitor 1 in two cross-sections from the side view (FIG. 5) and from the top view (FIG. 6), respectively, which comprises the material according to the invention.

[0147] The capacitor has two segments 2A and 2B, the segments being arranged one above the other in the stacking direction.

[0148] Each segment comprises a stack comprising electrode layers with first electrodes 3, electrode layers with second electrodes 4 and dielectric layers 6 arranged between these electrodes. The said layers are arranged one above the other in a defined stacking direction.

[0149] The ends of the first electrodes 3 and second electrodes 4 are exposed at two opposite exit surfaces 3A and 4A of the cuboid multilayer capacitor 1.

[0150] Since the electrodes 3/4 do not extend to the opposite exit surface in each case, there are two regions in multilayer capacitor 1 to be distinguished. In the regions in the center of the capacitor, first and second electrodes 3/4 overlap. These regions are called active regions 7A.

[0151] Only electrodes of one type, i.e. only first or only second electrodes 3/4, are present at the regions adjacent to the exit surfaces 3A/4A. These regions are called passive regions 7B.

[0152] The segments are connected in a connection region 8. Relief regions 9 are present within the connection region 8.

[0153] The connection region 8 comprises the same dielectric ceramic material as the dielectric layers in segments 2A and 2B.

[0154] The connection region 8 includes the lowermost dielectric layer of a first segment 2A and the uppermost dielectric layer of a second segment 2B, which are arranged one above the other in the stacking direction. There is no electrode inside the connection region 8.

[0155] At the edge of the connection region 8, a continuous relief region 9 is located along the entire outer periphery of the capacitor 1. The relief region 9 is located between the lowest dielectric layer of the first segment 2A and the uppermost dielectric layer of the second segment 2B.

[0156] The depth of the relief region 9, measured from the outside of the capacitor 1 to the innermost point in the capacitor 1 preferably corresponds to the stack height of a segment.

[0157] This ensures that the mechanical stresses due to the deformation of the ceramic in the electric field do not add up across the segments and thus lead to cracks in the material, for example.

[0158] The relief region 9 includes all passive regions 7B of the multilayer capacitor 1, i.e., the relief region 9 is arranged within the connection region 8 in parallel with all sections in the segments including only one kind of electrodes or no electrodes. Furthermore, the relief region 9 partially extends into the active region 7A.

[0159] Viewed from the stacking direction and as shown in FIG. 6, the active region 7A has the shape of a rectangle. The passive region 7B forms a rectangular frame surrounding the active region 7A. The relief region 9 forms a rectangular frame surrounding the passive region 7B and further partially overlaps with the active region 7A.

[0160] The relief region 9 is a region in which the stacked dielectric layers 6 are not firmly or only partially bonded to each other.

[0161] The embodiment of the multilayer capacitor 1 shown in FIGS. 7 and 8 is substantially the same as the multilayer capacitor 1 of the first example, which comprises the material according to the invention.

[0162] Multilayer capacitor 1 again comprises two segments 2A and 2B, each consisting of layer planes stacked in the same order.

[0163] In addition to first and second electrodes 3/4, the segments also comprise third electrodes 5. The third electrodes 5 are internal, so-called floating electrodes, which are not contacted from the outside.

[0164] The first and second electrodes 3/4 are each arranged in the same layer plane, but each is separated by a dielectric section.

[0165] Layer planes comprising first and second electrodes 3/4 are arranged between the layer planes comprising the third electrodes 5. A dielectric layer 6 is arranged between each of the electrode layers.

[0166] Thus, a multilayer capacitor 1 is formed comprising two capacitors connected in series. A first capacitor 1A formed between the first and third electrodes, and a second capacitor 1B formed between the third and second electrodes.

[0167] Between the two active regions 7A of capacitors 1A and 1B there is a passive region 7B in which only third electrodes 5 are present, and thus in which no electrodes of different types overlap.

[0168] In the connection region 8, two outer dielectric layers of the segments 2A and 2B arranged in the stacking direction of the layers are firmly connected to each other. The connection can be created by sintering, for example.

[0169] A relief region 9 is pronounced in the connection region 8. The relief region 9 here is a gap between the first and second segments.

[0170] The relief region 9 includes an outer section along the perimeter of the capacitor 1 and an inner section.

[0171] The additional inner section is pronounced so that the entire passive region 7B is covered by the relief region 9. Furthermore, the relief region 9 also extends into the outer sections of the two active regions 9A of the capacitors 1A and 1B.

[0172] The relief region 9 serves to relieve the capacitor 1 in the event of mechanical deformations due to the applied electric field. The relief region 9 prevents the addition of mechanical stresses over the entire stack height.