Metal oxide semiconductor integrated circuit basic unit

Abstract

A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.

Claims

1. A metal oxide semiconductor (MOS) integrated circuit basic unit, comprising: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode; wherein: the drain semiconductor region is a bottom of the basic unit; the gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region; an upper surface of the gate electrode is aligned to an upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region; the gate dielectric layer is disposed between the gate electrode and an adjacent functional layer; the gate dielectric layer provides the isolation between the gate electrode and the source region, and the lightly doped drain region, and the drain semiconductor region; and the drain semiconductor region is connected to the drain electrode of the basic unit.

2. The circuit of claim 1, wherein the gate dielectric layer comprises SiO.sub.2, Si.sub.3N.sub.4, HfO.sub.2, Al.sub.2O.sub.3 or a combination thereof.

3. The circuit of claim 1, wherein the source semiconductor region comprises pseudo-crystal SiGe, polycrystalline SiGe, polycrystalline germanium, polycrystalline InP, or polycrystalline HgCdTe; and the channel semiconductor region comprises silicon.

4. The circuit of claim 1, wherein the channel semiconductor region comprises SiC or GaN, and the source semiconductor region comprises Si or Ge.

5. An inverter, comprising two MOS integrated circuit basic units of claim 1 arranged in parallel; wherein: the two MOS integrated circuit basic units comprise a first basic unit and a second basic unit; in the first basic unit, the drain semiconductor region is an N.sup.+ type, the lightly doped drain region is an N.sup.− type, the channel semiconductor region is a P type, and the source semiconductor region is an N.sup.+ type; in the second basic unit, the drain semiconductor region is a P.sup.+ type, the lightly doped drain region is a P.sup.− type, the channel semiconductor region is an N type, and the source semiconductor region is a P.sup.+ type; the first basic unit and the second basic unit share a drain electrode; the gate electrodes of the first basic unit and the second basic unit are integrated as an entity; and the gate dielectric layer provides the isolation between the gate electrode and the source semiconductor region, and the lightly doped drain region, and the drain semiconductor region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a front view of the schematic diagram of the structure of a new type MOS integrated circuit basic unit.

(2) FIG. 2 is a top view of the schematic diagram of the structure of a new type MOS integrated circuit basic unit.

(3) FIG. 3 is the output characteristic curves of the simulation result of the Example 1.

(4) FIG. 4 is the output characteristic curves of the simulation result of the Example 2.

(5) FIG. 5 is the output characteristic curves of the simulation result of the Example 3.

(6) FIG. 6 is the output characteristic curves of the simulation result of the Example 4.

(7) FIG. 7 is the output characteristic curves of the simulation result of the Example 5.

(8) FIG. 8 is the transfer characteristic curves of the simulation result of the Example 5.

(9) FIG. 9 is a front view of the schematic diagram of the structure of an inverter made of a new type of the MOS Integrated Circuit Basic Unit.

(10) FIG. 10 is a top view of the schematic diagram of the structure of an inverter made of a new type of the MOS Integrated Circuit Basic Unit.

(11) In FIG. 1, 101. Gate dielectric layer; 102. Gate electrode; 103. Source semiconductor region; 104. Channel semiconductor region; 105. Lightly doped drain region; 106. Drain semiconductor region; 107. Source electrode; 108. Drain electrode.

DETAILED DESCRIPTION

Example 1

(12) This example simulated the output characteristic curves of the NMOS with the different channel lengths (L.sub.ch) which were the thicknesses of the channel semiconductor region 104. In this example, the thickness of the channel semiconductor region 104 were 7 nm, 5 nm, and 3 nm, respectively. In the simulations, except for the thickness of the channel semiconductor region 104, the other parameters were the same.

(13) Taking the lateral distance as the width and the vertical distance as the thickness, taking the NMOS with the 7 nm thickness of the channel semiconductor region 104 as an example, the specific parameters of its structure were as follows. The source semiconductor region 103 had a thickness of 10 nm and a width of 10 nm, the material was the SiGe, the doping concentration was 1×10.sup.20 cm.sup.−, and the impurity was phosphorus. The channel semiconductor region 104 had a thickness of 7 nm and a width of 10 nm, the material was the silicon, the doping concentration was 5×10.sup.19 cm.sup.−3, and the impurity was the boron. The lightly doped drain region 105 had a thickness of 80 nm and a width of 10 nm, the material was the silicon, the doping concentration was 1×10.sup.15 cm.sup.−3, and the impurity was the phosphorus. The drain semiconductor region 106 had a thickness of 10 nm and a width of 10 nm, the material was the silicon, and the doping concentration was 1×10.sup.30 cm.sup.−3, the impurity was the phosphorus. The gate dielectric layer 101 had a thickness of 2 nm, it wrapped outside the gate electrode 102, and the material was the SiO.sub.2. The gate electrode 102 had a thickness of 98 nm and a width of 16 nm, the material was the polysilicon, the doping concentration was 5×10.sup.20 cm.sup.−3. The source electrode 107 had a thickness of 15 nm and a width of 9 nm, the material was the titanium.

(14) In the simulation of the 5 nm and 3 nm devices, only the thicknesses of the channel semiconductor region 104 were changed, the other parameters were as same as that of 7 nm. The simulation results were shown in FIG. 3.

(15) FIG. 3 was the simulation result comprising the output characteristic curves of the 7 nm, 5 nm, and 3 nm devices of the Example 1. It could be seen that the devices worked normally. When the V.sub.gs=0, the drain currents were almost zero and the maximum trans-conductance was 0.135 mS, 0.141 mS and 0.142 mS for the devices with 7 nm, 5 nm, 3 nm L.sub.ch (104) respectively.

Example 2

(16) In this example, except for the L.sub.ch (104) were changed to 2 nm, 1 nm, 0.54 nm, respectively, the other parameters were the same as the Example 1.

(17) FIG. 4 was the simulation result comprising the output characteristic curves obtained by the Example 2. It could be seen that the devices worked normally. When V.sub.gs=0, the drain currents were almost zero, and the maximum trans-conductance was 0.146 mS, 0.150 mS and 0.153 mS for the devices with 2 nm, 1 nm, 0.54 nm L.sub.ch respectively.

Example 3

(18) The parameters of the structures of the Example 3 were exactly the same as what in the Example 1, except for the thickness of the lightly doped drain region 105 and the channel semiconductor region 104. In this example, the thickness of the channel semiconductor region 104 was 5 nm, and the thicknesses of the lightly doped drain region 105 (L.sub.drift) were 20 nm, 40 nm, and 80 nm, respectively.

(19) FIG. 5 was the simulation result comprising the output characteristic curves obtained by the Example 3. It could be seen that the devices worked normally and the drain current I.sub.ds was increased as the L.sub.drift was decreased.

Example 4

(20) In this example, on the basis of the Example 1, the material of gate dielectric layer 101 was changed to the HfO.sub.2, the material of the source semiconductor region 103 was changed to the InP. The L.sub.ch (104) was 7 nm. The other parameters of the structure of the Example 4 were exactly as same as what in the Example 1.

(21) FIG. 6 was the simulation result comprising the output characteristic curves obtained by the Example 4. It could be seen that the device worked normally. It also could be seen that when V.sub.gs=0, the drain currents were almost zero and the maximum trans-conductance was 115 mS.

Example 5

(22) In this example, on the basis of the Example 1, the thickness of the channel semiconductor region 104 (L.sub.ch) was 7 nm, the thickness of the lightly doped drain region 105 (L.sub.drift) was changed to 20 nm, and the operating voltage V.sub.dd was increased to 1.2V. The other parameters of the structure of the Example 5 were exactly as same as what in the Example 1.

(23) FIG. 7 was the simulation result of the output characteristic curves. FIG. 8 was the simulation result of the transfer characteristic curve. It could be seen that the device worked normally. It also could be seen that in FIG. 7, when V.sub.gs=0, the drain currents were almost zero and the maximum trans-conductance was 170 mS. In FIG. 8, the ratio of the drain currents when device was on and off Ids(on)/Ids(off) was over 10.sup.8.

Example 6

(24) In this example, on the basis of the Example 1, the material of gate dielectric layer 101 was changed to the Al.sub.2O.sub.3, and the material of source semiconductor region 103 was changed to the InP. The other parameters of the structure of the Example 6 were exactly the same as those of the Example 1.

Example 7

(25) In this example, on the basis of the Example 1, the material of the source semiconductor region 103 was changed to the Si, the material of the channel semiconductor region 104 was changed to the SiC. The other parameters of the structure of the Example 7 were exactly the same as those of the Example 1.

Example 8

(26) In this example, on the basis of the Example 1, the material of the source semiconductor region 103 was changed to the Si, and the material of the channel semiconductor region 104 was changed to the GaN. The other parameters of the structure of the Example 8 were exactly the same as those of the Example 1.

Example 9

(27) In this example, a MOS inverter unit was formed based on the device in the Example 1. The inverter comprises two MOS integrated circuit basic units arranged in parallel, which are called the first basic unit and the second basic unit. In the first basic unit, the drain semiconductor region of is an N.sup.+ type, the lightly doped drain region is an N.sup.− type, the channel semiconductor region is a P type, and the source semiconductor region is an N.sup.+ type. While in the second basic unit, the drain semiconductor region is a P.sup.+ type, the lightly doped drain region is a P.sup.− type, the channel semiconductor region is an N type, and the source semiconductor region is a P.sup.+type. The gate electrodes 102 of the first basic unit and the second basic unit are integrated as an entity. The first basic unit and the second basic unit share a drain electrode 108. The gate dielectric layer 101 provides the isolation between the gate electrode 102 and the source semiconductor region 103, and the lightly doped drain region 105, and the drain semiconductor region 106. The two MOS integrated circuit basic units had the same sizes and doping concentrations for the corresponding regions. The drain electrode 108 was the drain electrode, the material was the titanium, the width was 10 nm, and the thickness was 100 nm. The source electrode 107 of the first basic unit was connected to the ground GND. The source electrode 107 of the second basic unit was connected to the power supply V.sub.dd. The gate electrode 102 was the input port. The drain electrode 108 was the output port.

(28) It will be obvious to those skilled in the art that changes and modifications may be made, and therefore, the aim in the appended claims is to cover all such changes and modifications.