Method for enhancing port error monitoring in IEEE-1394 high-performance serial bus

Abstract

A method for enabling and disabling Port Error detection and customizing corresponding error count threshold values. The method allows for adjustment of signal error verification thresholds before a connected port signals a loss of connection due to corrupted characters detected during normal operation and initialization on an IEEE-1394 serial bus. Also, the method customizes the limits for a Loss of Synchronization transition and reduces the probability for Bus Resets. Further, the method provides for a more stable bus operation, which is critical for usage in tight-looped and low-latency control systems.

Claims

1. A system for balancing the effects and consequences of a corrupted signaling and data exchange circuit versus Bus Resets on a IEEE-1394 Serial Bus, the system providing for more robust bus stability by customizing a Loss-of-Synchronization detection threshold on one or more IEEE-1394 bus nodes, the system comprising: a Node with Node Cable Connector; a Node Port connected to the Node Cable Connector, the Note Port for transmitting and receiving data from the circuit; a Port Register, a Port State Machine and a Port Error Monitor all connected to the Node Port; a Port Error Counter connected to the Node Port, the Port Error Counter for counting a number of invalid characters received in the Port Register, the Port Error Counter programmed for the Loss-of-Synchronization detection only when a count is in an excess of four (4); a PHY State Machine under the control of a PHY Register, the PHY State Machine connected to the Port State Machine; and a Register Field connected to the circuit and to the Port Error Monitor, the Register Field includes defined settings for the optimization of the Port Error Monitor, which are PHY specific, and wherein a customizable threshold limit greater than the count in an excess of four (4) can be adjusted to values calculated from register values in the Register Field before a transition to Loss-of-Synchronization occurs.

2. A system for balancing the effects and consequences of a corrupted signaling and data exchange circuit versus Bus Resets on a IEEE-1394 Serial Bus, the system providing for more robust bus stability by customizing a Loss-of-Synchronization detection threshold on one or more IEEE-1394 bus nodes, the system comprising: a Node with Node Cable Connector; a Node Port connected to the Node Cable Connector, the Note Port for transmitting and receiving data from the circuit; a Port Register, a Port State Machine and a Port Error Monitor all connected to the Node Port; a Register Field connected to the circuit and the Port Error Monitor, the Register Field includes defined settings for the optimization of the Port Error Monitor, which are PHY specific; a Port Error Counter connected to the Node Port for counting a number of invalid characters received in the Port Register, the Port Error Counter programmed for the Loss-of-Synchronization detection only when a count is in an excess of four (4); and a PHY State Machine under the control of a PHY Register, the PHY State Machine connected to the Port State Machine, wherein a customizable threshold limit greater than the count in an excess of four (4) can be adjusted to values calculated from register values in the Register Field before a transition to Loss-of-Synchronization occurs.

3. A system for balancing the effects and consequences of a corrupted signaling and data exchange circuit versus Bus Resets on a IEEE-1394 Serial Bus, the system providing for more robust bus stability by customizing a Loss-of-Synchronization detection threshold on one or more IEEE-1394 bus nodes, the system comprising: a plurality of Nodes with Node Cable Connectors; Node Ports connected to the Node Cable Connectors, the Note Ports for transmitting and receiving data from the circuit; a Port Register, a Port State Machine and a Port Error Monitor all connected to the Node Ports; a Register Field connected to the circuit and the Port Error Monitor, the Register Field includes defined settings for the optimization of the Port Error Monitor, which are PHY specific; a Port Error Counter connected to the Node Ports for counting a number of invalid characters received in the Port Register, the Port Error Counter programmed for the Loss-of-Synchronization detection only when a count is in an excess of four (4); and a PHY State Machine under the control of a PHY Register, the PHY State Machine connected to the Port State Machine, wherein a customizable threshold limit greater than the count in an excess of four (4) can be adjusted to values calculated from register values in the Register Field before a transition to Loss-of-Synchronization occurs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates Nodes A, B and C connected to form an IEEE1394 bus.

(2) FIG. 2 illustrates relevant structures of PHYs and PHY ports, connected and disconnected.

(3) FIG. 3 illustrates a default method of a PHY port in case of corrupted characters.

(4) FIG. 4 illustrates the enhancement method custLimit of a PHY port in case of corrupted characters.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) The accompanying drawings illustrate complete preferred embodiments in the present invention according to the practical application of the subject of IEEE-1394 low signal integrity verification, and in which:

(6) In FIG. 1, Node A lO, Node B 12, and Node C 14 are shown interconnect to form an IEEE-1394 bus. The Nodes can be consumer electronic devices like a camcorder, a personal computer (PC) or a television set, but also subcomponents in an avionics system. In this drawing Node A 10 is physically connected to Node B 12 via cable 16 between connectors 15 and 17. Node B 12 is connected to Node C 14 via cable 18. Cable 18 is connected to a connector 19 on Node B and connected to a connector 21 on Node C.

(7) On Node A, connectors 20 and 22 are not connected. Also, connectors 24 and 26 on Node C are not connected. In this example, only one connector 28 is not connected on Node B. The nodes A, B and C are shown with their respective local hosts 30, 32 and 34, Link Layer Controllers or LLC 36, 38 and 40 and physical layer components or PHY 42, 44, and 46. From an IEEE-1394 perspective, it is the physical layer components PHYs that electrically and logically interconnect the three nodes to form serial bus nodes.

(8) The detailed functionality of Node A, Node B and Node C is defined by functional blocks within a PHY. IEEE-1394, which specifies logical blocks and a state machine. This combination is essential for bus interconnectivity and data exchange effected by the features of the subject method as disclosed herein. Therefore, only the relevant components are depicted in FIG. 2. Also, those skilled in IEEE-1394 technology will recognize that the functional blocks explained for Node B are identical for the other nodes, such as Nodes A and C, connected to the bus.

(9) In FIG. 2, the physical interconnect of cables 16 and 18 to connectors 17 and 19 extend to logical ports 48, 50 and 52 referred to as Port A, Port B, and Port C. The ports provide transmit and receive functions for formatting data as it passes between an arbitration state machine, cables and connectors. Also, they form a logical connectivity interface to a PHY StateMachine 54, which is controlled by a PHY Register 56. Non-relevant components within the PHY are summarized in block 58, which are not discussed herein.

(10) The ports 48, 50 and 52 consist of a series of identical blocks and only Port Error Monitors 60, 62 and 64, Port Registers 66, 68 and 70, as well as Port State Machines 72,74 and 76 are depicted in this drawing. The respective blocks are the same in the different ports, but will vary in an occupied state within the PHY State Machine 54, and will expose different Port register status values due to specifics of each port connection. For example and shown in FIG. 1, the connection status of port 48 would report disconnected, with the PHY State Machine 54 being a PO:disconnected state.

(11) For the same topology, Port B 50 and Port C 52 will be physically and logically connected. Therefore, their status register would report connected and having completed a tree identify process and establish a child/parent relationship. And the Port State Machines 74 and 76 will be in P2:Active, assuming the PHY went through a successful bus initialization and arbitration phase, and is able to receive or transmit data.

(12) Port Error Monitors 60, 62 and 64 are critical in this application of the subject port error monitoring method. Because of the disconnected state of Port A 48 its Port Error Monitor 60 will be deactivated. Reflecting this disconnected state, Port Error Monitor 62 and Port Error Monitor 64 will be activated and will be sampling low level data transmission for corrupted characters.

(13) The method for establishing a proper connection including the verification of character validity is part of the IEEE-1394-2008 specifications and shall only be summarized: Upon connection via a cable, the ports initiate a port training procedure during which the Port transmits a sequence of training symbols to the remote port. The remote port also begins the training procedure and transmits a sequence of training symbols. While receiving a training sequence, the port synchronizes itself with the received character stream.

(14) Maintaining synchronization for interconnected ports is essential and is key for an uninterrupted connection and data exchange. Therefore and depicted in FIG. 3, a Port Error Monitor 80 continues monitoring the validity of received characters. As shown in FIG. 3, each port, for example Port B and Port C, maintains a Port Error Counter 82 for counting the number of invalid characters received in the Port registers. When an invalid character is received this count is incremented, or it is decremented when two consecutive valid characters are received.

(15) FIG. 3 also shows if a port error count 84, when reaching a count of 4, give an indicate loss of synchronization 86 then any subsequent recovery operations 88, not resulting in an immediate resynchronization, the port will disconnect resulting in the Bus Reset.

(16) For IEEE-1394 serial bus, a Bus Reset is a disruptive event as all communication ceases. The bus reinitializes, reconfigures and undergoes a series of procedures before interconnected nodes can communicate to either other.

(17) The downtime depends on what type of BusReset is initiated and IEEE-1394 differentiates between a short arbitrated (1.3 μs) and a long (˜166.7 μs) BusReset. It depends very much on the application, but typically in consumer electronics even a long BusReset has a marginal effect on the user's experience for example when watch a streaming video. And on file transfer application the QoS with its Retry mechanisms would ensure data integrity and proper file transfer.

(18) The situation is very different when the IEEE-1394 serial bus is used in tight-looped and low-latency control systems. A good example is a typical avionics vehicle management system. Multiple LRUs (sensors and actuators) are interconnected and communicate to each other in a very precisely managed messaging methodology in which timing is key. A loss of bus synchronization and the resulting Bus Reset as explained above have severe effects on the latencies of such a system and needs to be avoided as much as possible. As a matter of fact corruption of data is less of an issue than the latencies introduced by a Bus Reset if the corruption is short lived. Avionics systems typically have systems redundancies, which can add fault tolerance not only if a specific sensor fails but also if its connectivity is causing issues. These fault tolerances are typically handled on a higher system level.

(19) Unfortunately, implementing a IEEE-1394 serial bus interface, with commercially available silicon, currently gives no control over the behavior of the Port State Machine. Commercially available PHY silicon follows the definitions of the IEEE specification and the behavior of the port regarding the Port error count is not modifiable.

(20) The method described below provides a programmable implementation that ensures backward compatibility as well as offers software/hardware programmable means to enable this new functionality. In addition to the method described below, other methods may be implemented that provide the same desired results such as deleting the Port Error verification code, increasing Port Error Count to a value greater than 4 or any other implementation that effectively disables or removes the Port Error verification capability described in IEEE-1394-2008 section 13.3.2.1.1.

(21) The subject method as described, adds a customizable verification limit mode of operation. This mode is configurable and adjustable through a PHY register or through hardware configuration (signal) means as follows:

(22) TABLE-US-00001 Power reset Field Size Type value Description portError_Crtl 2 Rw 000.sub.3 0003 = limit enabled, portError_limit value defines the limit for a the portError counter. If portError is greater or equal custanit then the port will indicate loss of sync. 001.sub.3 = reserved 010.sub.3 = reserved 011.sub.3 = reserved 100.sub.3 = reserved 101.sub.3 = reserved 111.sub.3 = indicate loss of sync is disabled entirely portError_Limit 8 rw 4 Defines how many character errors can be counted (in portError) before port will indicate loss of synchronization. The default value of 4 ensures compatibility with the method currently defined in the IEEE-1394- 2008 standard. portError_Limit- 8 Rw 0 Defines multiplier for the expansion portError_Limit.

(23) Those skilled in the art will understand right away that above register definitions can exist for each port on a specific PHY and define equally for all ports on the PHY. In commercially available silicon this number is usually limited to 3, yet IP based PHY solutions have successfully implemented up to 9 ports. The IEEE-1394-2008 specification limits the total number of ports per device to 16.

(24) In FIG. 4, a custom Limit flowchart provides easy to read graphical representation of the custom Limit implementation. By using portError_Ctrl=001 a custom Limit 90 used in a Port Error Verification 92 extends the static and hardcoded verification limit of 4 (four) to a dynamic and adjustable value. In the presented example the custom Limit is calculated from the values of two 8-bit registers portError_Limit and portError_Limit_expansion. The resulting custom Limit 90 maximum therefore is defined as custLimit=portError_Limit_expansion*255+portError_Limit and ranges from 0 to 32640 (i.e. 127*255+255). However, the invention should not be limited or restricted to the register structure presented above. Where needed providing for a much larger custom Limit can be implemented via additional registers.

(25) The benefit of the invention should be immediately evident to those skilled in the art. Providing an adjustable Port Error limit allows the device's control system to customize the threshold for fault detection dynamically. While this seems to be a strange concept in first sight, those skilled in the art will understand that certain implementations can benefit from this invention. For example, the electronic components on an aircraft can be exposed to EMI bursts and other extreme conditions during certain phases like the power up sequence. Such bursts are short lived and the signal disruption is temporary. While full and error-free communication of all devices on the bus might not be a real requirement at this stage, continuous Bus Resets could negatively affect the Start-up sequence of the aircraft. Another example can be small damage to cables during flight. In a damage scenario in which the cable causes sporadic signal disruptions, it might take a high level application some time to locate the cause of the fault and isolate the problem by disconnecting the device from the bus. In the meantime such a faulty cable could cause a series of Bus Resets and seriously disturb the vehicle control system. Should the functionality of a specific device allow for it, the impact of such fault scenarios could significantly be reduced by adjusting the customLimit to a suitable level.

(26) While the invention has been particularly shown, described and illustrated in detail with reference to the preferred embodiments and modifications thereof, it should be understood by those skilled in the art that equivalent changes in form and detail may be made therein without departing from the true spirit and scope of the invention as claimed except as precluded by the prior art.