OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR COMPONENTS

Abstract

In one embodiment, the optoelectronic semiconductor device comprises at least two metallic lead frame parts and a circuit chip on the lead frame parts. An electrically insulating and opaque matrix material mechanically connects the lead frame parts. The circuit chip is embedded in the matrix material, so that a carrier is formed by the matrix material together with the lead frame parts and the circuit chip. An optoelectronic semiconductor chip is provided on a carrier upper side. Furthermore, the semiconductor device comprises at least one optical component on the carrier upper side.

Claims

1. An optoelectronic semiconductor device with at least two metallic lead frame parts, each of which is a solid metal body produced by means of stamping and/or cutting, at least one circuit chip on at least one of the lead frame parts, an electrically insulating and opaque matrix material which mechanically connects the lead frame parts to one another and in which the circuit chip is embedded, so that a carrier is formed by the matrix material together with the lead frame parts and the circuit chip, at least one optoelectronic semiconductor chip, located on a carrier upper side of the carrier, and the carrier upper side is opposite to a mounting side, and at least one optical component on the carrier upper side, wherein the carrier comprises at least one laminate layer, and the carrier upper side is formed in places by the laminate layer.

2. The optoelectronic semiconductor device according to claim 1, further comprising at least one electrical redistribution layer electrically connected via electrical through-connections with at least one of the lead frame parts, wherein the circuit chip and the optoelectronic semiconductor chip are located in different planes parallel to the mounting side, the circuit chip and the optoelectronic semiconductor chip overlap with each other as seen in a plan view, the optical component or at least one of the optical components is formed by a reflection layer and the semiconductor chip rises above the reflection layer in a direction away from the mounting plane, and the optoelectronic semiconductor chip or at least one of the optoelectronic semiconductor chips is a light-emitting diode chip arranged at a distance from the circuit chip.

3. The optoelectronic semiconductor device according to claim 2, wherein the optoelectronic semiconductor chip or at least one of the optoelectronic semiconductor chips is arranged on or in the redistribution layer.

4. The optoelectronic semiconductor device according to claim 2, comprising a plurality of said redistribution layers, wherein the circuit chip is disposed between two redistribution layers, and one of the redistribution layers is located between the circuit chip and the optoelectronic semiconductor chip or at least one of the optoelectronic semiconductor chips.

5. The optoelectronic semiconductor device according to claim 1, wherein the circuit chip and/or the optoelectronic semiconductor chip or at least one of the optoelectronic semiconductor chips is located in at least one recess in at least one of the lead frame parts.

6. The optoelectronic semiconductor device according to claim 1, wherein the optical component or at least one of the optical components is formed by a lens, wherein the lens is bounded by a structural edge on the carrier upper side in a direction parallel to the mounting side, wherein the structural edge is formed in multiple layers.

7. The optoelectronic semiconductor device according to claim 6, wherein a plurality of said optical components are provided and one of the optical components is formed by an opaque diffuse reflective cover layer, wherein the cover layer partially or completely covers the lens on a side facing away from the carrier.

8. The optoelectronic semiconductor device according to claim 1, wherein a plurality of said optical components are present and said laminate layer forms one of the optical components.

9. The optoelectronic semiconductor device according to claim 1, wherein the optoelectronic semiconductor chip or at least one of the optoelectronic semiconductor chips is partially embedded in the matrix material.

10. The optoelectronic semiconductor device according to claim 1, whose main emission direction is oriented parallel to the mounting side with a tolerance of at most 20°.

11. The optoelectronic semiconductor device according to claim 10, in which the optical component or at least one of the optical components or all the optical components are flush with the carrier in a direction parallel to the mounting side.

12. The optoelectronic semiconductor device according to claim 1, comprising a plurality of said optoelectronic semiconductor chips, wherein the optoelectronic semiconductor chips are electrically independently controllable by means of the circuit chip individually or in several groups, wherein the semiconductor device comprises a data input interface which is common to all optoelectronic semiconductor chips and is electrically connected directly to the circuit chip.

13. The optoelectronic semiconductor device according to claim 1, wherein the lead frame parts are exposed at side surfaces of the carrier, wherein the lead frame parts each comprise at least one solder control point on the side surfaces, which is formed by a laterally exposed cutout in the respective lead frame part.

14. The optoelectronic semiconductor device according to claim 1, wherein the carrier is a printed circuit board for the optoelectronic semiconductor chip in which the circuit chip is integrated.

15. A manufacturing method for optoelectronic semiconductor devices according to claim 1, comprising the following steps: A) Providing the carriers in the carrier assembly; B) Applying the optoelectronic semiconductor chips to the carriers; C) Producing at least some of the optical components; and D) Separating to form the semiconductor devices.

16. The method according to claim 15, wherein at least some of the optical components are formed by lenses, wherein the separating in step D) is performed through the lenses so that the main emission directions of the semiconductor devices after step D) are oriented parallel to the mounting sides with a tolerance of at most 20°.

17. An optoelectronic semiconductor device with at least two metallic lead frame parts, each of which is a solid metal body produced by means of stamping and/or cutting, at least one circuit chip on at least one of the lead frame parts, an electrically insulating and opaque matrix material which mechanically connects the lead frame parts to one another and in which the circuit chip is embedded, so that a carrier is formed by the matrix material together with the lead frame parts and the circuit chip, at least one optoelectronic semiconductor chip, located on a carrier upper side of the carrier, and the carrier upper side is opposite to a mounting side, and at least one optical component on the carrier upper side.

Description

[0080] In the following, an optoelectronic semiconductor device described herein and a method described herein are explained in more detail with reference to the drawings by means of exemplary embodiments. Identical reference signs specify identical elements in the individual figures. However, no references to scale are shown; rather, individual elements may be shown exaggeratedly large for better understanding.

[0081] In the figures:

[0082] FIG. 1 shows a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor device.

[0083] FIG. 2 shows a schematic plan view of an optoelectronic semiconductor device described here.

[0084] FIGS. 3 to 11 show schematic sectional views of optoelectronic semiconductor devices described herein.

[0085] FIGS. 12 to 14 show schematic sectional views of method steps of a method described herein.

[0086] FIG. 15 shows a schematic sectional view of a method step of a method described herein.

[0087] FIGS. 16 and 17 show schematic sectional views of method steps of a method described here.

[0088] FIG. 18 shows a schematic sectional view of a carrier for optoelectronic semiconductor devices described herein,

[0089] FIG. 19 shows a schematic top view of lead frame parts for optoelectronic semiconductor devices described herein.

[0090] FIGS. 20 and 21 show schematic sectional views along different sectional directions of a carrier for optoelectronic semiconductor devices described herein.

[0091] FIGS. 22 and 23 show a schematic sectional view and a schematic side view of an optoelectronic semiconductor device described herein.

[0092] FIG. 24 shows a schematic sectional view of an optoelectronic semiconductor device described herein.

[0093] FIG. 25 shows a schematic sectional view of a method step of a method described herein.

[0094] FIGS. 26 to 31 show schematic sectional views of optoelectronic semiconductor devices described herein.

[0095] FIG. 1 shows an exemplary embodiment of an optoelectronic semiconductor device 1. The semiconductor device 1 comprises a carrier 45. The carrier 45 is composed of a plurality of lead frame parts 4 and a matrix material 5 as a supporting component. The matrix material 5 is, for example, an epoxy, in particular a fiber-reinforced epoxy, but may also be a ceramic or a glass. The lead frame parts 4 are preferably each made of a copper sheet or a copper foil.

[0096] Further, the carrier 45 comprises an electrical redistribution layer 7, also referred to as RDL, on a mounting side 46 and on a carrier upper side 44, respectively. The redistribution layers 7 are preferably formed by metallizations, for example by galvanically applied copper layers. For example, to improve solderability, the redistribution layers 7 may each comprise further layers not shown.

[0097] A laminate layer 81, for example made of a solder resist, is located on the mounting side 46. The redistribution layer 7 at the mounting side 46 is also optionally provided with solder balls 76.

[0098] There is also a laminate layer 63 on the carrier upper side 44. This laminate layer 63 is colored white, for example, and forms an optical component 6.

[0099] The laminate layer 63 comprises an opening in which an optoelectronic semiconductor chip 2 is located. The semiconductor chip 2 is, for example, an LED chip. Preferably, a plurality of the semiconductor chips 2 are provided, but only one of the semiconductor chips 2 is illustrated to simplify the illustration. The diffuse reflective laminate layer 36 extends almost to the semiconductor chip 2.

[0100] The semiconductor chip 2 is attached to the carrier 45 via electrical bonding agents 72, such as a solder or an electrically conductive adhesive. A main emission direction M of the semiconductor chip 2 points away from the mounting side 46.

[0101] The lead frame pats 4 as well as the redistribution layers 7 are electrically interconnected via electrical through-connections 74 through the matrix material 5. An electrical interconnection of the semiconductor chips 2 via the lead frame parts 4, the through-connections 74 as well as the redistribution layers 7 is illustrated in the figures only schematically and in a highly simplified manner in each case.

[0102] Seen in a plan view, see FIG. 2, the semiconductor chip 2 and a circuit chip 3 overlap each other. The circuit chip 3 is configured to control the semiconductor chip 2. Preferably, the circuit chip 3 is located entirely within the carrier 45.

[0103] In other words, the carrier 45 with the circuit chip 3, for example an ASIC, is used as a substrate for mounting the at least one semiconductor chip 21. Thus, a space-saving assembly is provided. In particular, the carrier 45 is a so-called EASI substrate or a so-called SESUB.

[0104] In the following, the respective exemplary embodiments of the semiconductor device 1 are illustrated only for a specific design of the carrier 45. However, other types of construction of the carrier 45 may also be used. In particular, the carrier 45 can also be designed in each case as an alternative to the design of FIG. 1, as illustrated in FIGS. 3, 4, 5 as well as 6.

[0105] According to FIG. 3, the circuit chip 3 is not located on one of the lead frame parts 4, but in a cutout in one of the lead frame parts 4. Furthermore, the carrier underside 46 is formed by the lead frame parts 4 as well as by the matrix material 5. That is, there is no electrical redistribution layer on the carrier underside 46 in this case.

[0106] In contrast, according to FIG. 4, the carrier upper side 44 is formed by the lead frame parts 4 and by the matrix material 5. Essentially, the carrier 45 of FIG. 4 corresponds to the carrier of FIG. 3, wherein, however, the mounting side 46 and the carrier upper side 44 are interchanged. Solder balls 76 may be located on the mounting side 46.

[0107] In FIG. 5, it is illustrated that the carrier 45 comprises a plurality of the circuit chips 3, each of which may be accommodated in cutouts in the lead frame parts 4. A more complex interconnection scheme is achievable via the redistribution layers 7 and the through-connections 76. On the mounting side 46 as well as on the carrier upper side 44, the laminate layers 61, 81 and the redistribution layers 7 are preferably located, respectively.

[0108] In the exemplary embodiment of FIG. 6, several of the semiconductor chips 2 are schematically shown, as is also possible in all other exemplary embodiments. Light emitting diode chips and detector chips may be present in combination with each other, as is also possible in all other exemplary embodiments. The circuit chips 3 are attached to different sides of the lead frame parts 4 and may each be located in cutouts, in particular back etchings. The laminate layers 61, 81 and the redistribution layers 7 are located on both main sides 44, 46.

[0109] With regard to the design of the optical component 6, the explanations regarding the other exemplary embodiments each apply accordingly to the designs of FIGS. 3 to 6.

[0110] Shown only for the configuration of the carrier 45 of FIG. 1, it is illustrated in FIG. 7 that the optical component 6 is formed by the electrical redistribution layer 7 on the carrier upper side 44. For this purpose, the redistribution layer 7 is provided with a reflective coating, for example of silver. The redistribution layer 7 is exposed over as large an area as possible on the carrier upper side 44 and is preferably covered only to a very small extent by the laminate layer 63. To protect the redistribution layer 7 and to maintain a reflectivity for a long time, a protective layer not shown may be present, for example of silicon dioxide or of a nitride such as aluminum nitride.

[0111] In the exemplary embodiment of FIG. 8, it is shown that the optical component 6 is additionally formed by a lens 62, in addition to the reflective redistribution layer 7 on the carrier upper side 44, with the uppermost redistribution layer 7 being located in places on the upper laminate layer 63.

[0112] The top laminate layer 7, 6 is formed as a structural edge 47 for the lens 62. That is, when material for the lens is dispensed, this material extends exactly to the structural edge 47. Thus, a shape and a light exit side 10 of the lens 62 can be produced in a defined manner. The main emission direction M is oriented approximately perpendicular to the mounting side 46.

[0113] In the exemplary embodiment of FIG. 9, it is shown that the structural edge 47 for defining the lens 62 is formed by the laminate layer 63 on the carrier upper side 44. The laminate layer 63 is structured accordingly. The structural edge 47 is preferably formed by a trench which extends to the upper redistribution layer 7 and which preferably completely surrounds the lens 62.

[0114] In FIG. 10, it is shown that a multilayer structure of laminate layers 63 and redistribution layers 7 is present on the carrier upper side 44. A recess 82 is defined by the laminate layers 63 together with the uppermost redistribution layer 7. Preferably, both the top two redistribution layers 7 and the laminate layers 63 are formed to be reflective. It is possible that the semiconductor chip 2 is completely located in the recess 82.

[0115] In FIG. 11, there are also a plurality of laminate layers 63 and a top redistribution layer 7. Trenches in the top laminate layer 63 and/or in the top redistribution layer 7 define the shape of the lens 62. Thus, the structural edge 47 for defining the shape of the lens 62 is optionally multilayered.

[0116] The uppermost redistribution layers 7 of FIGS. 8, 10 and 11 are preferably electrically non-functionalized. That is, these redistribution layers 7 preferably serve only as optical components 6 and/or for adjusting the shape of the lens 62.

[0117] Preferably, as few redistribution layers 7, or RDLs for short, are used as possible to enable a low-cost structure of the semiconductor device 1.

[0118] FIGS. 12 to 14 show an example of a manufacturing method for optoelectronic semiconductor devices 1. Referring to FIG. 12, a carrier assembly 40 is provided which includes many of the subsequent carriers for the semiconductor devices 1. The carrier assembly 40 is preferably a continuous plate comprising the circuit chips 3. Already in the state of the carrier assembly 40, as illustrated in FIG. 12, a testing of the circuit chips 3 optionally is carried out.

[0119] In the step of FIG. 13, it is shown that the semiconductor chips 2 are each applied to the corresponding unit for the subsequent carriers 45. Separation into the semiconductor devices 1 takes place along separation lines S completely through the carrier assembly 40. The separation lines S are preferably arranged at a distance from the semiconductor chips 2 as well as from the circuit chips 3.

[0120] In the optional method step of FIG. 14 it is shown that the semiconductor chips 2 can be embedded in an embedding layer 65. The embedding layer 45 can be flush with the semiconductor chips 2 in the direction away from the mounting side 46. The embedding layer 65 is preferably made of a diffuse white reflective material, for example a silicone filled with titanium dioxide particles.

[0121] In addition, according to FIG. 14, an out-coupling layer 66 is optionally present, which may cover all semiconductor chips 2 as well as the embedding layer 65 as a continuous layer. The out-coupling layer 66 is preferably made of a transparent material. The main emission direction M is correspondingly oriented away from the mounting side 46. Optionally, the out-coupling layer may include scattering particles for light scattering or luminescent substances for wavelength conversion of a radiation generated by the semiconductor chips 2. Such an embedding layer 65 and/or such an out-coupling layer 66 may also be present in all exemplary embodiments.

[0122] The semiconductor chips 2 of FIGS. 1 to 14 shown so far are formed as flip chips. In contrast, semiconductor chips 2 with electrical contact regions on opposite main sides can also be used, see FIG. 15. For electrical contacting of the semiconductor chips 2, contacting structures 78 can be used which are configured as a through-connection to a top redistribution layer 7 and which are also formed by a conductor path running flat on the cover layer 64. Alternatively to flip chips, such a type of contacting may also be relied upon in all other exemplary embodiments. Furthermore, contacting is possible with the aid of bonding wires. In this case, all electrical connections can be placed on a side facing away from the lead frame parts 40, so that two or more than two bonding wires are then used for electrical contacting on this side.

[0123] In the method of FIGS. 16 and 17 it is shown how the semiconductor devices 1 can be produced with carriers of the type in particular of FIG. 3. Optionally, back etchings 41, i.e. recesses, can be created in the lead frame parts 4 from the mounting side 46. These back etchings 41 are located in the region of the separation lines S, see FIG. 17.

[0124] This allows solder control points 42 to be formed on the side surfaces of the carriers 45. The solder control points 42 are preferably provided with a coating wetting for solder, not shown. The solder control points 42 preferably do not extend to the matrix material 5 of the side surfaces of the carrier 45.

[0125] Corresponding lead frame parts 4 are shown in the schematic plan view of FIG. 19, wherein only the lead frame parts 4 are shown. The solder control points 42 are exposed on only one side surface of the carrier 45 per lead frame part 4, for example. Seen in a plan view, the solder control points 42 are preferably surrounded in a U-shape all around by a material of the lead frame parts 4.

[0126] Alternatively or in addition, the solder control points may be placed on opposite sides of a particular lead frame part. Thus, alternatively or in addition to the solder control points 42 drawn in FIG. 19, solder control points may be provided on the larger and/or on the smaller lead frame part 4 on the sides lying above and below in FIG. 19, i.e. in particular on opposite sides running parallel or substantially parallel to a longitudinal axis of the assembly of the two lead frame parts 4. In a direction perpendicular to such a longitudinal axis, the solder control points may be opposite to each other or be arranged offset from each other.

[0127] In FIGS. 16 to 19, such solder control points 42 are shown only for the lead frame parts 4. Analogously, however, such solder control points 42 may alternatively or additionally be provided on the redistribution layers 7.

[0128] FIGS. 20 and 21 show different sectional views of the carrier 45. The sectional view of FIG. 21 corresponds to a section along the dash line of FIG. 20. The solder control points 42 and thus back etchings 41 can accordingly be oriented transversely in comparison with FIGS. 16 to 19.

[0129] Furthermore, solder pads 77 can be defined not only on the lead frame parts 4 but also on the redistribution layer 7. With respect to their width and height, the solder pads 77 can be balanced. With such a configuration, as shown in FIGS. 20 and 21, in particular laterally emitting semiconductor devices 1 can be produced, whose main emission direction is transverse to the mounting side 46.

[0130] Preferred configurations of laterally emitting semiconductor devices 1 are explained in more detail in FIGS. 22 to 31. In FIGS. 22 and 23, an exemplary embodiment of the semiconductor device 1 is shown, see the sectional view of FIG. 22 and the side view of FIG. 23 of the light exit side 10.

[0131] The lens 62, which together with the redistribution layer 7 forms the optical components 6, is approximately hyperbolic and/or paraboloidal in cross-section according to FIG. 22. The lens 62 is exposed at the light exit side 10 and is flush with the matrix material 5, in a direction parallel to the mounting side 46. The lens is completely covered by the cover layer 64. This results in a particularly diffuse reflection of the light generated by the semiconductor chip 2 in operation at the cover layer 64 towards the direction parallel to the mounting side 46.

[0132] Seen in side view, see FIG. 23, the lens 62 preferably appears approximately semicircular. Due to the cover layer 64, the semiconductor device 1 may comprise an overall rectangular cross-section. A shaping of the lens 62 is preferably again performed via a structural edge 47, analogous to FIG. 8, 9 or 11.

[0133] In FIG. 24 a further exemplary embodiment of the semiconductor device 1 is illustrated. Unlike in FIG. 23, no laminate layer 63 is present at a cut edge of the lens 62. In all other respects, the exemplary embodiment of FIG. 24 corresponds to that of FIGS. 22 and 23.

[0134] In FIG. 25, a manufacturing method for the semiconductor devices 1 of FIGS. 22 to 24 is explained schematically. The lenses 62 are manufactured as approximately circular solid lenses when viewed in a plan and approximately semicircular solid lenses when viewed in cross section. Since the separation lines S preferably extend centrally through the lens 62, the geometry of the lenses 62 is formed as explained in FIGS. 22 to 24.

[0135] The cover layer 64 is produced, for example, by film assisted molding, or FAM for short. It is also possible to build up the cover layer 64 by first creating a dam, for example from a so-called glob top, wherein subsequently a filling of the dam is carried out with a material for the cover layer 64. The cover layer 64 is thus not necessarily cuboidal in cross-section and can be built up from several components.

[0136] FIG. 26 also shows a side emitter. Instead of a lens, there is a light-transmitting out-coupling layer 66 which is optionally provided with a luminescent substance. Seen in cross-section, the out-coupling layer 66 is approximately rectangular. The embedding layer 65 is generated via FAM, for example, and defines a subsequent shape of the out-coupling layer 66, which is preferably manufactured subsequently. The embedding layer 65 is preferably diffusely reflective and may appear white. The embedding layer 65 as well as the out-coupling layer 66 are optionally jointly covered by the preferably likewise diffusely reflective, white-appearing cover layer 64. The semiconductor device 1 of FIG. 26 can also be manufactured analogously to FIG. 25.

[0137] It is not necessary that the lens 62 or the out-coupling layer 66 of FIGS. 22 to 26 are exposed only on one side surface of the semiconductor device 1. Thus, two side surfaces can be provided with the lens 62 or with the out-coupling layer 66 via appropriate formation of the separation lines S. In the case of an out-coupling layer 66, it may also be exposed on three side surfaces.

[0138] If the out-coupling layer 66 is formed as a continuous, coherent layer, so that in particular no embedding layer 65 is present, the out-coupling layer 66 can also be exposed all around, so that light is emitted in the lateral direction all around. This is illustrated in FIG. 27.

[0139] In the exemplary embodiments of FIGS. 1 to 27, the carrier 45 is formed in each case as a type of circuit board or printed circuit board. In contrast, FIGS. 28 to 31 show designs of the semiconductor device 1 that are formed in a QFN-like manner. For this purpose, the lead frame parts 4 are each embedded in the matrix material 5 and are mechanically firmly connected to each other via the matrix material 5. The matrix material can again be a plastic, but ceramics or glasses can also be used.

[0140] In each case, the circuit chip 3 is embedded in the matrix material 5. Electrical contact is made with the circuit chip 3, for example, via bonding wires 71. The carrier 45 is thus relatively thick in the region of the circuit chip 3. In contrast, the semiconductor chip 2 is applied to one or more of the lead frame parts 4. In the region of the semiconductor chip 2, the carrier 45 is comparatively thin.

[0141] According to FIG. 28, the lens-shaped out-coupling layer 66 is located above the semiconductor chip 2. A shape of the out-coupling layer 66 is defined in the matrix material 5 via the structural edge 47. The out-coupling layer 66 and the matrix material 5 are in contact with each other. Optionally, the matrix material 5 and the lens 62 are covered by the cover layer 64, analogous, for example, to FIG. 24.

[0142] In FIG. 29 it is illustrated that the lateral emission of the semiconductor device 1 is achieved via the out-coupling layer 66 which is trapezoidal in cross-section, for example.

[0143] In a direction away from the mounting side 46, the out-coupling layer 66 as well as the matrix material 5 may be flush with each other and jointly covered by the cover layer 64, analogously to FIG. 26.

[0144] In FIGS. 30 and 31 it is illustrated that the circuit chip 3 may be integrated in a subcarrier 45′. The subcarrier 45′ is in particular formed as illustrated in connection with FIGS. 1 to 6, but preferably without an optoelectronic semiconductor chip. The devices 1 of FIGS. 30 and 31 may thus represent carrier-in-carrier configurations.

[0145] Deviating from FIGS. 28 to 30, it is not necessary that the circuit chip 3 of FIG. 31 or the subcarrier 45′ be mounted on a single one of the lead frame parts 4. Thus, the circuit chip 3 or the subcarrier 45′ may extend over several of the lead frame parts 4. It is thus also possible that additional electrical contacting, for example via bonding wires 71, may be omitted. In all other respects the components of FIGS. 30 and 31 correspond to those of FIG. 29.

[0146] Semiconductor devices described here can be used, for example, in reflex light barriers, or RLS for short.

[0147] Unless otherwise indicated, the components shown in the figures preferably follow one another directly in the order indicated. Layers not touching each other in the figures are preferably spaced apart. Where lines are drawn parallel to each other, the corresponding surfaces are preferably also aligned parallel to each other. Likewise, unless otherwise indicated, the relative positions of the drawn components to each other are correctly reproduced in the figures.

[0148] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims and any combination of features in the exemplary embodiments, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

[0149] This patent application claims priority to German patent application 10 2019 104 325.5, the disclosure content of which is hereby incorporated by reference.

REFERENCES

[0150] 1 optoelectronic semiconductor device [0151] 10 light exit side [0152] 2 optoelectronic semiconductor chip [0153] 3 circuit chip [0154] 4 lead frame part [0155] 40 carrier assembly [0156] 41 back etching [0157] 42 solder control point [0158] 44 carrier upper side [0159] 45 carrier [0160] 46 mounting side [0161] 47 structural edge [0162] 5 matrix material [0163] 6 optical component [0164] 61 reflection layer [0165] 62 lens [0166] 63 laminate layer [0167] 64 cover layer [0168] 65 embedding layer [0169] 66 out-coupling layer [0170] 7 electrical redistribution layer [0171] 71 bonding wire [0172] 72 electrical bonding agent [0173] 74 electrical through-connection [0174] 76 solder ball [0175] 77 solder pad [0176] 78 contacting structure [0177] 81 further laminate layer [0178] 82 recess [0179] M main emission region [0180] S separation lines