Copper Filled Recess Structure and Method for Making the Same

Abstract

The present application discloses a copper filled recess structure, which comprises a recess formed in a first dielectric layer; a block layer is formed on the bottom surface and side surfaces of the recess; a cobalt layer and a ruthenium layer are formed on the surface of the block layer; a copper layer completely fills the recess; a supportive nucleation film layer of the copper layer is formed by superposing the cobalt layer and the ruthenium layer. The present application further discloses a method for making a copper filled recess structure. Since the copper layer in the present application does not contain a copper seed layer and completely consists of the electrochemically-plated copper film, the ability of filling copper in the recess can be improved, and it is especially suitable for use as a copper connection and a via at a process node of less than 14 nm.

Claims

1. A copper filled recess structure, wherein the copper filled recess structure comprises: a recess formed in a first dielectric layer; a block layer is formed on the bottom surface and side surfaces of the recess; a cobalt layer is formed on the surface of the block layer and a ruthenium layer is formed on the surface of the cobalt layer; a copper layer completely fills the recess on which the block layer, the cobalt layer and the ruthenium layer are formed, so as to form the copper filled recess structure; the copper layer completely consists of an electrochemically-plated copper film; a supportive nucleation film layer of the copper layer is formed by superposing the cobalt layer and the ruthenium layer; the supportive nucleation film layer enables the copper layer to have a structure in which the electrochemically-plated copper film and the ruthenium layer are in direct contact, such that a region filled with the electrochemically-plated copper film is a region surrounded by the supportive nucleation film layer.

2. The copper filled recess structure according to claim 1, wherein the recess is a trench and the copper filled recess structure is a copper interconnection; or the recess is an opening of a via and the copper filled recess structure is the via.

3. The copper filled recess structure according to claim 2, wherein the first dielectric layer is an interlayer film.

4. The copper filled recess structure according to claim 1, wherein the barrier layer is a single layer of TaN or TiN, or a multilayer composed of TaN and Ta or TiN and Ti.

5. The copper filled recess structure according to claim 1, wherein the thickness of the cobalt layer is 5 Å-30 Å.

6. The copper filled recess structure according to claim 5, wherein the thickness of the ruthenium layer is 5 Å-40 Å.

7. The copper filled recess structure according to claim 3, wherein the interlayer film is formed on a semiconductor substrate, a semiconductor device is formed on the semiconductor substrate, and the copper interconnection forms an electrode leading-out structure of the semiconductor device.

8. The copper filled recess structure according to claim 7, wherein the process node of the semiconductor device is less than 14 nm.

9. A method for making a copper filled recess structure, wherein the method for making the copper filled recess structure comprises the following steps: step 1: forming a recess in a first dielectric layer; step 2: forming a block layer on the bottom surface and side surfaces of the recess; step 3: forming a cobalt layer on the surface of the block layer; step 4: forming a ruthenium layer on the surface of the cobalt layer, a supportive nucleation film layer of the copper layer being formed by superposing the cobalt layer and the ruthenium layer; and step 5: directly performing a copper electrochemical plating process to form a copper layer completely consisting of an electrochemically-plated copper film on the supportive nucleation film layer, the copper layer completely filling the recess on which the block layer, the cobalt layer and the ruthenium layer are formed, so as to form the copper filled recess structure.

10. The method for making the copper filled recess structure according to claim 9, wherein the recess is a trench and the copper filled recess structure is a copper interconnection; or the recess is an opening of a via and the copper filled recess structure is the via.

11. The method for making the copper filled recess structure according to claim 10, wherein the first dielectric layer is an interlayer film.

12. The method for making the copper filled recess structure according to claim 9, wherein the barrier layer is a single layer of TaN or TiN, or a multilayer composed of TaN and Ta or TiN and Ti.

13. The method for making the copper filled recess structure according to claim 9, wherein the thickness of the cobalt layer is 5 Å-30 Å.

14. The method for making the copper filled recess structure according to claim 13, wherein the thickness of the ruthenium layer is 5 Å-40 Å.

15. The method for making the copper filled recess structure according to claim 11, wherein the interlayer film is formed on a semiconductor substrate, a semiconductor device is formed on the semiconductor substrate, and the copper interconnection forms an electrode leading-out structure of the semiconductor device.

16. The method for making the copper filled recess structure according to claim 15, wherein the process node of the semiconductor device is less than 14 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The present application will be further described below in detail in combination with the embodiments with reference to the drawings.

[0053] FIG. 1 is a structural schematic view of a copper filled recess structure formed by adopting an existing first method for making the copper filled recess structure.

[0054] FIG. 2 is a structural schematic view of a copper filled recess structure formed by adopting an existing second method for making the copper filled recess structure.

[0055] FIG. 3 is a structural schematic view of a copper filled recess structure according to one embodiment of the present application.

[0056] FIG. 4 is a flowchart of a method for making a copper filled recess structure according to one embodiment of the present application.

DETAILED DESCRIPTION OF THE APPLICATOIN

[0057] Referring to FIG. 3, it is a structural schematic view of a copper filled recess structure according to one embodiment of the present application. The copper filled recess structure according to one embodiment of the present application includes:

[0058] a recess 2 formed in a first dielectric layer 1.

[0059] A block layer 3 is formed on the bottom surface and side surfaces of the recess 2.

[0060] In one embodiment of the present application, the block layer 3 is a TaN layer. In other embodiments, the block layer 3 may also be a TiN layer or a multilayer composed of TaN and Ta or TiN and Ti.

[0061] A cobalt layer 4 is formed on the surface of the block layer 3 and a ruthenium layer 5 is formed on the surface of the cobalt layer 4.

[0062] A copper layer 6 completely fills the recess 2 on which the block layer 3, the cobalt layer 4 and the ruthenium layer 5 are formed, so as to form the copper filled recess structure.

[0063] The copper layer 6 completely consists of an electrochemically-plated copper film.

[0064] A supportive nucleation film layer of the copper layer 6 is formed by superposing the cobalt layer 4 and the ruthenium layer 5.

[0065] The supportive nucleation film layer enables the copper layer 6 to have a structure in which the electrochemically-plated copper film and the ruthenium layer 5 are in direct contact, such that a region filled with the electrochemically-plated copper film is a region surrounded by the supportive nucleation film layer. From FIG. 3, it can be seen that there is no copper seed layer in the copper layer 6, thus overcoming a overhang effect produced by the copper seed layer and preventing the top opening of the recess 2 from being decreased due to the overhang effect of the copper seed layer, such that the width d1 of the top opening of the recess 2 can be kept to be greater, the filling of the electrochemically-plated copper film of the copper layer 6 is facilitated, and the filling process window and filling quality can be improved.

[0066] In one embodiment of the present application, the first dielectric layer 1 is an interlayer film.

[0067] The interlayer film is formed on a semiconductor substrate, a semiconductor device is formed on the semiconductor substrate, and the copper interconnection forms an electrode leading-out structure of the semiconductor device.

[0068] The process node of the semiconductor device is less than 14 nm.

[0069] The recess 2 is a trench and the copper filled recess structure is a copper interconnection;

[0070] or the recess 2 is an opening of a via and the copper filled recess structure is the via.

[0071] The thickness of the cobalt layer 4 is 5 Å-30 Å.

[0072] The thickness of the ruthenium layer 5 is 5 Å-40 Å.

[0073] In the copper filled recess structure provided by the embodiment of the present application, the supportive nucleation film layer of the copper layer 6 formed by superposing the cobalt layer 4 and the ruthenium layer 5 is adopted before the electrochemically-plated copper film is formed. Since the ruthenium layer has low electrochemical potential energy, copper electrochemical plating can be directly performed on the ruthenium layer 5. Moreover, ruthenium oxide, i.e., RuOx, has good conductivity, so even if ruthenium is oxidized in acidic ECP solution, it will not affect the conductivity of the copper filled recess structure. However, if the ruthenium layer 5 is used alone to form the copper layer 6, the reliability is poor, so the ruthenium layer 5 cannot be used as the supportive nucleation layer of the electrochemically-plated copper film.

[0074] In addition, just as the ruthenium layer 5 facilitates copper nucleation, the cobalt layer 4 also facilitates copper nucleation, that is, the cobalt layer 5 and the ruthenium layer 5 both facilitate copper nucleation. However, Co is not compatible with acidic ECP solution, it is easily dissolved and the oxide of Co is not conductive, which makes the conductivity of the whole copper filled recess structure be poor when the cobalt layer 4 is used alone to form the copper layer 6, so the cobalt layer 4 cannot be used alone as the supportive nucleation film layer of the electrochemically-plated copper film.

[0075] By combining the cobalt layer 4 with the ruthenium layer 5 and providing the ruthenium layer 5 between the cobalt layer 4 and the copper layer 6, the embodiment of the present application can overcome the defect that the ruthenium layer 5 or the cobalt layer 5 provided alone cannot be used as the supportive nucleation film layer of the electrochemically-plated copper film, and finally the electrochemically-plated copper film with good reliability can be obtained without adopting the copper seed crystal layer, thus overcoming the defect that the filling of the electrochemically-plated copper film is not facilitated due to the reduction of the opening of the recess 2 which is easily caused by the use of the copper seed layer, such that the ability of filling copper in the recess 2 can be improved, the process window of filling copper in the recess 2 can be improved, the reliability can be kept excellent at the same time, the reduction of the dimension of the copper filled recess structure is facilitated, and it is especially suitable for use as a copper connection and a via at a process node of less than 14 nm.

[0076] Referring to FIG. 4, it is a flowchart of a method for making the copper filled recess structure according to one embodiment of the present application. The copper filled recess structure formed by adopting the method for making the copper filled recess structure according to one embodiment of the present application is as illustrated in FIG. 3. The method for making the copper filled recess structure according to one embodiment of the present application includes the following steps:

[0077] In step 1, a recess 2 is formed in a first dielectric layer 1.

[0078] In step 2, a block layer 3 is formed on the bottom surface and side surfaces of the recess 2.

[0079] In one embodiment of the present application, the block layer 3 is a TaN layer. In other embodiments, the block layer 3 may also be a TiN layer or a multilayer composed of TaN and Ta or TiN and Ti.

[0080] In step 3, a cobalt layer 4 is formed on the surface of the block layer 3.

[0081] In step 4, a ruthenium layer 5 is formed on the surface of the cobalt layer 4.

[0082] A supportive nucleation film layer of the copper layer 6 is formed by superposing the cobalt layer 4 and the ruthenium layer 5.

[0083] In step 5, a copper electrochemical plating process is directly performed to form a copper layer 6 completely consisting of an electrochemically-plated copper film on the supportive nucleation film layer. The copper layer 6 completely fills the recess 2 on which the block layer 3, the cobalt layer 4 and the ruthenium layer 5 are formed, so as to form the copper filled recess structure.

[0084] In the method according to one embodiment of the present application, the first dielectric layer 1 is an interlayer film.

[0085] The interlayer film is formed on a semiconductor substrate, a semiconductor device is formed on the semiconductor substrate, and the copper interconnection forms an electrode leading-out structure of the semiconductor device.

[0086] The process node of the semiconductor device is less than 14 nm.

[0087] The recess 2 is a trench and the copper filled recess structure is a copper interconnection;

[0088] or the recess 2 is an opening of a via and the copper filled recess structure is the via.

[0089] The thickness of the cobalt layer 4 is 5 Å-30 Å.

[0090] The thickness of the ruthenium layer 5 is 5 Å-40 Å.

[0091] Compared with the existing first method for making the copper filled recess structure and the existing second method for making the copper filled recess structure, it can be seen that the method for making the copper filled recess structure according to one embodiment of the present application adopts a TaN+Co+Ru process, for reasons as follows:

[0092] Both Co and Ru facilitate the nucleation of Cu. However, Co is not compatible with acidic ECP bath and is easily dissolved. Moreover, the oxide of Co is not conductive. Therefore, in the method according to one embodiment of the present application, the cobalt layer 4 is placed on the lower layer of the ruthenium layer 5. However, the electrochemical potential energy of the ruthenium layer 5 is low, and even electroless deposited (ELD) copper plating can be performed. In addition, the conductivity of the oxide of the ruthenium layer 5 (RuOx) is very good, so the top layer in the method according to one embodiment of the present is the ruthenium layer 5. However, since the reliability of the ruthenium layer 5, i.e., ElectroMigration (EM) of metals, is poor, and Co can significantly improve the reliability (EM), this is the reason why Co exists.

[0093] Finally, the method according to one embodiment of the present application can increase the process window (Cu gapfill window) of the copper filled recess at the technology node of less than 14 nm, is applicable to BEOL interconnection technologies of smaller dimension, and can keep excellent EM performance at the same time.

[0094] The present application has been described above in detail through the specific embodiments, which, however, do not constitute limitations to the present application. Without departing from the principle of the present application, those skilled in the art may make many modifications and improvements, which should also be regarded as included in the scope of protection of the present application.