MOS TRANSISTOR ISOLATED FROM THE SUBSTRATE OF AN INTEGRATED CIRCUIT AND APPLICATION FOR DETECTING AN OPENING OF A CLOSED CONTAINER

Abstract

An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.

Claims

1. A system, comprising: a closed container; an integrated circuit having a first substrate and first and second terminals; an electrically conductive wire connecting the first and second terminals and having a severable part that is arranged to be severed in the event of an opening or attempted opening of the closed container, and a detection device configured to detect a severing of the severable part; wherein the detection device includes, within the integrated circuit: a first capacitor electrically isolated from the first substrate of the integrated circuit and connected to the first terminal; a first MOS transistor having source and drain regions that are electrically isolated from the first substrate, and a gate region connected to the second terminal, wherein said first MOS transistor is configured to be in an on-state in response to a zero voltage applied to the gate region and in an off-state in response to a non-zero voltage applied to the gate region; a second capacitor electrically isolated from the first substrate of the integrated circuit and having a first electrode connected to the drain region of the first MOS transistor; and a measuring circuit configured to measure a voltage at said first electrode, wherein the voltage of said first electrode is indicative of a present or past severing of said severable part if said voltage is lower than a threshold.

2. The system according to claim 1, wherein the first MOS transistor comprises: a first polysilicon region electrically isolated from the first substrate and including the gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including the source region, a substrate region and the drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region.

3. The system according to claim 2, wherein the substrate region of the second polysilicon region for the first MOS transistor is less heavily doped than the first polysilicon region.

4. The system according to claim 2, wherein the substrate region of the second polysilicon region for the first MOS transistor comprises one of: intrinsic polysilicon or doped polysilicon with a dopant concentration of less than 10.sup.17 atoms/cm.sup.3.

5. The system according to claim 2, wherein the first polysilicon region has a dopant concentration of more than 10.sup.19 atoms/cm.sup.3.

6. The system according to claim 2, wherein the first MOS transistor is a PMOS transistor.

7. The system according to claim 6, wherein the source region the first MOS transistor connected to ground and wherein the first MOS transistor has a threshold voltage such that it is in an on state in response to a zero voltage is applied to the gate region and in an off state in in response to a negative bias applied to the gate region.

8. The system according to claim 1, wherein each of the first capacitor and the second capacitor comprises two polysilicon electrodes separated by a dielectric and resting on an isolating region of the integrated circuit.

9. The system according to claim 1, further comprising: a contactless passive transponder configured to communicate with a reader via an antenna by using a carrier signal, the contactless passive transponder including the integrated circuit having two antenna terminals connected to the antenna; wherein the integrated circuit further includes a comparison circuit configured to compare the voltage of said first electrode with said threshold; and a processing circuit configured to: command a charging of the first capacitor in response to a first command from the reader; command a charging of the second capacitor in response to a second command from the reader; activate the measuring circuit in response to an activation command from the reader; and communicate a result of said comparison in response to a read command from the reader.

10. A method for detecting whether a severable part of an electrically conductive wire connecting first and second terminals of an integrated circuit has been severed in the event of an opening or attempted opening of a closed container, comprising: charging a first capacitor electrically isolated from a first substrate of the integrated circuit and connected to the first terminal; charging a second capacitor electrically isolated from the first substrate of the integrated circuit and having a first electrode connected to a drain region of a first MOS transistor; and using said first MOS transistor to take at least one measurement of a voltage of the first electrode of the second capacitor and compare the measured voltage to a threshold.

11. The method according to claim 10, wherein charging the first and second capacitors comprises charging only once, wherein using comprises taking a plurality of measurements of the voltage of the first electrode at distant measuring times comparing the plurality of measurements to said threshold, wherein a measured voltage that is below said threshold at one of said distant measuring times is indicative of the severable part having been severed at or before said one of said distant measuring times.

12. A system, comprising: an integrated circuit, including: a first substrate; and at least one first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region.

13. The system according to claim 12, wherein the substrate region of the second polysilicon region for the first MOS transistor is less heavily doped than the first polysilicon region.

14. The system according to claim 12, wherein the substrate region of the second polysilicon region for the first MOS transistor comprises one of: intrinsic polysilicon or doped polysilicon with a dopant concentration of less than 10.sup.17 atoms/cm.sup.3.

15. The system according to claim 12, wherein the first polysilicon region has a dopant concentration of more than 10.sup.19 atoms/cm.sup.3.

16. The system according to claim 12, wherein the first MOS transistor is a PMOS transistor.

17. The system according to claim 16, wherein the source region the first MOS transistor connected to ground and wherein the first MOS transistor has a threshold voltage such that it is in an on state in response to a zero voltage is applied to the gate region and in an off state in in response to a negative bias applied to the gate region.

18. The system according to claim 12, wherein the first MOS transistor is an NMOS transistor.

19. The system according to claim 12, wherein the integrated circuit further comprises an isolation trench located in the first substrate, and wherein the first polysilicon region is located above the isolation trench.

20. The system according to claim 19, wherein, in a source-drain direction of the first MOS transistor, the first polysilicon region extends beyond the second polysilicon region and wherein the second polysilicon region rests on the first polysilicon region via a first dielectric region.

21. The system according to claim 19, wherein: the first polysilicon region extends beyond the second polysilicon region in a direction perpendicular to a source-drain direction of the first MOS transistor; and in the source-drain direction of the first MOS transistor, a dimension of the second polysilicon region is greater than a dimension of the first polysilicon region and the second polysilicon region rests on the first polysilicon region and on the isolation trench via a second dielectric region.

22. The system according to claim 19, wherein: the first polysilicon region extends beyond the second polysilicon region in a direction perpendicular to a source-drain direction of the first MOS transistor; and in the source-drain direction of the first MOS transistor, a dimension of the second polysilicon region is greater than a dimension of the first polysilicon region, and the second polysilicon region rests on the first polysilicon region via a third dielectric region, and further rests on the isolation trench.

23. The system according to claim 12, wherein the integrated circuit further comprises: an isolation trench located in the first substrate; and a dielectric layer surrounding the first polysilicon region, wherein the first polysilicon region is surrounded by the dielectric layer thereof extending through the isolation trench into the first substrate, and wherein the substrate region of the first MOS transistor rests at least partially on one end of the first polysilicon region surrounded by said dielectric layer and the source and drain regions resting on the isolation trench.

24. The system according to claim 23, wherein the integrated circuit further comprises at least one non-volatile memory cell of a type having a select transistor with a gate buried in the first substrate, and wherein the first polysilicon region has a shape like that of the gate of said select transistor.

25. The system according to claim 12, wherein the integrated circuit further comprises: a dielectric layer disposed between the first polysilicon region and the first substrate; and a second MOS transistor including, in the first substrate, a source region, a drain region and a substrate region between the source and drain regions and covered by said dielectric layer, the first polysilicon region including a gate region common to the first MOS transistor and to the second MOS transistor.

26. The system according to claim 25, wherein the second MOS transistor is one of an NMOS transistor or a PMOS transistor.

27. A method for manufacturing an MOS transistor within an integrated circuit having a first substrate, comprising: forming a first polysilicon region electrically isolated from the first substrate; forming a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region; forming, within the second polysilicon region, a source region and a drain region located on either side of a substrate region of the MOS transistor; forming at least one source contact area on the source region and at least one drain contact area on the drain region; and forming at least one gate contact area on the first polysilicon region.

28. The method according to claim 27, further comprising in situ doping of the first polysilicon region.

29. The method according to claim 28, wherein the substrate region has an absence of doping.

30. The method according to claim 28, wherein a doping of the substrate region is weaker than the in situ doping of the first polysilicon region.

31. The method according to claim 27, further comprising forming an isolation trench in the first substrate and forming the first polysilicon region above said isolation trench.

32. The method according to claim 27, further comprising producing non-volatile memory select transistor gates buried in the first substrate simultaneously with forming the first polysilicon region.

33. The method according to claim 27, further comprising forming a floating gate of a dual-gate state transistor of a non-volatile memory cell simultaneously with forming the first polysilicon region.

34. The method according to claim 27, further comprising forming a gate of a low-voltage transistor of a memory circuitry simultaneously with forming the second polysilicon region.

35. The method according to claim 27, wherein the MOS transistor is one of a PMOS transistor or an NMOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Other advantages and features will become apparent upon examining the detailed description of non-limiting embodiments and implementations of the invention, and from the accompanying drawings in which:

[0089] FIGS. 1-7 illustrate cross-sectional views of transistor embodiments;

[0090] FIG. 8 is a flow diagram for a method of making;

[0091] FIGS. 9-14 show steps in a method of making;

[0092] FIG. 15 illustrates a cross-sectional view of a transistor embodiment;

[0093] FIGS. 16-18 show use in a package opening detection implementation;

[0094] FIG. 19 is a circuit diagram for a package opening detection circuit;

[0095] FIG. 20 illustrates a cross-sectional view of a capacitor for the circuit of FIG. 19;

[0096] FIG. 21 illustrates a relationship between current and voltage;

[0097] FIG. 22 illustrates a cross-sectional view of a transistor embodiment;

[0098] FIGS. 23-24 are flow diagrams for a method of detecting;

[0099] FIG. 25 is a block diagram of a near field communication implementation; and

[0100] FIG. 26 is a flow diagram for operation.

DETAILED DESCRIPTION

[0101] In FIG. 1, the reference IC is used to denote an integrated circuit including a substrate SB1, referred to hereinafter as the “first substrate” so as to distinguish it from the substrate region RSB of the first transistor TRP, the structure of which will now be described.

[0102] This first transistor TRP, which in this case is a PMOS transistor, has a first polysilicon region P1 resting on the insulating material of a shallow trench-type isolation trench 1 made in the first substrate SB1.

[0103] This first polysilicon region P1 is thus electrically isolated from the first substrate SB1.

[0104] This first polysilicon region P1 includes a gate region RG of the first transistor TRP.

[0105] The first transistor TRP further comprises a second polysilicon region P2 electrically isolated from the first polysilicon region P1 via a first dielectric region 2 on which it rests.

[0106] In this example, the first dielectric region 2 includes a gate oxide 21 flanked by two dielectric stacks 20 each including, for example, a silicon oxide-silicon nitride-silicon oxide (ONO) stack.

[0107] Since this second polysilicon region P2 is electrically isolated from the first polysilicon region P1, and since this first polysilicon region P1 is electrically isolated from the first substrate SB1, the second polysilicon region P2 is also electrically isolated from the first substrate SB1.

[0108] The second polysilicon region P2 includes a source region RS, a substrate region RSB and a drain region RD of the first transistor TRP.

[0109] Thus, as shown in FIG. 1, the first polysilicon region P1 is located between an area Z of the first substrate SB1 and the second polysilicon region P2.

[0110] In this example embodiment, the first polysilicon region P1 protrudes from (i.e., beyond) the second polysilicon region P2 in the source-drain direction of the first transistor and the second polysilicon region rests, as stated hereinabove, on the first polysilicon region via the first dielectric region 2.

[0111] The protruding part P1D of the first polysilicon region P1 allows a silicided area SG of gate contact intended to receive a contact CG of a conventional and known structure, to be produced on the surface thereof.

[0112] The first polysilicon region P1 can be doped fairly heavily, for example with a dopant concentration greater than or equal to 10.sup.19 atoms/cm.sup.3.

[0113] The substrate region of the first transistor is less heavily doped than the first polysilicon region P1.

[0114] Thus, this substrate region RSB (vertical to the gate oxide 21) can comprise intrinsic polysilicon, i.e., polysilicon with a dopant concentration of less than or equal to 10.sup.15 atoms/cm.sup.3. It could also be doped with a dopant concentration of less than 10.sup.17 atoms/cm.sup.3 while, of course, remaining lower than the dopant concentration of the first polysilicon region P1.

[0115] The doping of the substrate region RSB allows the threshold voltage of the first transistor TRP to be adjusted.

[0116] In this example, since the first transistor TRP is a PMOS transistor, the source RS and drain RD regions are P+ doped (and are vertical to the gate oxides 20).

[0117] Moreover, in a conventional and known manner, the source region RS includes, on the top surface thereof, a silicided source contact area SS intended to receive a source contact CS having a conventional structure.

[0118] The drain region RD includes, on the top surface thereof, a silicided drain contact area SD intended to receive a drain contact CD having a conventional structure.

[0119] A first transistor TRN shown in FIG. 2 differs simply from the first transistor TRP in FIG. 1 in that the transistor TRN is an NMOS transistor with, in this case, the source RS and drain RD regions being N+ doped.

[0120] FIG. 3 and FIG. 4 (which is a section along line IV-IV in FIG. 3) diagrammatically show another embodiment of a first transistor TRP which again is a PMOS transistor, with it being understood that it could also be an NMOS transistor depending on the type of doping of the source and drain regions thereof. In the embodiment shown in FIG. 3, the dimension of the second polysilicon region P2 is shown in this case to be larger, in the source-drain direction, than the dimension of the first polysilicon region P1.

[0121] In this case, the second polysilicon region P2 rests on the first polysilicon region and on the isolation trench 1 via a second dielectric region 3. This second dielectric region includes, similarly to the first dielectric region 2, a silicon oxide-silicon nitride-silicon oxide stack 30 and a gate oxide 31.

[0122] The source and drain regions rest on the isolating region via the stacks 30, whereas the substrate region RSB rests partially on the first polysilicon region 1 via the gate oxide 31.

[0123] Moreover, as shown in FIG. 4, the first polysilicon region P1 in this case protrudes (i.e., extends) from the second polysilicon region P2 in a direction perpendicular to the source-drain direction of the first transistor.

[0124] Moreover, the silicided gate contact area SG intended to receive the gate contact CG is again located on this protruding part P1D.

[0125] The substrate region RSB further includes, on the top surface thereof, a silicided substrate contact area SSB intended to receive a substrate contact CRSB.

[0126] It should be noted that, in FIGS. 1 and 2, this substrate contact is not shown for simplification purposes.

[0127] The transistor TRP in FIG. 5 differs from the transistor TRP in FIG. 3 in that the silicon oxide-silicon nitride-silicon oxide stack 30 has been removed.

[0128] Moreover, in this embodiment, the second polysilicon region P2 rests on the first polysilicon region P1 via a third dielectric region 40, which in this case is a gate oxide, and also rests directly on the isolation trench 1 at the source RS and drain RD regions.

[0129] Moreover, the first polysilicon region P1 protrudes(i.e., extends) from the second polysilicon region P2 in a direction perpendicular to the source-drain direction of the first transistor in a manner similar to that shown in FIG. 4.

[0130] Reference is now made more particularly to FIGS. 6 and 7, which show another alternative embodiment of a first MOS transistor, which again is a PMOS transistor, with it being understood that it could also be an NMOS transistor depending on the type of doping of the source and drain regions thereof.

[0131] Again, the integrated circuit IC includes an isolation trench 1 located in the first substrate SB1.

[0132] In this alternative embodiment, the first polysilicon region P1 is surrounded by a dielectric layer 5, for example silicon dioxide.

[0133] Moreover, the first polysilicon region P1 surrounded by the dielectric layer 5 thereof extends through the isolation trench 5 into the first substrate SB1.

[0134] Furthermore, the second polysilicon region P2 still includes the source region RS, the drain region RD and the substrate region RSB located between the source region RS and the drain region RD.

[0135] The substrate region RSB of the transistor TRP rests at least partially on an end 51 of the first polysilicon region surrounded by the dielectric layer 5, whereas the source RS and drain RD regions rest on the isolation trench 1.

[0136] Thus, also in this alternative embodiment, the first polysilicon region P1 is located between an area Z of the first substrate and the second polysilicon region P2.

[0137] The second polysilicon region is again electrically isolated from the first polysilicon region and also electrically isolated from the first substrate SB1.

[0138] As shown in FIG. 7, which is a section along line VII-VII in FIG. 6, the first polysilicon region P1 surrounded by the dielectric layer 5 thereof protrudes (i.e., extends) from the second polysilicon region P2 in a direction perpendicular to the drain-source direction, which allows, as described with reference to FIG. 4, at the gate contact CG, contact to be made with the silicided area SG.

[0139] This alternative embodiment is thus compatible with a method for manufacturing non-volatile memory cells of the type having a select transistor with a gate buried in the first substrate SB1.

[0140] More specifically, the first buried polysilicon region can be produced simultaneously with the production of the buried gates of the select transistors of these memories.

[0141] Moreover, the first polysilicon region thus has, for example, a shape similar to that of the buried gate of such a select transistor.

[0142] In practice, the first MOS transistor comprises, on the top surface of the second polysilicon region P2, a protective layer intended to protect the underlying part of the second polysilicon region P2 during the silicidation step to obtain the silicided areas.

[0143] For simplification purposes in FIGS. 1 to 7, this protective layer is not shown in these figures, but will be referred to in the description of FIG. 8 and will be shown in FIGS. 13 to 15.

[0144] Reference is now made more particularly to FIG. 8 to describe one implementation of a method for manufacturing a first MOS transistor.

[0145] In the substrate SB1, the first polysilicon region P1 isolated from the first substrate SB1 is formed (step ST80).

[0146] By way of example, after the shallow trench type isolation trench 1 has been produced in a conventional manner, the formation of the first polysilicon region P1 can comprise depositing polysilicon followed by etching (in the case, for example, of the embodiments shown in FIGS. 1 to 5), or depositing in a deep trench followed by chemical-mechanical polishing (in the case, for example, of the embodiment shown in FIGS. 6 and 7). In this respect, more specifically, after having produced the shallow trench 1, a deep engraving is carried out through this trench 1 in order to produce the deep trench, followed by an oxidation of this deep trench. A layer of polysilicon is then deposited to fill the trench and the excess polysilicon is removed, for example by chemical-mechanical polishing.

[0147] Optionally, in situ doping ST81 of the first polysilicon region can be provided if a step similar to that of a conventional CMOS manufacturing method is used.

[0148] Then, in step ST82, the second polysilicon region P2 isolated from the first polysilicon region P1 and from the first substrate SB1 is formed.

[0149] For information, this formation can firstly comprise forming a dielectric region (for example a silicon oxide growth) on the polysilicon region formed in step ST80, then depositing a second polysilicon level followed by etching, or in the case of a first buried polysilicon region, depositing a polysilicon level on the isolation trench followed by etching, to form the second polysilicon region P2.

[0150] At this stage, the first polysilicon region P1 is obtained between an area of the first substrate SB1 and the second polysilicon region P2.

[0151] Then, in step ST83, the source RS and drain RD regions are formed in a conventional manner known per se, with the substrate region RSB being located between the source and drain regions and being less heavily doped than the first polysilicon region P1.

[0152] Optionally, localized doping of this substrate region RSB can be carried out in order to adjust the threshold voltage of the transistor.

[0153] Then, in step ST84, the silicided areas SS, SB and SG are formed in a conventional and known manner after having protected the non-silicided areas with the protective layer mentioned hereinabove.

[0154] Reference is now made more particularly to FIGS. 9 to 14, which show in more detail one implementation of a method for producing a transistor such as that described in FIG. 1.

[0155] In FIG. 9, after having produced the isolation trench 1 in the first substrate SB1 of the integrated circuit in a conventional and known manner, the first polysilicon region P1 is formed by polysilicon deposition and then etching.

[0156] The formation of this first polysilicon region can, for example, be carried out simultaneously with the formation of the floating gate of a dual-gate state transistor of a non-volatile memory cell.

[0157] In FIGS. 10 to 14, for simplification purposes, the first substrate SB1 is no longer shown.

[0158] Then, as shown in FIG. 10, the first polysilicon region P1 is covered with the first dielectric region 2 including a silicon oxide growth and a deposition of a silicon oxide-silicon nitride-silicon oxide stack. In practice, the silicon oxide-silicon nitride-silicon oxide stack is firstly deposited and then the area in which the silicon oxide growth will take place is masked. The stack is removed in this area and then the silicon oxide growth is carried out in this area.

[0159] Then, as shown in FIG. 11, the second polysilicon region P2 which rests on a part of the dielectric region 2 is formed by depositing a second polysilicon level and then etching.

[0160] The formation of this second polysilicon region can, for example, be carried out simultaneously with the formation of the gate of a low-voltage transistor of a memory circuitry for example, i.e., a transistor capable of withstanding a gate-source voltage of, for example, less than or equal to 3 volts.

[0161] In FIG. 12, the lateral isolating regions or spacers ESP1 on the flanks of the first region P1 and the spacers ESP2 on the flanks of the second region P2 are produced in a conventional and known manner.

[0162] The second polysilicon region P2 is then locally implanted to form the source RS and drain RD regions.

[0163] The above-mentioned protective layer SPRT is then deposited (FIG. 13) on the top surface of the second polysilicon region P2 to protect the underlying part of the second polysilicon region P2 during the silicidation step described in FIG. 14.

[0164] More specifically, during this silicidation step, the silicided areas SS, SG and SD are produced in a conventional and known manner.

[0165] Reference is now made more particularly to FIG. 15, which shows an example embodiment of two transistors TR1 and TR2.

[0166] The first transistor TR1 is a transistor with a structure similar to that described with reference to FIGS. 1 and 2.

[0167] In this example, the first transistor TR1 is an NMOS transistor, but it goes without saying that the transistor TR1 could also be a PMOS transistor with P+ doping of the source RS1 and drain RD1 regions.

[0168] In FIG. 15, the layer protecting against silicidation and covering the substrate region RSB1 of the transistor TR1 is also shown, as well as part of the source RS1 and drain RD1 regions.

[0169] The first polysilicon region P1 of the first transistor TR1 rests on the first substrate SB1 of the integrated circuit IC via a dielectric layer 6, for example a gate oxide.

[0170] Moreover, the integrated circuit IC thus includes a second transistor TR2, in this case an NMOS transistor.

[0171] This second transistor TR2 includes, in the first substrate SB1, a source region RS2, a drain region RD2 and a substrate region RSB2 between the source and drain regions, this substrate region RSB2 being covered by the dielectric layer 2.

[0172] Moreover, the first polysilicon region P1 includes a gate region common to the first transistor TR1 and to the second transistor TR2.

[0173] It goes without saying that the second transistor TR2 could be a PMOS transistor if the source RS2 and drain RD2 regions were P+ doped.

[0174] It can thus be seen that if one of the two transistors is an NMOS transistor and the other is a PMOS transistor, then two complementary transistors with a compact structure are obtained.

[0175] Reference is now made more particularly to FIG. 16 and the following, which diagrammatically show embodiments and implementations of a system SYS for detecting an opening or attempted opening of a closed container.

[0176] In FIG. 16, the system SYS includes a closed container RCP and an integrated circuit having a first terminal TD1 and a second terminal TD0 connected by an electrically conductive wire FL1.

[0177] This wire has a severable part FL10 and is arranged to be severed at the severable part thereof in the case of opening or attempted opening of the container RCP.

[0178] The system SYS further includes a detection device DSD, incorporated, in this case, within the integrated circuit IC, and configured to detect a present or past severing of the severable part FL10 of the wire FL1.

[0179] As shown in FIG. 17, the container RCP can be a case including a body CRP closed by a lid CV that creates a slot FNT with the body CRP.

[0180] It goes without saying that this is only one example and the container RCP can take any shape that is appropriate to the contents of the container. The container can be, for example, a bottle of wine or alcohol closed by a cork.

[0181] In the example shown in FIG. 17, the electrically conductive wire FL1, surrounded by an isolating cover, coils so as to extend alternately over the lid CV and over the body CRP.

[0182] This coil-shaped part FL10 forms the severable part of the electrically conductive wire.

[0183] More specifically, when the lid CV is opened, the wire FL1 will be severed at the severable part FL10.

[0184] It goes without saying that the drawing in FIG. 17 is not to scale and that a person skilled in the art will know how to choose the appropriate diameter for the wire FL1 so as to ensure that it is severed when the lid CV is opened.

[0185] The integrated circuit IC is, for example, attached to a wall of the body CRP.

[0186] Then, once this assembly has been produced, the unit is covered with a cover CH as shown in a very diagrammatic manner in FIG. 18.

[0187] Reference is now made more particularly to FIG. 19, which shows one example embodiment of a detection device DSD.

[0188] The device DSD in this case includes a first capacitor C1, electrically isolated from the first substrate SB1 of the integrated circuit and having a first electrode BC11 connected to the first terminal TDI of the integrated circuit.

[0189] In this example embodiment, the second electrode BC12 of the first capacitor C1 is connected to a supply voltage VCC1 via a first auxiliary capacitor CTUN1 and a first controllable switch SW1.

[0190] The device DSD further includes a first MOS transistor TR whose source and drain regions are electrically isolated from the first substrate SB1 and whose gate region is connected to the second terminal TD0 of the integrated circuit.

[0191] Generally speaking, the first transistor TR is configured to be in an on state when a zero voltage is applied to the gate thereof and in an off state when a non-zero bias is applied to the gate region thereof.

[0192] By way of example, in a non-limiting manner, the first transistor TR can be a PMOS transistor as described with reference to FIG. 1 and FIGS. 3 to 7.

[0193] In such a case, the first PMOS transistor TR has, for example, its source connected to the ground GND and is configured to, as shown in FIG. 21, be off in the presence of a negative bias Vg (for example −2 volts) applied to the gate thereof, and on in the presence of a zero voltage Vg applied to the gate thereof.

[0194] The first transistor TR is thus “normally on”.

[0195] In order to obtain such a configuration, the threshold voltage of this first PMOS transistor TR is negative and for example in the order of −600 to −700 mV.

[0196] The device DSD further includes a second capacitor C2 electrically isolated from the first substrate SB1 of the integrated circuit.

[0197] This second capacitor C2 has a first electrode BC21 connected to the drain of the first transistor TR.

[0198] The second capacitor C2 has a second electrode BC22 connected to a supply voltage VCC2 via a second auxiliary capacitor CTUN2 and a second controllable switch SW2.

[0199] The detection device DSD further includes a measuring circuit MES configured to measure the voltage of the first electrode BC21.

[0200] As will be seen in more detail hereinbelow, a voltage of the first electrode below a threshold TH is representative of a present or past severing of the severable part FL10 of the wire FL1.

[0201] In this respect, in this embodiment, the integrated circuit IC includes a comparison circuit CMP configured to compare the voltage of the first electrode output by the measuring circuit IVIES with the threshold TH and to output a signal SRS representative of the result of the comparison.

[0202] This signal SRS can be a signal having a high state when the measured voltage is below the threshold TH and a low state when the measured voltage is above the threshold TH.

[0203] It goes without saying that the reverse is possible.

[0204] One example embodiment that procures capacitors C1/C2 electrically isolated from the first substrate SB1 is diagrammatically shown in FIG. 20.

[0205] It can be seen in FIG. 20 that the first capacitor C1 and the second capacitor C2 are capacitors including two polysilicon electrodes P10 and P20, separated by a dielectric 8 including, for example, a stack 80 of the silicon oxide-silicon nitride-silicon oxide type.

[0206] These capacitors rest on an isolation trench 100, for example of the shallow trench type, made in the first substrate SB1.

[0207] Before going into detail regarding the operation of the system SYS, it should be noted here that, as stated hereinabove, a PMOS transistor TRP such as that described with reference to FIG. 1 and FIGS. 3 to 7 is not the only possible transistor that can be used.

[0208] More specifically, any transistor whose source and drain regions are electrically isolated from the first substrate and configured to be in an on state in the presence of a zero voltage applied to the gate thereof and in an off state in the presence of a non-zero bias of the gate region thereof, is suitable.

[0209] This can be, for example, the case of a transistor TRP100 such that that shown in FIG. 22.

[0210] This transistor TRP100 is also a double-polysilicon PMOS transistor, the first polysilicon region P100 whereof rests on an isolation trench 15 of the shallow trench type and the second polysilicon region P200 whereof rests on the first polysilicon region P100 via a gate oxide 9.

[0211] However, unlike the transistor TRP in FIG. 1 for example, the gate region of this transistor TRP100 is located in the second polysilicon region and the source and drain regions thereof are located in the first polysilicon region.

[0212] Compared to such a transistor TRP100, a transistor TRP such as that described with reference to FIG. 1 and FIGS. 3 to 7 is more advantageous since it has fewer leakages between the source and drain regions since they are disposed in the second polysilicon region, the substrate region whereof is either made of intrinsic polysilicon or lightly doped.

[0213] In the case whereby the substrate is a silicon-on-insulator (SOI) substrate including a carrier substrate positioned underneath a buried isolating layer known by a person skilled in the art as a BOX (Buried OXide), itself positioned underneath a semiconductor film, an MOS transistor can also be disposed in and on the semiconductor film. This would thus be electrically isolated from the carrier substrate of the integrated circuit via the BOX layer.

[0214] It goes without saying that, while it is generally easier to provide a PMOS transistor as the transistor TR, the use of an NMOS transistor is not ruled out.

[0215] Reference is now made more particularly to FIG. 23 to describe the operation of the system SYS.

[0216] In a step STP 220, the first capacitor C1 is charged.

[0217] This charging is carried out by closing the switch SW1 in order to connect the first auxiliary capacitor CTUN1 to the supply voltage VCC1.

[0218] One role of the first auxiliary capacitor CTUN1 is to allow charges to be injected into the first capacitor C1 by the Fowler-Nordheim effect or by a hot-electron injection phenomenon.

[0219] The thickness of the dielectric layer of the first auxiliary capacitor CTUN1, for example 65-95 angstroms, is advantageously less than that of the first capacitor C1 to allow the capacitive structure to be programmed without using a too high voltage.

[0220] The dielectric layer of the first capacitor C1, which is thick because it uses a silicon oxide-silicon nitride-silicon oxide (ONO) stack, procures a capacitive structure that is well isolated from the first substrate SB1. Such a thickness, for example 150-200 angstroms, procures a very long charge retention, typically in the order of two decades, and prevents the risk of leakage on the first auxiliary capacitor CTUN1.

[0221] The first capacitor C1, once charged, thus has, at the first electrode BC11 thereof, a voltage that is, for example, negative and equal to −2 volts.

[0222] In step STP221, the second capacitor C2 is charged, this time by connecting the second auxiliary capacitor CTUN2 to the supply voltage VCC2 via the closed first switch SW2.

[0223] The function of the second auxiliary capacitor CTUN2 is similar to that of the first capacitor CTUN1.

[0224] Once charged, the voltage VC2 of the first electrode BC21 of the second capacitor C2 is, for example, a positive voltage equal to 2 volts. This voltage VC2 is measured in step STP222 by the measuring circuit MES.

[0225] In this respect, the measuring circuit IVIES can be, for example, an MOS transistor, the gate whereof is connected to the electrode BC21, the source whereof is connected to the ground, and the drain whereof is connected to a current source allowing for a current-to-voltage conversion of the drain current of this transistor.

[0226] The node BC21 is thus not connected to the first substrate SB1, and to prevent gate leakages as much as possible, a high-voltage MOS transistor having, for example, a gate oxide in the order of 200 angstroms, will preferably be used.

[0227] If the severable part FL10 of the wire FL1 is not severed, then the transistor TR is off since the gate voltage thereof is equal to −2 volts.

[0228] As a result, the second capacitor remains charged and if a threshold TH equal to 1 volt for example is chosen, the comparison made in step STP223 shows that this voltage VC2 is higher than the threshold TH, which means that the severable part FL10 is not severed.

[0229] However, if the part FL10 of the wire is severed, then the gate voltage of the transistor TR is zero, which switches this transistor TR on and thus connects the electrode BC21 to the ground GND.

[0230] This results in a discharging of the second capacitor C2 and consequently in a drop in the voltage VC2.

[0231] This then falls below the threshold TH, which is representative of a severing of the severable part FL10.

[0232] It should be noted that a voltage VC2 below the threshold TH is also representative of a past severing of the severable part FL10 followed by a repair, for example by a welding spot, of this severable part.

[0233] More specifically, as soon as the wire has been severed, the gate voltage of the transistor becomes zero and the transistor is switched on, discharging the second capacitor C2 and causing the voltage VC2 to fall below the threshold TH.

[0234] Moreover, even if the wire is repaired, the capacitor C2 remains discharged.

[0235] It is also possible, as shown diagrammatically in FIG. 24, to monitor the state of the severable part of the wire at regular or irregular time intervals.

[0236] More specifically, once the capacitors C1 and C2 have been charged, a first measurement of the voltage VC2 at the time T0 can be taken in step STP230. Then, in step STP231, the voltage VC2 is compared to the threshold.

[0237] If this voltage is below the threshold, this means that the severable part is severed or has previously been severed.

[0238] If the voltage VC2 is above the threshold, this means that the severable part FL10 has never been severed.

[0239] Moreover, steps STP230 and STP231 can then be repeated at distant measuring times Ti (represented by the incrementation of the index i in step STP232).

[0240] Moreover, a measured voltage that is below the threshold TH at a measuring time Ti thus indicates that the severable part of the wire is either severed at this measuring time or was severed prior to this measuring time.

[0241] Use of a passive transponder in combination with a reader is particularly advantageous, as shown in FIG. 25, to detect the present or past severing of the wire FL1.

[0242] In this respect, in FIG. 25, the system SYS further includes a contactless passive transponder TG, for example a tag.

[0243] The passive transponder TG is configured to communicate with a reader RD, for example a cellular mobile phone having a contactless reader function, via an antenna ANT using a carrier signal with a frequency of 13.56 MHz for example.

[0244] The contactless passive transponder TG is, in this case, a transponder capable of communicating according to a contactless communication protocol using, for example, near field communication (NFC) technology.

[0245] This transponder can also be an RFID transponder using this NFC technology. The transponder TG comprises the integrated circuit IC, which can be, for example, an integrated circuit of the family ST25 marketed by STMicroelectronics.

[0246] In addition to the two terminals TD1 and TD0 described hereinabove, the integrated circuit includes two antenna terminals AC0 and AC1 respectively connected to the two terminals of the antenna ANT.

[0247] The circuit IC further includes processing circuit MT, for example including an energy recovery circuit, a microprocessor and/or a wired logic and a memory.

[0248] The processing circuit are configured to output a supply voltage to the entire integrated circuit from the magnetic field received from the reader and to process the information received from the reader and retro-modulate the carrier signal for the transmission of information to the reader.

[0249] More specifically, as shown in FIG. 26, the processing circuit MT are configured to: command (step STP262) a charging of the first capacitor C1 in response to a first command CMD1 originating (step STP260) from the reader; command (step STP263) a charging of the second capacitor C2 in response to a second command CMD2 originating (step STP261) from the reader; activate (step STP265) the measuring circuit in response to an activation command CMDA originating (step STP264) from the reader; and communicate (step STP267) the result SRS of said comparison to the reader RD in response to a read command originating (step STP266) from the reader.