Thin film transistor and method of manufacturing same

Abstract

A thin film transistor (TFT) and a method of manufacturing same are provided. A photoresist layer is dry-etched to form a tunnel before an active layer is formed, wherein a bottom of the tunnel is a copper trace layer. After that, two edges of the photoresist layer are aligned with two edges of the copper trace layer. Therefore, the photoresist layer won't protrude over an amorphous silicon layer to block the etching gas from etching the amorphous silicon layer. As a result, an aperture ratio of the TFT is increased, and quality of the TFT is improved. By forming an oxidation protective layer on the tunnel, the copper trace layer is prevented from being reacted with the etching gas to form a compound. Therefore, metals or compounds on the tunnel can be completely etched, and quality of the TFT is further improved.

Claims

1. A method of manufacturing a thin film transistor (TFT), comprising steps of: step 1: disposing a gate layer, an insulating layer, an amorphous silicon layer, a metal layer, a copper trace layer, and a photoresist layer on a substrate; step 2: etching the copper trace layer and the metal layer outside a first region by wet etching; step 3: etching the photoresist layer to form a tunnel by dry etching, and forming an oxidation protective layer in the tunnel, wherein a bottom of the tunnel is the copper trace layer; step 4: etching the amorphous silicon layer by dry-etching to form an active layer; step 5: etching the copper trace layer and the metal layer in the tunnel by wet-etching to form a source electrode and a drain electrode.

2. The method of claim 1, where material of the metal layer in step 1 is Mo, MoTi, MoTa, MoNb, or MoW.

3. The method of claim 1, wherein an etchant used in step 2 comprises an acid etchant for etching copper.

4. The method of claim 1, wherein an etchant used in step 5 comprises an acid etchant for etching copper.

5. The method of claim 1, wherein a right edge of the photoresist layer is aligned with a right edge of the copper trace layer after the step 3; and wherein a left edge of the photoresist layer is aligned with a left edge of the copper trace layer after the step 3.

6. The method of claim 1, wherein an etching gas used in the step 4 comprises O.sub.2, Cl.sub.2, and one or more of NF.sub.3, SF.sub.6, CHF.sub.3, and CF.sub.4.

7. The method of claim 1, wherein a method of forming the oxidation protective layer comprises: oxidizing a surface of the copper trace layer in the tunnel by plasma oxidation.

8. The method of claim 1, wherein a method of forming the oxidation protective layer comprises: heating the copper trace layer in the tunnel to at least 200 degrees Celsius; and cooling the copper trace layer in the tunnel with compressed air.

Description

DESCRIPTION OF DRAWINGS

(1) The accompanying figures to be used in the description of embodiments of the present disclosure or prior art will be described in brief to more clearly illustrate the technical solutions of the embodiments or the prior art. The accompanying figures described below are only part of the embodiments of the present disclosure, from which figures those skilled in the art can derive further figures without making any inventive efforts.

(2) FIG. 1 is a schematic structural diagram showing a thin film transistor (TFT) during the process of forming an active layer in the prior art.

(3) FIG. 2 is a flowchart showing a method of manufacturing a TFT according to an embodiment of the present invention.

(4) FIG. 3 is a schematic structural diagram showing a TFT after step 1 of the method of manufacturing a TFT according to an embodiment of the present invention.

(5) FIG. 4 is a schematic structural diagram showing a TFT after step 2 of the method of manufacturing a TFT according to an embodiment of the present invention.

(6) FIG. 5 is a schematic structural diagram showing a TFT after step 3 of the method of manufacturing a TFT according to an embodiment of the present invention.

(7) FIG. 6 is a schematic structural diagram showing a TFT after step 4 of the method of manufacturing a TFT according to an embodiment of the present invention.

(8) FIG. 7 is a schematic structural diagram showing a TFT after step 5 of the method of manufacturing a TFT according to an embodiment of the present invention.

(9) FIG. 8 is a schematic structural diagram showing a TFT after step 6 of the method of manufacturing a TFT according to an embodiment of the present invention.

(10) FIG. 9 is a schematic structural diagram showing a TFT according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(11) In order to further explain the technical means and effects of the present invention, the following detailed description will be made in conjunction with the preferred embodiments of the present invention and the accompanying drawings. In the following embodiments, the same portions are denoted by the same reference numerals in the different drawings.

(12) In the prior art, during the process of forming an active layer, an amorphous silicon layer can't be completely etched due to a protruding photoresist layer, thereby causing parasitic capacitances to appear. A thin film transistor and a method of manufacturing same provided by the present invention can solve the above technical problem.

(13) FIG. 2 is a flowchart showing a method of manufacturing a TFT, comprising:

(14) Step 1: referring to FIG. 3, sequentially disposing a gate layer (not shown), an insulating layer (not shown), an amorphous silicon layer 10, a metal layer 11, a copper trace layer 12, and a photoresist layer 13 on a substrate (not shown) sequentially.

(15) Step 2: referring to FIG. 4, etching the metal layer 11 and the copper trace layer 12 outside the first region 100 by a first wet-etching process.

(16) Step 3: referring to FIG. 5, etching the photoresist layer 13 by a first dry-etching process to thin the photoresist layer 13, form a tunnel in the first region 100, make a left edge of the photoresist layer 13 align with a left edge of the copper trace layer 12, and make a right edge of the photoresist layer 13 align with a right edge of the copper trace layer 12, wherein a bottom of the tunnel is the copper trace layer 12.

(17) Step 4: referring to FIG. 6, forming an oxidation protective layer 14 on the tunnel.

(18) Step 5: referring to FIG. 7, etching the amorphous silicon layer 10 outside the first region 100 by a second dry-etching process to form an active layer 15. Since two edges of the photoresist layer 13 are aligned with two edges of the copper trace layer 12, the photoresist layer 13 won't block an etching gas from etching the amorphous silicon layer 10. Therefore, two edges of the active layer 15 will also be aligned with two edges of the metal layer 11, thereby preventing parasitic capacitances from appearing. As a result, an aperture ratio of the TFT is increased, and quality of the TFT is improved.

(19) Step 6: referring to FIG. 8, etching the oxidation protective layer 14, the copper trace layer 12, and the metal layer 11 in the first region 100 by a second wet-etching process to form a source/drain electrode 16. Since the oxidation protective layer 14 blocks the copper trace layer 12 from being reacted with an etching gas of the second dry-etching process, no compound is formed on the copper trace layer 12 in the first region 100. Therefore, the tunnel can be formed without remaining any other metals or metal compounds after the second wet-etching process, thereby improving quality of the TFT.

(20) Specifically, material of the metal layer 11 is Mo.

(21) Specifically, a method of forming the oxidation protective layer 14 of the tunnel includes: oxidizing a surface of the copper trace layer 12 in the tunnel by plasma oxidation.

(22) Specifically, a right edge of the photoresist layer 14 is aligned with a right edge of the copper trace layer 12 after the step 3, and a left edge of the photoresist layer 14 is also aligned with a left edge of the copper trace layer 12 after the step 3.

(23) Specifically, an etchant used in the first wet-etching process includes an acid etchant for etching copper.

(24) Specifically, an etchant used in the second wet-etching process includes an acid etchant for etching copper.

(25) Specifically, an etching gas used in the second dry-etching process includes O.sub.2, Cl.sub.2, and one or more of NF.sub.3, SF.sub.6, CHF.sub.3, and CF.sub.4.

(26) Referring to FIG. 9, the present invention further provides a TFT comprising: a substrate 30, a gate layer 31 disposed on the substrate 30, an insulating layer 32 disposed on the gate layer 31, an active layer 33 disposed on the insulating layer 32, and a source electrode 34 and a drain electrode 35 disposed on the active layer 33, wherein a tunnel 36 is defined between the source electrode 34 and the drain electrode 35.

(27) Specifically, a bottom of the tunnel 36 is the active layer 33 without remaining any other metals or metal compounds.

(28) Specifically, one edge of the active layer 33 is aligned with an outer edge of the source electrode 34, and the other edge of the active layer 33 is aligned with an outer edge of the drain electrode 35.

(29) Regarding the beneficial effect of the present embodiment: a TFT provided by the present embodiment has a tunnel between a source electrode and a drain electrode, wherein a surface of the tunnel is formed without remaining any metals or metal compounds. Quality of the TFT is improved. On the other hand, two edges of an active layer are respectively aligned with an outer edge of the source electrode and an outer edge of the drain electrode. Therefore, the amount of parasitic capacitance formed at the edge of the active layer is reduced, and quality of the TFT is further improved.

(30) The present disclosure has been described with a preferred embodiment thereof. The preferred embodiment is not intended to limit the present disclosure, and it is understood that many changes and modifications to the described embodiment can be carried out without departing from the scope and the spirit of the disclosure that is intended to be limited only by the appended claims.