THIN-FILM TRANSISTOR

Abstract

Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

Claims

1. A device, comprising: a substrate; a first semiconductor channel of a first thin film transistor (TFT), the first semiconductor channel disposed over the substrate, the first semiconductor channel comprising: a first layer having a first electron mobility; and a second layer contacting the first layer, wherein the second layer comprises an electron mobility greater than the first layer wherein the first TFT has an electron mobility of about 35 cm.sup.2/V.Math.s to about 70 cm.sup.2/V s; a first gate disposed over a first gate insulator layer of the first TFT; an inter-layer dielectric (ILD) layer disposed over the first gate electrode; a first source electrode contacting the first semiconductor channel, the first source electrode disposed in a source electrode via of the ILD layer; and a first drain electrode contacting the first semiconductor channel, the first drain electrode disposed in a first drain electrode via of the ILD layer.

2. The device of claim 1, further comprising: a second semiconductor channel of a second TFT disposed over the substrate, the second semiconductor channel having an electron mobility less than the electron mobility of the second layer of the first TFT, wherein the second semiconductor channel is in contact with a second gate insulator layer of the second TFT, the second gate insulator layer disposed over the second semiconductor channel; a second gate electrode disposed over the second gate insulator layer; a second source electrode contacting the second semiconductor channel, the second source electrode disposed in a second source electrode via of the ILD layer; and a second drain electrode contacting the second semiconductor channel, the second drain electrode disposed in a second drain electrode via of the ILD layer, wherein the second TFT has a threshold voltage of about −1.5 V to about 2.5 V.

3. The device of claim 2, wherein the second TFT further comprises: a second bottom gate electrode disposed over the substrate; and a bottom insulator layer disposed over the second bottom gate electrode.

4. The device of claim 3, wherein the first TFT further comprises: a first bottom gate electrode disposed over the substrate wherein the bottom insulator layer is disposed over the first bottom gate electrode.

5. The device of claim 1, wherein the first TFT further comprises: a first bottom gate electrode disposed over the substrate, wherein the bottom insulator is disposed over the first bottom gate electrode.

6. The device of claim 1, wherein the first semiconductor channel further comprises one or more additional layers.

7. The device of claim 1, wherein each layer of the semiconductor channel has a thickness from about 0.5 nm to about 50 nm.

8. A device, comprising: a substrate; a first semiconductor channel of a first thin film transistor (TFT) disposed over the substrate, the first semiconductor channel comprising: a first layer having a first electron mobility; and a second layer contacting the first layer, wherein the second electron mobility is greater than the first electron mobility, wherein the first TFT has an electron mobility of about 35 cm.sup.2/V.Math.s to about 70 cm.sup.2/V s; a first bottom gate electrode disposed over the substrate; a bottom insulator layer disposed over the first bottom gate electrode; an inter-layer dielectric (ILD) layer disposed over the first semiconductor channel; a first source electrode contacting the first semiconductor channel; and a first drain electrode contacting the first semiconductor channel.

9. The device of claim 26, further comprising: a second semiconductor channel of a second TFT disposed over the substrate, the second semiconductor channel having an electron mobility less than the electron mobility of the second layer of the first TFT, wherein the second semiconductor channel is in contact with a second gate insulator layer of the second TFT, the second gate insulator layer disposed over the second semiconductor channel; a second gate electrode disposed over the second gate insulator layer; a second source electrode contacting the second semiconductor channel, the second source electrode disposed in a second source electrode via of the ILD layer; and a second drain electrode contacting the second semiconductor channel, the second drain electrode disposed in a second drain electrode via of the ILD layer.

10. The device of claim 9, further comprising: a second bottom gate electrode disposed over the substrate, wherein the bottom insulator layer is disposed over the second bottom gate electrode.

11. The device of claim 8, wherein the first semiconductor channel further comprises one or more additional layers, such that an odd total number of layers are in the first semiconductor channel.

12. The device of claim 8, wherein each of the layers is a metal oxide containing layer.

13. The device of claim 12, wherein each of the layers comprises In—Zn—O, In—Sn—O, In—Zn—Sn—O, In—Ga—O, In—Ga—Zn—O, In—Ga—Sn—O, In—Ga—Zn—Sn—O, or any combination thereof.

14. The device of claim 13, wherein the second layer has a lower atomic percentage of gallium (Ga) than the first layer.

15. A device, comprising a substrate; an inter-layer dielectric (ILD) layer disposed over the substrate; a first thin film transistor (TFT), comprising: a multi-layer semiconductor channel disposed over the substrate, the multi-layer semiconductor channel comprising: a first layer having a first electron mobility; and a second layer contacting the first layer, the second layer having a second electron mobility greater than about 20 cm.sup.2/V.Math.s; a first set of one or more gate electrodes disposed over the substrate, wherein each of the first set of gate electrodes is disposed above or below the multi-layer semiconductor channel; a first insulator layer disposed over or below at least one of the first set of gate electrodes; a first source electrode electrically contacting the multi-layer semiconductor channel; and a first drain electrode electrically contacting the multi-layer semiconductor channel; and a second TFT, comprising: a second semiconductor channel disposed over the substrate; a second set of one or more gate electrodes disposed over the substrate, wherein each of the second set of gate electrodes is disposed above or below the second semiconductor channel; a second insulator layer disposed over or below at least one of the second set of gate electrodes; a second source electrode electrically contacting the second semiconductor channel; and a second drain electrode electrically contacting the second semiconductor channel.

16. The device of claim 15, wherein the first TFT further comprises: a first gate insulator layer disposed over the multi-layer semiconductor channel; and a first gate electrode of the first set of gate electrodes disposed over the first gate insulator layer, wherein the first layer of the uppermost stack of the one or more stacks is in contact with the first gate insulator layer of the first TFT.

17. The device of claim 16, wherein the second TFT further comprises: a second gate insulator layer disposed over the second semiconductor channel; and a second gate electrode of the second set of gate electrodes disposed over the second gate insulator layer.

18. The device of claim 16, further comprising a first bottom gate electrode of the first set of gate electrodes disposed below the multi-layer semiconductor channel, wherein the first insulator layer is disposed above the first bottom gate electrode, wherein a bottom gate length of the first bottom gate electrode is larger than a gate length of the first gate electrode.

19. The device of claim 15, the first TFT further comprising a first top gate electrode of the first set of gate electrodes disposed over the ILD layer.

20. The device of claim 19, the second TFT further comprising a second top gate electrode of the second set of pate electrodes disposed over the ILD layer.

21. The device of claim 1, wherein the first electron mobility is less than about 20 cm.sup.2/V s and the second electron mobility is greater than about 20 cm.sup.2/V s, wherein the first layer is in contact with a first gate insulator layer of the first TFT, the first gate insulator layer disposed over the first semiconductor channel.

22. The device of claim 21, wherein the first semiconductor channel further comprises a third layer, wherein the third layer is disposed below the first and second layers, the third layer comprising a third electron mobility less than the electron mobility of the second electron mobility.

23. The device of claim 2, wherein the second TFT has an electron mobility of about 35 cm.sup.2/V.Math.s to about 70 cm.sup.2/V s, wherein the first TFT has a threshold voltage of about −1.5 V to about 2.5 V.

24. The device of claim 1, wherein the second layer is free of Sn.

25. The device of claim 1, wherein at least one layer of the semiconductor channel is free of Zn.

26. The device of claim 8, further comprising a first gate electrode disposed over a first gate insulator layer of the first TFT.

27. The device of claim 9, wherein the second semiconductor channel consists of a single layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0011] FIGS. 1A-1D illustrate schematic side views of thin-film transistors, according to some embodiments.

[0012] FIGS. 2A-2D illustrate schematic side views of thin-film transistors, according to some embodiments.

[0013] FIGS. 3A-3G illustrate schematic side views of devices, according to some embodiments.

[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

[0015] Embodiments herein include thin-film transistors (TFTs) that include channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers and/or the high mobility channel layers due to higher carrier density in high mobility channel layer, which increases the response of speed of the TFTs due to higher on current in the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFTs. The high mobility layer increases the speed of response of the TFTs. A low mobility layer allows more positive threshold voltage (turn on voltage) and lower leakage current than a high mobility layer in the same TFTs. The combination of the low mobility layer and the high mobility layer results in TFTs with improved qualities such as improved mobility, lower off leakage current, and positive threshold voltage (turn on voltage), as described herein. In addition, the channel layer stack has an effective mobility due to the combination of the layers therein. Embodiments disclosed herein can be useful for, but are not limited to, TFTs including channel layer stacks with layers having differing mobilities.

[0016] As used herein, the term “about” refers to a +/−10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

[0017] FIGS. 1A-1D and 2A-2D illustrate schematic, cross-sectional views of TFTs, according to some embodiments. Any of the TFTs described herein are configured to operate as a traditional transistor in any conventional circuit. Any of the TFTs described herein can be included in a device.

[0018] FIG. 1A illustrates a schematic, cross-sectional view of a TFT 100A, according to one embodiment. The TFT 100A can be considered a top-gate (TG) TFT. As shown, the TFT 100A includes a substrate 101, a gate structure 121A, a channel layer stack (alternatively referred to as a semiconductor channel) 104A, and an inter-layer dielectric (ILD) layer 110, a source electrode 112, and a drain electrode 114.

[0019] The substrate 101 can include any suitable material, such as silicon based substrates, semiconductor based substrates, insulating based substrates, germanium based substrates, and, in general, one or more generic layers that would be present in a complementary metal-oxide-semiconductor (CMOS) device structure. The substrate 101 can include a transparent material, such as rigid glass or flexible polyimides (PI), which can be useful if the TFT is used in LCD or OLED display applications, such as TVs, tablets, laptops, mobile phones or other displays.

[0020] In some embodiments, a buffer layer 102 is disposed over the substrate 101 and the channel layer stack 104A is disposed over the buffer layer 102. The ILD layer 110 is disposed over at least the channel layer stack 104A, the buffer layer 102, and the gate structure 121A. The source electrode 112 is disposed in a source electrode via 116 of the ILD layer 110. The drain electrode 114 is disposed in a drain electrode via 118 of the ILD layer 110.

[0021] The gate structure 121A is disposed over the channel layer stack 104A. The gate structure 121A is configured to modulate the voltage in the channel layer stack 104A. As shown, the gate structure 121A includes an insulator layer (alternatively referred to as a gate insulator layer) 106 and a gate electrode 108. The insulator layer 106 can include silicon dioxide. The gate electrode 108 is configured to be connected to a gate line signal as a power source (not shown) to provide a voltage across the channel layer stack 104A. The gate electrode 108 is disposed over the insulator layer 106. The gate electrode 108 includes a conducting material.

[0022] The buffer layer 102 can include insulating materials such as single silicon dioxide (SiO.sub.x), silicon nitride (SiN.sub.x), multi-layer silicon nitride/silicon oxide (SiN.sub.x/SiO.sub.y), silicon oxynitride (SiON), other insulating materials, or combinations thereof. The ILD layer 110 can include insulating materials such as SiO.sub.x, SiN.sub.x, other insulating materials, or combinations thereof, including SiO.sub.y/SiN.sub.x. The insulating layer 106 can include insulating materials such as silicon, SiN.sub.x, other insulating materials, or combinations thereof. The gate electrode 108, the source electrode 112, and the drain electrode 114 each include conductive materials such as molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, any electrically conductive materials, such as including conductive metal oxides, such as indium tin oxide (InSnO) [ITO] and indium zinc oxide (InZnO) [IZO], or any combination thereof.

[0023] The channel layer stack 104A is disposed over the substrate 101. The channel layer stack 104A includes one or more layers 105. In embodiments where the channel layer stack 104A includes a plurality of layers 105, the channel layer stack 104A can be referred to as a multi-layer channel layer stack (alternatively referred to as a multi-layer semiconductor channel). In embodiments where the channel layer stack 104A includes one layer 105, the channel layer stack 104A can be referred to as a single layer channel layer stack (alternatively referred to as a single layer semiconductor channel).

[0024] The layers 105 include any material that allows for conducting electrons and/or holes, as is given in more detail below. The one or more layers 105 can include two layers having alternating mobilities, such as a first layer 105A disposed over the buffer layer 102, and a second layer 105B disposed under the first layer. The first layer 105A has a mobility greater than the mobility of the second layer 105B, according to one embodiment. The first layer 105A has a mobility less than the mobility of the second layer 105B, according to one embodiment. The combination of the plurality of layers 105 results in the channel layer stack 104A having an effective mobility of from about 1 cm.sup.2/V s to about 70 cm.sup.2/V s, such as about 25 cm.sup.2/V s to about 45 cm.sup.2/V s, such as about 25 cm.sup.2/V s to about 35 cm.sup.2/V s, or from about 35 cm.sup.2/V s to about 45 cm.sup.2/V s.

[0025] In embodiments where the first layer 105A has a mobility greater than the mobility of the second layer 1056, the first layer 105A conducts a large portion of the current through the channel layer stack 104A, which allows the channel layer stack to effectively conduct current due to the high mobility of the first layer 105A. In these embodiments, TFTs can have higher off-leakage currents and negative threshold voltage due to higher carrier density at the interface between the insulating layer 106 and the high mobility channel (e.g., second layer 105B). Low off-leakage current and positive threshold voltage can be obtained by suppressing carrier density near the insulating layer 106, which can reduce mobility of the channel layer stack 104A. Therefore, there is a trade off between mobility and threshold voltage/off-leakage current. The combination of the plurality of layers 105 results in the channel layer stack 104A having an effective mobility greater than about 20 cm.sup.2/V.Math.s. In one example, the TFT 100A with the ratio of width and length (W/L=40 um/10 um) of about 4 has a threshold voltage of about −1.0 V to about 1.0 V, a drain-source current of about 1E-12 A to about 8E-5 A at a gate-to-source voltage (V.sub.GS) from about −20V to about 20V, a drain-to-source voltage (V.sub.DS) of about 1 V, and a channel layer stack 104A mobility of about 25 cm.sup.2/V s to about 35 cm.sup.2/V s.

[0026] In embodiments where the first layer 105A has a mobility less than the mobility of the second layer 105B, the second layer 105B conducts a large portion of the current through the channel layer stack 104A, which allows the channel layer stack to effectively conduct current due to the high mobility of the second layer 105B. In addition, the lower mobility of the first layer 105A allows a reduced leakage current and more positive threshold voltage (turn on voltage) with respect to a TFT with a high mobility layer only. Therefore, higher effective mobility can be easily obtained with low off-leakage current and positive threshold voltage. The combination of the plurality of layers 105 results in the channel layer stack 104A having an effective mobility greater than 20 cm.sup.2/V.Math.s. The first layer 105A has a mobility less than about 20 cm.sup.2/V.Math.s, and the second layer 105B has a mobility greater than about 20 cm.sup.2/V.Math.s, according to one embodiment. In one example, the TFT 100A with the ratio of width (W) and length (L) (W/L=40 um/10 um) about 4 has a threshold voltage of about −0.5 V to about 2.5 V, a drain-source current of about 1E-13 A to about 1E-4 A at a gate-to-source voltage (V.sub.GS) of about −20 V to about 20 V, a drain-to-source voltage (V.sub.DS) of about 1V, and a mobility of about 35 cm.sup.2/V s to about 70 cm.sup.2/V s.

[0027] In general, any of the TFTs disclosed herein have electron mobilities of about 35 cm.sup.2/V.Math.s to about 70 cm.sup.2/V s, threshold voltages of about −0.5 V to about 2.5 V, and drain-source currents of about 1E-13 A to about 1E-4 A at a gate-to-source voltage (V.sub.GS) of about −20 V to about 20 V.

[0028] FIG. 1B illustrates a schematic cross-sectional view of a TFT 100B, according to one embodiment. The TFT 100B is similar to the TFT 100A (FIG. 1A), except that the TFT 100B includes a channel layer stack 104B rather than the channel layer stack 104A. The TFT 100B can be considered a TG TFT.

[0029] As shown, the channel layer stack 104B includes the plurality of layers 105, including the first layer 105A, the second layer 105B, and a third layer 105C. The third layer 105C is disposed over the buffer layer 102 and under the second layer 105B. The first layer 105A is directly in contact with the second layer 105B, as shown in FIG. 1B. In other embodiments, there are one or more additional layers disposed between the first layer 105A and the second layer 105B.

[0030] The plurality of layers 105 comprises an odd number of layers, according to some embodiments, such as three layers 105A, 105B, 105C shown in FIG. 1B. The first layer 105A has a lower mobility than the second layer 105B, the third layer 105C has a lower mobility than the second layer 105B, the second layer 105B is disposed closer to the buffer layer 102 than the first layer 105A, and the third layer 105C is disposed closer to the buffer layer 102 than the second layer 105B, according to one embodiment. The first layer 105A can have a same, greater, or lesser mobility than the third layer 105C. Each of the layers 105A, 105B, 105C includes indium (In), according to one embodiment. The first layer 105A and the third layer 105C have a mobility less than about 20 cm.sup.2/V.Math.s, and the second layer 105B has a mobility greater than about 20 cm.sup.2/V.Math.s, according to one embodiment.

[0031] Electrons are restricted to the second layer 105B, due to band bending between the second layer 105B and the first layer 105A, and band bending between the second layer 105B and the third layer 105C. The band bending is caused by the difference in band gaps and/or valence band maximums (VBM) between the first layer 105A and the second layer 105B, and/or between the second layer 105B and the third layer 105C. The increased number of electrons contained in the second layer 105B increases the free charge density in the second layer, increasing the current from the source electrode 112 to the drain electrode 114.

[0032] It is to be understood that although the TFTs 100A, 100B described herein include two layers 105A, 105B and three layers 105A, 105B, 105C, respectively, any number of layers can be included in the channel layer stacks 104A, 104B. For example, the channel layer stacks 104A, 104B include four, five, six, or even more layers 105 in certain embodiments. The layers 105 alternate such that each layer has a different mobility than adjacent layers. For example, the layers 105 alternate relatively high mobility and relatively low mobility, as described in further detail below.

[0033] The plurality of layers 105 include two high mobility layers and three low mobility layers, the high mobility layers disposed between adjacent low mobility layers, according to one embodiment. Electrons are restricted to the high mobility layers, due to band bending between the low mobility layers and the high mobility layers. The increased number of electrons contained in the high mobility layers increases the free charge density in the high mobility layers, increasing the current from the source electrode 112 to the drain electrode 114. In addition, using multiple high mobility layers further increases the current from the source electrode 112 to the drain electrode 114.

[0034] FIG. 10 illustrates a schematic side view of a TFT 100C, according to one embodiment. The TFT 100C is similar to the TFT 100A (FIG. 1A), except that the TFT 100C includes a gate structure 121B rather than the gate structure 121A. The TFT 100C can be considered a double-gate (DG) TFT.

[0035] The gate structure 121B is disposed over and under the channel layer stack 104A, as described in detail below. The gate structure 121B is configured to modulate the voltage in the channel layer stack 104A. As shown, the gate structure includes an insulator layer 106, a gate electrode 108, a bottom insulator layer 130, and a bottom gate electrode 131. Both the gate electrode 108 and the bottom gate electrode 131 are configured to be connected to one or more gate signal lines as power sources (not shown) to provide a voltage in the channel layer stack 104A. The same gate signal line or two different gate signal lines can be connected to the bottom gate electrode 131 and the gate electrode 108. The gate electrode 108 is disposed over the insulator layer 106. The bottom insulator layer 130 and the bottom gate electrode 131 are disposed over the buffer layer 102. The bottom insulator layer 130 can include silicon dioxide. The bottom gate electrode 131 includes a conducting material. The gate structure 121B, including both the gate electrode 108 and the bottom gate electrode 131, allows higher carrier densities in the channel layer stack 104A, increasing the mobility and current flowing therein.

[0036] As shown in FIG. 10, the bottom gate electrode length L.sub.131 is about the same as the gate electrode length L.sub.106. In this embodiment, the bottom gate electrode length L.sub.131 increases operation speed, and reduces parasitic capacitance, of the TFT 100C.

[0037] FIG. 1D illustrates a schematic side view of a TFT 100D, according to one embodiment. The TFT 100D is similar to the TFT 100C (FIG. 1C), except that the bottom gate electrode length L.sub.131 is about the same as the channel layer stack length L.sub.104. Thus, the bottom gate electrode length L.sub.131 is larger than the gate electrode length L.sub.106. The increased bottom gate electrode can decrease the operation speed of the TFT 100D due to increased parasitic capacitance compared to the TFT 100C shown in FIG. 1C. However, the increased bottom gate electrode length L.sub.131 can block undesired illumination of light on the channel layer stack 104A.

[0038] FIG. 2A illustrates a schematic side view of a TFT 200A, according to one embodiment. The TFT 200A is similar to the TFT 100C of FIG. 1C, except that the TFT 200A includes a different gate structure 221A. The gate structure 221A includes the bottom gate electrode 131. The bottom gate electrode 131 is configured to be connected to a gate signal as a power source (not shown) to provide a voltage in the channel layer stack 104A. As shown in FIG. 2A, a source electrode 212 and a drain electrode 214 are disposed directly over the channel layer stack 104A without use of a source electrode via or a drain electrode via. The TFT 200A can be considered a bottom-gate (BG) TFT.

[0039] FIG. 2B illustrates a schematic side view of a TFT 200B, according to one embodiment. The TFT 200B is similar to the TFT 200A of FIG. 2A, except that the TFT 200B includes a different gate structure 221B. The gate structure 221B further includes a top gate electrode 240. The bottom gate electrode 131 and the top gate electrode 240 are configured to be connected to one or more gate signal lines as power sources (not shown) to provide a voltage in the channel layer stack 104A. The same gate signal line or two difference gate signal lines can be connected to the bottom gate electrode 131 and the top gate electrode 240. The top gate electrode 240 includes a conducting material. The TFT 200B can be considered a DG TFT.

[0040] FIG. 2C illustrates a schematic side view of a TFT 200C, according to one embodiment. The TFT 200C is similar to the TFT 200A of FIG. 2A, except that the TFT 200A includes a different gate structure 221C. The gate structure 221C includes the bottom gate electrode 131. As shown in FIG. 2C, the source electrode 112 and the drain electrode 114 are connected to the channel layer stack 104A by the source electrode via 116 and the drain electrode via 118. The TFT 200C can be considered a BG TFT. The bottom gate electrode 131 is configured to be connected to a gate signal line as a power source (not shown) to provide a voltage in the channel layer stack 104A.

[0041] FIG. 2D illustrates a schematic side view of a TFT 200D, according to one embodiment. The TFT 200D is similar to the TFT 200C of FIG. 2A, except that the TFT 200D includes a different gate structure 221D. The gate structure 221D further includes the bottom gate electrode 131 and the top gate electrode 240. As shown in FIG. 2D, the source electrode 112 and the drain electrode 114 are connected to the channel layer stack 104A by the source electrode via 116 and the drain electrode via 118. The TFT 200D can be considered a DG TFT. The bottom gate electrode 131 and the top gate electrode 240 are configured to be connected to one or more gate signal lines as power sources (not shown) to provide a voltage in the channel layer stack 104A. The same gate signal line or two difference gate signal lines can be connected to the bottom gate electrode 131 and the top gate electrode 240.

[0042] FIG. 3A illustrates a schematic side view of a device 300A, according to one embodiment. As shown, the device 300A includes a first TFT 301A and a second TFT 301B. As shown, the first TFT 301A includes a gate structure 321A. The first TFT 301A is similar to the TFT 100A of FIG. 1A. The channel layer stack 304B is similar to the channel layer stack 104A. As shown, the second TFT 301B includes a gate structure 321B. The second TFT 301B is similar to the TFT 100A of FIG. 1A, but the second TFT 301B includes a channel layer stack 304B. The channel layer stack 304B, as shown, includes the first layer 105A. The layer 105A from the channel layer stack 304B in the second TFT 301 B can be the same layer or can be a different layer compared to the first layer 105A from the channel layer stack 104A in the first TFT 301A.

[0043] FIG. 3B illustrates a schematic side view of a device 300B, according to one embodiment. As shown, the device 300B includes a first TFT 301C and a second TFT 301D. As shown, the first TFT 301C includes a gate structure 321C. The first TFT 301C is similar to the TFT 301A of FIG. 3A. However, as shown, the second TFT 301D includes a gate structure 321D. The gate structures 321C, 321D further include bottom gate electrodes 131A, 131B respectively.

[0044] FIG. 3C illustrates a schematic side view of a device 300C, according to one embodiment. As shown, the device 300C includes a first TFT 301E and a second TFT 301F. As shown, the first TFT 301E includes a gate structure 321E. The first TFT 301E is similar to the TFT 301A of FIG. 3A. As shown, the second TFT 301F includes a gate structure 321F. The gate structures 321E, 321F further include secondary insulating layers 306 disposed between insulating layer 106 and the gate electrode 108. The secondary insulating layer 306 can include any material disclosed above in the insulating layer 106.

[0045] FIG. 3D illustrates a schematic side view of a device 300D, according to one embodiment. As shown, the device 300D includes a first TFT 301G and a second TFT 301H. As shown, the first TFT 301G includes a gate structure 321G. The first TFT 301G is similar to the TFT 301A of FIG. 3A, except that the first TFT 301G includes a channel layer stack 104C. As shown, the channel layer stack 104C further includes the insulating layer 106 disposed under the second layer 105B. As shown, the second TFT 301H includes a gate structure 321H. The gate structure 321H further include the secondary insulating layer 306 disposed between the insulating layer 106 and the gate electrode 108.

[0046] FIG. 3E illustrates a schematic side view of a device 300E, according to one embodiment. As shown, the device 300E includes a first TFT 301I and a second TFT 301J. As shown, the first TFT 301I includes a gate structure 221A. The first TFT 301I is similar to the TFT 200A of FIG. 2A. As shown, the second TFT 301J includes a gate structure 221A. The second TFT 301J is similar to the TFT 200A of FIG. 2A, with the exception that the TFT 301J includes the channel layer stack 304B (that is, the channel layer stack 304B includes the first layer 105A). The first layer 105A of the channel layer stack 304B is a low mobility layer (described below). The source electrodes 212A, 212B and the drain electrode 214A, 214B are in electrical contact with the channel layer stacks 304A, 304B, respectively.

[0047] In some embodiments, one or both of the TFTs 301I, 301J further include a top gate electrode (e.g., top gate electrode 240A and/or top gate electrode 240B) disposed over the ILD layer 110.

[0048] FIG. 3F illustrates a schematic side view of a device 300F, according to one embodiment. As shown, the device 300F includes a first TFT 301K and a second TFT 301L. As shown, the first TFT 301K includes the gate structure 321C. The first TFT 301K is similar to the TFT 301C of FIG. 3B. As shown, the second TFT 301L includes the gate structure 321A. The second TFT 301L is similar to the second TFT 301B of FIG. 3A. In some embodiments, the first TFT 301K includes the gate structure 321A instead of the gate structure 321C, and the second TFT includes the gate structure 321C instead of the gate structure 321A.

[0049] In some embodiments, the first layer 105A from the channel layer stack 304A in the first TFT 301K is different than the first layer 105A from the channel layer stack 304B in the second TFT 301L. In some embodiments, the first layer 105A in the first TFT 301K is a high mobility layer (described below), and the first layer 105A in the second TFT 301L is a low mobility layer (described below). In some embodiments, the first layer 105A in the first TFT 301K is a low mobility layer, and the first layer 105A in the second TFT 301L is a high mobility layer.

[0050] FIG. 3G illustrates a schematic side view of a device 300G, according to one embodiment. As shown, the device 300G includes a first TFT 301M and a second TFT 301N. As shown, the first TFT 301M includes a gate structure 221A. The first TFT 301M is similar to the TFT 200A of FIG. 2A. As shown, the second TFT 301N includes a gate structure 221A.

[0051] In some embodiments, the first layer 105A from the channel layer stack 304A in the first TFT 301M is different than the first layer 105A from the channel layer stack 304B in the second TFT 301N. In some embodiments, the first layer 105A in the first TFT 301M is a high mobility layer (described below), and the first layer 105A in the second TFT 301N is a low mobility layer (described below). In some embodiments, the first layer 105A in the first TFT 301M is a low mobility layer, and the first layer 105A in the second TFT 301N is a high mobility layer. In some embodiments, one or both of the TFTs 301M, 301N include a top gate electrode (not shown) disposed over the ILD layer 110.

[0052] Although the TFTs disclosed herein are illustrated as including a specific channel layer stack (e.g., channel layer stack 104A) and/or (e.g., gate structure 121A), it is to be understood that the TFTs can instead include any of the channel layer stacks disclosed herein and/or any of the gate structures disclosed herein. Said another way, the channel layer stack of the TFTs can include one, two, three, four, five, six, or even more individual layers 105. The layers 105 alternate such that each layer has a different mobility than adjacent layers. For example, the layers 105 alternate relatively high mobility and relatively low mobility, as described in further detail below. In addition, any channel layer stack can further include the first insulator layer 106 and/or the secondary insulating layer 306. In addition, any gate structure described herein can be included in any of the disclosed TFTs, and thus each TFT can be a TG, BG, or DG TFT.

[0053] In any of the embodiments described above, the TFTs share the substrate 101. In some embodiments, the two-gate structure further includes the buffer layer 102, and the two TFTs share the buffer layer. It is to be understood that any of the two-gate structures disclosed herein can include the buffer layer 102. The two TFTs in each two-gate structure are used as a LCD or OLED display pixel circuits, or in gate driver in panel (GIP) circuits. For example, each of the TFTs in the two-gate structure can be used as switching or driving TFTs in OLED pixel circuits.

[0054] In one embodiment, which can be combined with other embodiments described herein, each of the layers 105 (e.g., layers 105A, 105B, and/or 105C) have a thickness of about 0.5 nm to about 50 nm. In another embodiment, which can be combined with other embodiments described herein, the mobility of each of the layers 105 is either greater than about 20 cm.sup.2/V.Math.s or less than about 20 cm.sup.2/V.Math.s. For example, the channel layer stack 104B includes alternating layers 105, wherein each layer alternately has a mobility of greater than about 20 cm.sup.2/V.Math.s (referred to herein as a high mobility layer) and less than about 20 cm.sup.2/V.Math.s (referred to herein as a low mobility layer). It is understood that the mobility of 20 cm.sup.2/V.Math.s is an example, and any high mobility layer having a mobility relatively higher than the corresponding low mobility layer is covered by the disclosure herein.

[0055] In one embodiment, which can be combined with other embodiments described herein, the high mobility layers and the low mobility layers have material compositions that are substantially the same. In another embodiment, which can be combined with other embodiments described herein, the high mobility layers and the low mobility layers have different material compositions.

[0056] In one embodiment, which can be combined with other embodiments described herein, the high mobility layer and/or the low mobility layer include indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and/or hafnium (Hf). Examples of the high mobility layer include, but are not limited to, In—Ga—Zn—O, In—Ga—O, In—Zn—O, In—Ga—Sn—O, In—Zn—Sn—O In—Ga—Zn—Sn—O, In—Sn—O, Hf—In—Zn—O, Ga—Zn—O, In—O, Al—Sn—Zn—O, Zn—O, Zn—Sn—O, Al—Zn—O, Al—Zn—Sn—O, Hf—Zn—O, Sn—O, and Al—Sn—Zn—ln—O. Examples of the low mobility layer include, but are not limited to, In—Ga—Zn—O, Ga—O, In—Ga—O, Zn—Sn—O, In—Sn—O, Hf—In—Zn—O, Al—Sn—Zn—O, Zn—O, Al—In—Zn—Sn—O, and Al—Sn—Zn—O.

[0057] In some embodiments, the material of the high mobility layer and the low mobility layer includes the same elements, but the stoichiometry of the material differs. For example, In—Ga—Zn—O is a multi-component amorphous oxide semiconductor (AOS) system and is commercially used for mass production of LCD and OLED display products. In—Ga—Zn—O typically shows mobility values of about 10 cm.sup.2/V.Math.s with 1:1:1 ratios of In—O, Ga—O, and Zn—O, but it is also possible to achieve mobility larger than 10 cm.sup.2/V.Math.s by increasing In and/or reducing Ga compositions from In—Ga—Zn—O AOS systems. Therefore, mobility is adjustable by changing the compositions of components in AOS systems. Zn—O or In—O without Ga in AOS systems allow higher mobility (higher carrier concentration), but it can be difficult to obtain an amorphous phase. However, binary components such as Zn—ln—O or Zn—Ga—O can form amorphous phases due to changing composition of Zn—O and In—O. For high mobility (>20 cm.sup.2/V.Math.s) AOS, it is possible to increase carrier concentration by increasing the composition of In and/or decreasing the composition of Ga from multi-component AOS systems. Thus, in one embodiment, the low mobility layer includes In—Ga—Zn—O, the high mobility layer includes In—Ga—Zn—O, and the high mobility layer has a higher composition of In than the low mobility layer. In another embodiment, the low mobility layer includes In—Ga—Zn—O, the high mobility layer includes In—Ga—Zn—O, and the high mobility layer has a lower composition of Ga than the low mobility layer. In yet another embodiment, the low mobility layer includes In—Ga—Zn—O, the high mobility layer includes In—Ga—Zn—O, the high mobility layer has a higher composition of In than the low mobility layer, and the high mobility layer has a lower composition of Ga than the low mobility layer.

[0058] It is to be understood that the composition of In, Ga, Zn, and O can easily change electron transport properties (e.g., mobilities). For example, electron transport properties (e.g., mobilities) of In.sub.2O.sub.3—Ga.sub.2O.sub.3—ZnO (In—Ga—Zn—O) thin films are determined by the composition of In.sub.2O.sub.3, Ga.sub.2O.sub.3, and ZnO by changing X, Y, and Z, where X is defined by [(ZnO).sub.X—(Ga.sub.2O.sub.3).sub.1-X] mol %, Y is defined by [(Ga.sub.2O.sub.3).sub.Y—(In.sub.2O.sub.3).sub.1-Y] mol %, and Z is defined by (In.sub.2O.sub.3).sub.Z—(ZnO).sub.1-Z] mol %. In the In—Ga—Zn—O system, it is generally understood that the In atoms contained therein act as In.sup.3+ ions that form electron pathways, which leads to high electron mobility. In addition, it is understood that Zn atoms contained therein act as Zn.sup.2+ ions that prefer tetrahedral coordination, which increases stability of an amorphous phase of In—Ga—Zn—O. Finally, it is understood that Ga atoms contained therein act as Ga.sup.3+ ions that suppress carrier generation due to the high ionic field strength of the Ga.sup.3+ ions. Ga.sup.3+ ions form stronger chemical bonds with O atoms than the Zn and In atoms, due to O vacancy formation. Thus, increasing the Ga percentage leads to low mobility and/or carrier concentration, and thus a layer containing high Ga percentage leads to a low off current and large on/off current ratio.

[0059] If X=Y=Z=0.5, In—Ga—Zn—O allows a mobility of about 9 cm.sup.2/V.Math.s. Higher mobility can be controlled by decreasing Ga and increasing In. For example, if X=1, Y=0, Z=1, the composition is In—O. If X=1, Y=0, Z=0, the composition is Zn—O. However, In—O and Zn—O form a crystalline phase. If X=1, Y=0, 0<Z<1, the composition is In—Zn—O. Therefore, In—Zn—O has an amorphous phase and mobility larger than about 20 cm.sup.2/V.Math.s, which can be the material of the high mobility channel layer. In—Ga—Zn—O has an amorphous phase and lower mobility less than about 20 cm.sup.2/V.Math.s, which can be the material of the low mobility channel layer.

[0060] The AOS systems can include In—Ga—Zn—O, or other AOS including In—Zn—O, Zn—Sn—O, In—Ga—O, In—Zn—O, In—Ga—Sn—O, In—Zn—Sn—O In—Ga—Zn—Sn—O, In—Sn—O, Hf—In—Zn—O, Ga—Zn—O, In—O, Al—Sn—Zn—O, Zn—O, Zn—Sn—O, Al—Zn—O, Al—Zn—Sn—O, Hf—Zn—O, Sn—O, Al—Sn—Zn—ln—O, and the like.

[0061] As described above, a TFT is provided. The TFT includes a gate structure and a channel layer stack. The gate stack includes one or more gate structures, and thus the TFT is a TG, DG, or BG TFT. The channel layer stack includes a plurality of layers with differing mobilities.

[0062] The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT. The low mobility layer reduces leakage current and allows positive threshold voltage (turn on voltage) in the TFT. The combination of the low mobility layer and the high mobility layer results in a TFT with improved qualities such as improved mobility, lower off leakage current, and positive threshold voltage (turn on voltage), as described herein.

[0063] While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.