Display panel

Abstract

A display panel includes a substrate, at least one first transistor, and at least one second transistor. The substrate includes at least one reflective region and at least one transmissible region. The first transistor is configured on the substrate and located on the corresponding reflective region. Each of the first transistors includes a first active layer. The second transistor is configured on the substrate and located on the corresponding transmissible region. Each of the second transistors includes a second active layer. A material of the first active layer is different from a material of the second active layer.

Claims

1. A display panel, comprising: a substrate, comprising a reflective region and a transmissible region; a first transistor, disposed on the reflective region, and comprising a first active layer, wherein the first active layer comprises a first material; a second transistor, disposed on the transmissible region, and comprising a second active layer, wherein the second active layer comprises a second material that is different from the first material; a plurality of first transistors; a plurality of second transistors; a plurality of reflective regions; a plurality of transmissible regions; a plurality of data lines; and a plurality of scanning lines, wherein the plurality of scanning lines is interlaced with the plurality of data lines; wherein each of the first transistors and each of the second transistors are coupled to one of the data lines, one of the scanning lines, and one of the pixels; wherein the reflective regions and the transmissible regions are arranged into a matrix with a plurality of columns and a plurality of rows and are corresponding to the pixels; and wherein each of the data lines is only coupled to the first transistors or the second transistors; wherein the substrate is divided into a plurality of pixel groups, each of the pixel groups comprises a plurality of pixels, and each of the plurality of pixel groups contain either a set of serially connected first transistors or a set of serially connected second transistors.

2. The display panel according to claim 1, wherein the first active layer comprises an oxide semiconductor, and the second active layer comprises polysilicon.

3. The display panel according to claim 1, wherein each of the pixel groups further comprises: an x.sup.th data line, an (x+1).sup.th data line, and an (x+2).sup.th data line disposed sequentially along a first direction, wherein x is a positive integer; one of the first transistors, located between the x.sup.th data line and the (x+1).sup.th data line and coupled to the x.sup.th data line; and one of the second transistors, located between the (x+1).sup.th data line and the (x+2).sup.th data line and coupled to the (x+1).sup.th data line.

4. The display panel according to claim 1, wherein each of the pixel groups comprises: an x.sup.th data line, an (x+1).sup.th data line, and an (x+2).sup.th data line disposed sequentially along a first direction; an m.sup.th column and n.sup.th row of the first transistors and an m.sup.th column and (n+1).sup.th row of the second transistors, located between the x.sup.th data line and the (x+1).sup.th data line, wherein the m.sup.th column and n.sup.th row of the first transistors is coupled to the (x+1).sup.th data line, and the m.sup.th column and (n+1).sup.th row of the second transistors is coupled to the x.sup.th data line; and an (m+l).sup.th column and nth row of the second transistors and an (m+l).sup.th column and (n+l).sup.th row of the first transistors, located between the (x+1).sup.th data line and the (x+2).sup.th data line, wherein the (m+l).sup.th column and n.sup.th row of the second transistors is coupled to the (x+2).sup.th data line, and the (m+l).sup.th column and (n+l).sup.th row of the first transistors is coupled to the (x+1).sup.th data line, wherein x, m, and n are positive integers.

5. The display panel according to claim 1, wherein each of the pixel groups comprises: an x.sup.th data line, an (x+1).sup.th data line, and an (x+2).sup.th data line disposed sequentially along a first direction; an m.sup.th column and n.sup.th row of the second transistors, an (m+l).sup.th column and n.sup.th row of the second transistors, an m.sup.th column and (n+1).sup.th row of the first transistors, and an (m+1).sup.th column and (n+1).sup.th row of the first transistors, located between the x.sup.th data line and the (x+1).sup.th data line, wherein the (m+1).sup.th column and n.sup.th row of the second transistors is coupled to the x.sup.th data line via the m.sup.th column and nth row of the second transistors, and the m.sup.th column and (n+1).sup.th row of the first transistors is coupled to the (x+1).sup.th data line via the (m+1).sup.th column and (n+l).sup.th row of the first transistors; and an (m+2).sup.th column and nth row of the first transistors, an (m+3).sup.th column and n.sup.th row of the first transistors, an (m+2).sup.th column and (n+1).sup.th row of the second transistors, and an (m+3).sup.th column and (n+1).sup.th row of the second transistors, located between the (x+1).sup.th data line and the (x+2).sup.th data line, wherein the (m+3).sup.th column and n.sup.th row of the first transistors is coupled to the (x+1).sup.th data line via the (m+2).sup.th column and nth row of the first transistors, and the (m+2).sup.th column and (n+1).sup.th row of the second transistors is coupled to the (x+2).sup.th data line via the (m+3).sup.th column and (n+1).sup.th row of the second transistors, wherein x, m, and n are positive integers.

6. The display panel claim 1, wherein each of the pixel groups comprises: an x.sup.th data line, an (x+1).sup.th data line, an (x+2).sup.th data line, and an (x+3).sup.th data line disposed sequentially along a first direction; an m.sup.th column and (n+1).sup.th row of the first transistors and an (m+1).sup.th column and n.sup.th row of the first transistors, located between the x.sup.th data line and the (x+2).sup.th data line, wherein the (m+1).sup.th column and n.sup.th row of the first transistors is coupled to the x.sup.th data line by using the m.sup.th column and (n+1).sup.th row of the first transistors; and an (m+1).sup.th column and (n+1).sup.th row of the second transistors and an (m+2).sup.th column and n.sup.th row of the second transistors, located between the (x+1).sup.th data line and the (x+3).sup.th data line, wherein the (m+2).sup.th column and n.sup.th row of the second transistors is coupled to the (x+1).sup.th data line by using the (m+1).sup.th column and (n+1).sup.th row of the second transistors, wherein x, m, and n are positive integers.

7. The display panel according to claim 1, wherein each of the pixel groups comprises: an x.sup.th data line, an (x+1).sup.th data line, an (x+2).sup.th data line, and an (x+3).sup.th data line disposed sequentially along a first direction; an m.sup.th column and n.sup.th row of the first transistors and an (m+3).sup.th column and n.sup.th row of the first transistors, located between the x.sup.th data line and the (x+2).sup.th data line, wherein the (m+3).sup.th column and n.sup.th row of the first transistors is coupled to the x.sup.th data line by using the m.sup.th column and n.sup.th row of the first transistors; and an (m+2).sup.th column and nth row of the second transistors and an (m+5).sup.th column and n.sup.th row of the second transistors, located between the (x+1).sup.th data line and the (x+3).sup.th data line, wherein the (m+5).sup.th column and n.sup.th row of the second transistors is coupled to the (x+1).sup.th data line by using the (m+2).sup.th column and n.sup.th row of the second transistors, wherein x, m, and n are positive integers.

8. The display panel according to claim 1, wherein each of the pixel groups comprises: an x.sup.th data line, an (x+1).sup.th data line, an (x+2).sup.th data line, and an (x+3).sup.th data line disposed sequentially along a first direction, wherein extension directions of the x.sup.th data line, the (x+1).sup.th data line, the (x+2).sup.th data line, and the (x+3).sup.th data line are partially parallel to the first direction, and partially parallel to a second direction approximately perpendicular to the first direction; an (m+5).sup.th column and (n+1).sup.th row of the first transistors located between the (x+1).sup.th data line and the (x+2).sup.th data line, and an (m+4).sup.th column and (n+2).sup.th row of the first transistors and an (m+6).sup.th column and n.sup.th row of the first transistors located between the (x+2).sup.th data line and the (x+3).sup.th data line, wherein the (m+6).sup.th column and nth row of the first transistors is coupled to the (x+2).sup.th data line by using the (m+4).sup.th column and (n+2).sup.th row of the first transistors and the (m+5).sup.th column and (n+1).sup.th row of the first transistors; an (m+2).sup.th column and (n+l).sup.th row of the second transistors located between the x.sup.th data line and the (x+1).sup.th data line, and an (m+1).sup.th column and (n+2).sup.th row of the second transistors and an (m+3).sup.th column and nth row of the second transistors located between the (x+1).sup.th data line and the (x+2).sup.th data line, wherein the (m+3).sup.th column and n.sup.th row of the second transistors is coupled to the (x+1).sup.th data line by using the (m+1).sup.th column and (n+2).sup.th row of the second transistors and the (m+2).sup.th column and (n+1).sup.th row of the second transistors, wherein x, m, and n are positive integers.

9. The display panel according to claim 1, further comprising: a reflective layer, located on the reflective region; a first pixel electrode, located on the reflective region and coupled to the first transistor; and a second pixel electrode, located on the transmissible region and coupled to the second transistor.

10. The display panel according to claim 1, wherein each of the data lines are disposed sequentially along a first direction, have a winding shape, and extend in both the first direction and a second direction orthogonal to the first direction.

11. The display panel according to claim 10, wherein each of the data lines are coupled to the first transistors or the second transistors of pixels in three successive different rows.

12. The display panel according to claim 1, wherein the respective first or second transistors of each set of serially connected first or second transistors are arranged in different rows and columns of the matrix.

13. The display panel according to claim 1, wherein each of the plurality of pixel groups contain a red pixel, a green pixel, and a blue pixel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a top view of a display panel according to an embodiment of the present disclosure;

(2) FIG. 2 illustrates a schematic view of a pixel layout of a display panel according to an embodiment of the present disclosure;

(3) FIG. 3 illustrates a schematic view of a pixel layout of a display panel according to another embodiment of the present disclosure;

(4) FIG. 4 illustrates a schematic view of a pixel layout of a display panel according to another embodiment of the present disclosure;

(5) FIG. 5 illustrates a schematic view of a pixel layout of a display panel according to another embodiment of the present disclosure;

(6) FIG. 6 illustrates a schematic view of a pixel layout of a display panel according to another embodiment of the present disclosure;

(7) FIG. 7 illustrates a schematic view of a pixel layout of a display panel according to another embodiment of the present disclosure;

(8) FIG. 8 illustrates a partial sectional view of a display panel according to an embodiment of the present disclosure;

(9) FIG. 9 illustrates a partial sectional view of a display panel according to another embodiment of the present disclosure;

(10) FIG. 10 illustrates a partial sectional view of a display panel according to another embodiment of the present disclosure; and

(11) FIG. 11 illustrates a partial sectional view of a display panel according to another embodiment of the present disclosure.

DETAILED DESCRIPTION

(12) The present disclosure relates to a display panel. The display panel of the present disclosure includes a reflective region and a transmissible region, and different types of first transistors and second transistors are selected for the reflective region and the transmissible region. Because materials used by the first transistors can reduce the current leakage of the display panel, and material used by the second transistors can improve the frame rate of the display panel, effects of both saving power and promoting image quality can be achieved.

(13) FIG. 1 illustrates a top view of a display panel 10 according to an embodiment of the present disclosure.

(14) Referring to FIG. 1, the display panel 10 includes a substrate 101, and a surface 101a of the substrate 101 includes a visible region AA, a peripheral circuit region AB, and a drive circuit region AC. The substrate 101 may be paired with another substrate (not illustrated), and a liquid crystal layer (not illustrated) may exist between the substrate 101 and the another substrate. The surface 101a is a surface facing the liquid crystal layer and the another substrate, namely, an inner side of the substrate 101. The visible region AA of the substrate 101 includes reflective regions Rr and transmissible regions Tr, as shown by the block AAi of a partially visible region AA in FIG. 2.

(15) FIG. 2 illustrates a schematic view of a pixel layout of the display panel 10 according to an embodiment of the present disclosure.

(16) Referring to FIG. 2, the display panel 10 includes first transistors I (such as I.sub.2,1, I.sub.4,1, I.sub.6,1 . . . I.sub.2,2, I.sub.4,2, I.sub.6,2 . . . , I.sub.2,3, I.sub.4,3, I.sub.6,3 . . . ) and second transistors L (such as L.sub.1,1, L.sub.3,1, L.sub.5,1 . . . L.sub.1,2, L.sub.3,2, L.sub.5,2 . . . L.sub.1,3, L.sub.3,3, L.sub.5,3). The first transistors I are configured on the surface 101a of the substrate 101 and located on the corresponding reflective regions Rr. The second transistors L are configured on the surface 101a of the substrate 101 and located on the corresponding transmissible regions Tr. The first transistor I includes a first active layer; and the second transistor L includes a second active layer. A material of the first active layer may be different from a material of the second active layer. In an embodiment, the material of the first active layer includes an oxide semiconductor, and the oxide semiconductor may be a mixture of oxides of group 2 to 4 elements in the periodic table of elements, such as IGZO, IZTO, IGTO, IZO, IGO, ZTO, and SnO. The material of the second active layer includes polysilicon. In other words, the first transistor I may be an oxide semiconductor transistor, and the second transistor L may be a polysilicon transistor.

(17) Compared with an oxide semiconductor transistor and an amorphous silicon transistor, a polysilicon transistor has a higher charging rate, can provide a better frame rate of the display panel and improve the phenomenon of motion blur, and has excellent pixel quality when rendering dynamic images. Compared with a polysilicon semiconductor transistor and an amorphous silicon transistor, an oxide semiconductor transistor has a lower current leakage, and can still maintain static images under an operation of reducing the frame rate, and achieve the objective of reducing power consumption of the display panel. In the present disclosure, an oxide semiconductor transistor is selected for a first transistor I corresponding to the reflective region, and a polysilicon transistor is selected for a second transistor L corresponding to the transmissible region, so that by means of the feature of its low current leakage, the oxide semiconductor transistor can maintain an operation of a low frame rate when static images need to be rendered, to achieve a power-saving requirement, and by means of the feature of its high charging capability, the polysilicon transistor can execute an operation of a high frame rate when dynamic images need to be rendered, to achieve the objective of improving image quality of a video. Therefore, a display panel having excellent image quality and power-saving effects can be provided.

(18) Referring to FIG. 2, the display panel 10 includes a plurality of data lines D1, D2, D3, D4, D5, D6, D7 . . . and a plurality of scanning lines G1, G2, G3, G4 . . . that are interlaced. The substrate 101 is divided into a plurality of pixel groups, and each of the pixel groups includes a plurality of pixels (such as a red pixel R, a green pixel G, and a blue pixel B (not illustrated)). The data lines D1, D2, D3, D4, D5, D6, D7 . . . for example, extend along a Y direction and are arranged sequentially along an X direction. The scanning lines G1, G2, G3, G4 . . . for example, extend along the X direction and are arranged sequentially along the Y direction. The X direction may be perpendicular to the Y direction. Each of the first transistors I.sub.2,1, I.sub.4,1, I.sub.6,1 . . . I.sub.2,2, I.sub.4,2, I.sub.6,2 . . . , I.sub.2,3, I.sub.4,3, I.sub.6,3 . . . and each of the second transistors L.sub.1,1, L.sub.3,1, L.sub.5,1 . . . L.sub.1,2, L.sub.3,2, L.sub.5,2 . . . L.sub.1,3, L.sub.3,3, L.sub.5,3 are coupled to the corresponding data lines D1, D2, D3, D4, D5, D6, D7 . . . , scanning lines G1, G2, G3, G4 . . . , and pixels. The reflective regions Rr and the transmissible regions Tr are arranged into a matrix including a plurality of columns and a plurality of rows and corresponding to the pixels. According to the difference of reflective regions Rr and transmissible regions Tr on which the pixels are located, each of the pixels are separately corresponding to a first pixel electrode 180a and a second pixel electrode 180b. The matrix, for example, has an M.sub.1.sup.st column, an M.sub.2.sup.nd column, an M.sub.3.sup.rd column . . . an M.sub.m.sup.th column, an M.sub.m+1.sup.th column . . . , and an N.sub.1.sup.st row of, N.sub.2.sup.nd row of, N.sub.3.sup.rd row of . . . an N.sub.n.sup.th column, an N.sub.n+1.sup.th column . . . m and n are positive integers. Each of the data lines D1, D2, D3, D4, D5, D6, D7 . . . is only coupled to the first transistors I.sub.2,1, I.sub.4,1, I.sub.6,1 . . . I.sub.2,2, I.sub.4,2, I.sub.6,2 . . . , I.sub.2,3, I.sub.4,3, I.sub.6,3 . . . or the second transistors L.sub.1,1, L.sub.3,1, L.sub.5,1 . . . L.sub.1,2, L.sub.3,2, L.sub.5,2 . . . L.sub.1,3, L.sub.3,3, L.sub.5,3. For example, the data line D1 is only coupled to the second transistors L.sub.1,1, L.sub.1,2, L.sub.1,3 . . . , but is not coupled to any first transistor I. The data line D2 is only coupled to the first transistors I.sub.2,1, I.sub.2,2, I.sub.2,3 . . . , but is not coupled to any second transistor L. Each of the scanning lines G1, G2, G3 . . . may be coupled to the first transistor and the second transistor. For example, the scanning line G1 is coupled to the first transistors I.sub.2,1, I.sub.4,1, I.sub.6,1 . . . and the second transistors L.sub.1,1, L.sub.3,1, L.sub.5,1 . . . .

(19) In the present disclosure, the data lines D1, D2, D3, D4 . . . may be in a sequence relationship. For example, in an embodiment, the data line D1 may represent an x.sup.th data line, the data line D2 may represent an (x+1).sup.th data line, the data line D3 may represent an (x+2).sup.th data line, the data line D4 may represent an (x+3).sup.th data line, and so on. In another embodiment, the data line D1 may represent an (x−1).sup.d′ data line, the data line D2 may represent an x.sup.th data line, the data line D3 may represent an (x+1).sup.th data line, the data line D4 may represent an (x+2).sup.th data line, and so on. However, the present disclosure is not limited thereto. x may be any positive integer.

(20) In this embodiment, the first transistor I.sub.2,1 is located between the data line D2 and the data line D3 and coupled to the data line D2. The second transistor L.sub.3,1 is located between the data line D3 and the data line D4 and coupled to the data line D3. In addition, both the first transistor I.sub.2,1 and the second transistor L.sub.3,1 are coupled to the scanning line G1.

(21) FIG. 3 illustrates a schematic view of a pixel layout of a display panel 20 according to another embodiment of the present disclosure, and is similar to the region of the block AAi of the partially visible region AA in FIG. 2. The difference from the embodiment of FIG. 2 lies in: a same column of pixels may set the reflective region Rr and the transmissible region Tr alternatively.

(22) Referring to FIG. 3, an M.sub.1.sup.st column and N.sub.1.sup.st row of first transistor I.sub.1,1 and an M.sub.1.sup.st column and N.sub.2.sup.nd row of second transistor L.sub.1,2 are located between the data line D1 and the data line D2, the M.sub.1.sup.st column and N.sub.1.sup.st row of first transistor I.sub.1,1 is coupled to the data line D2, and the M.sub.1.sup.st column and N.sub.2.sup.nd row of second transistor L.sub.1,2 is coupled to the data line D1. An M.sub.2.sup.nd column and N.sub.1.sup.st row of second transistor L.sub.2,1 and an M.sub.2.sup.nd column and N.sub.2.sup.nd row of first transistor I.sub.2,2 are located between the data line D2 and the data line D3, the M.sub.2.sup.nd column and N.sub.1.sup.st row of second transistor L.sub.2,1 is coupled to the data line D3, and the M.sub.2.sup.nd column and N.sub.2.sup.nd row of first transistor I.sub.2,2 is coupled to the data line D2. The data line D1 is only coupled to the second transistor L.sub.1,2 . . . , but is not coupled to any first transistor I. The data line D2 is only coupled to the first transistors I.sub.1,1, I.sub.2,2, and I.sub.1,3 . . . , but is not coupled to any second transistor L. Compared with the pixel layout of the display panel 10 in FIG. 2, because in the pixel layout of the display panel 20 in FIG. 3, a same column of pixels are not all corresponding to a same type of transistors, but two different types of transistors (first transistor and second transistor) are separated, so that a uniform display effect can be achieved.

(23) In this embodiment, each of the scanning lines G1, G2, G3 . . . may be coupled to the first transistor and the second transistor. For example, the scanning line G1 is coupled to the first transistors I.sub.1,1, I.sub.3,1, I.sub.5,1 . . . and the second transistors L.sub.2,1, L.sub.4,1, L.sub.6,1 . . . .

(24) FIG. 4 illustrates a schematic view of a pixel layout of a display panel 30 according to another embodiment of the present disclosure, and is similar to the region of the block AAi of the partially visible region AA in FIG. 2. The difference from the embodiment of FIG. 2 lies in: a same column of pixels may set the reflective region Rr and the transmissible region Tr alternatively, and each of the data lines may be coupled to two transistors in a same row of pixels.

(25) Referring to FIG. 4, an M.sub.1.sup.st column and N.sub.1.sup.st row of second transistor L.sub.1,1, an M.sub.2.sup.nd column and N.sub.1.sup.st row of second transistor L.sub.2,1, an M.sub.1.sup.st column and N.sub.2.sup.nd row of first transistor I.sub.1,2, and an M.sub.2.sup.nd column and N.sub.2.sup.nd row of first transistor I.sub.2,2 are located between the data line D1 and the data line D2. The second transistor L.sub.2,1 is coupled to the data line D1 by using the second transistor L.sub.1,1. The first transistor I.sub.1,2 is coupled to the data line D2 by using the first transistor I.sub.2,2. An M.sub.3.sup.rd column and N.sub.1.sup.st row of first transistor I.sub.3,1, an M.sub.4.sup.th column and N.sub.1.sup.st row of first transistor I.sub.4,1, an M.sub.3.sup.rd column and N.sub.2.sup.nd row of second transistor L.sub.3,2, and an M.sub.4.sup.th column and N.sub.2.sup.nd row of second transistor L.sub.4,2 are located between the data line D2 and the data line D3. The first transistor I.sub.4,1 is coupled to the data line D2 by using the first transistor I.sub.3,1. The second transistor L.sub.3,2 is coupled to the data line D3 by using the second transistor L.sub.4,2. The data line D1 is only coupled to the second transistors L.sub.1,1, L.sub.2,1, L.sub.1,3, L.sub.2,3 . . . , but is not coupled to any first transistor I. The data line D2 is only coupled to the first transistors I.sub.3,1, I.sub.4,1, I.sub.1,2, I.sub.2,2 . . . , but is not coupled to any second transistor L.

(26) In an embodiment, each of the scanning lines G1, G2, G3 . . . may be coupled to the first transistor and the second transistor. For example, the scanning line G1 is coupled to the first transistor I.sub.4,1 . . . and the second transistor L.sub.2,1 . . . . A pixel may exist between the first transistor I.sub.4,1 and the second transistor L.sub.2,1 The scanning line G2 is coupled to the first transistors I.sub.1,2, I.sub.3,1 . . . and the second transistors L.sub.1,1, L.sub.3,2 . . . . The scanning line G2 is located between the second transistor L.sub.1,1 and the first transistor I.sub.1,2 and located between the first transistor I.sub.3,1 and the second transistor L.sub.3,2.

(27) The display panel 30 of this embodiment uses a half source line driving (HSD) pixel layout, which includes fewer data lines compared with the embodiments of the display panels 10 and 20, so that the amounts of pins and pads of an integrated circuit can be reduced, the area of a frame of the display panel can be smaller, and more costs can be reduced.

(28) FIG. 5 illustrates a schematic view of a pixel layout of a display panel 40 according to another embodiment of the present disclosure, and is similar to the region of the block AAi of the partially visible region AA in FIG. 2. The difference from the embodiment of FIG. 2 lies in: each column of pixels include two different types of transistors (first transistor I and second transistor L), and each of the data lines may be coupled to two transistors in neighboring two rows of pixels.

(29) Referring to FIG. 5, an M.sub.1.sup.nd column and N.sub.2.sup.nd row of first transistor I.sub.2,2 and an M.sub.3.sup.rd column and N.sub.1.sup.st row of first transistor I.sub.3,1 are located between the data line D2 and the data line D4, namely, an M.sub.2.sup.nd column and N.sub.2.sup.nd row of first transistor I.sub.2,2 is located between the data line D2 and the data line D3, and an M.sub.3.sup.rd column and N.sub.1.sup.st row of first transistor I.sub.3,1 is located between the data line D3 and the data line D4. The M.sub.3.sup.rd column and N.sub.1.sup.st row of first transistor I.sub.3,1 is coupled to the data line D2 by using the M.sub.2.sup.nd column and N.sub.2.sup.nd row of first transistor I.sub.2,2. An M.sub.3.sup.rd column and N.sub.2.sup.nd row of second transistor L.sub.3,2 and an M.sub.4.sup.th column and N.sub.1.sup.st row of second transistor L.sub.4,1 are located between the data line D3 and the data line D5, namely, an M.sub.3.sup.rd column and N.sub.2.sup.nd row of second transistor L.sub.3,2 is located between the data line D3 and the data line D4, and an M.sub.4.sup.th column and N.sub.1.sup.st row of second transistor L.sub.4,1 are located between the data line D4 and the data line D5. The M.sub.4.sup.th column and N.sub.1.sup.st row of second transistor L.sub.4,1 is coupled to the data line D3 by using the M.sub.3.sup.rd column and N.sub.2.sup.nd row of second transistor L.sub.3,2.

(30) In this embodiment, each of the scanning lines G1, G2, G3 . . . may be coupled to the first transistor and the second transistor. For example, the scanning line G1 is coupled to the first transistors I.sub.1,1, I.sub.3,1, I.sub.5,1 . . . and the second transistors L.sub.2,1, L.sub.4,1, L.sub.6,1 . . . . The scanning line G2 is coupled to the N.sub.2.sup.nd row of first transistors I.sub.2,2, I.sub.4,2 . . . and second transistors L.sub.1,2, L.sub.3,2 . . . , and is coupled to the N.sub.3.sup.rd row of first transistor I.sub.2,3 . . . and second transistor L.sub.1,3.

(31) FIG. 6 illustrates a schematic view of a pixel layout of a display panel 50 according to another embodiment of the present disclosure, and is similar to the region of the block AAi of the partially visible region AA in FIG. 2. The difference from the embodiment of FIG. 2 lies in: each column of pixels only has one type of transistor, for example, an M.sub.1.sup.st column of pixels have a second transistor L, an M.sub.1.sup.nd column of pixels have a first transistor I . . . , and each of the data lines may be coupled to two transistors in a same row of pixels.

(32) Referring to FIG. 6, an M.sub.3.sup.rd column and N.sub.1.sup.st row of first transistor I.sub.3,1 and an M.sub.6.sup.th column and N.sub.1.sup.st row of first transistor I.sub.6,1 are located between the data line D2 and the data line D4. The M.sub.6.sup.th column and N.sub.1.sup.st row of first transistor I.sub.6,1 is coupled to the data line D2 by using the M.sub.3.sup.rd column and N.sub.1.sup.st row of first transistor I.sub.3,1. An M.sub.5.sup.th column and N.sub.1.sup.st row of second transistor L.sub.5,1 and an M.sub.8.sup.th column and N.sub.1.sup.st row of second transistor L.sub.8,1 are located between the data line D3 and the data line D5. The M.sub.8.sup.th column and N.sub.1.sup.st row of second transistor L.sub.8,1 is coupled to the data line D3 by using the M.sub.5.sup.th column and N.sub.1.sup.st row of second transistor L.sub.5,1.

(33) In an embodiment, each of the scanning lines G1, G2, G3 . . . may be coupled to the first transistor and the second transistor. For example, the scanning line G1 is coupled to the first transistors I.sub.2,1, I.sub.6,1 . . . and the second transistors L.sub.4,1, L.sub.8,1 . . . . The scanning line G2 is coupled to the N.sub.1.sup.st row of first transistors I.sub.3,1, I.sub.7,1 . . . and second transistors L.sub.1,1, L.sub.5,1 . . . , and coupled to the N.sub.2.sup.nd row of first transistor I.sub.3,2 . . . and second transistor L.sub.1,2.

(34) Because the display panel 50 of this embodiment has both the reflective region Rr and the transmissible region Tr in one pixel, the display panel 50 has better resolution compared with the embodiments of the display panels 10, 20, and 30 in which one pixel region has only the reflective region Rr or only the transmissible region Tr.

(35) FIG. 7 illustrate a schematic view of a pixel layout of a display panel 60 according to another embodiment of the present disclosure, and is similar to the region of the block AAi of the partially visible region AA in FIG. 2. The difference from the embodiment of FIG. 2 lies in: a same column of pixels may set the reflective regions Rr and the transmissible regions Tr alternatively, each of the data lines may be coupled to three successive different rows of pixels of transistors. Some of the data lines D1, D2, D3, D4 . . . extend along an X direction, and some extend along a Y direction and have a winding shape.

(36) Referring to FIG. 7, an M.sub.8.sup.th column and N.sub.2.sup.nd row of first transistor I.sub.8,2 is located between the data line D2 and the data line D3, and an M.sub.7.sup.th column and N.sub.3.sup.rd row of first transistor I.sub.7,3 and an M.sub.9.sup.th column and N.sub.1.sup.st row of first transistor I.sub.9,1 is located between the data line D3 and the data line D4. The first transistor I.sub.9,1 is coupled to the data line D3 by using the first transistor I.sub.7,3 and the first transistor I.sub.8,2. An M.sub.5.sup.th column and N.sub.2.sup.nd row of second transistor L.sub.5,2 is located between the data line D1 and the data line D2, and an M.sub.4.sup.th column and N.sub.3.sup.rd row of second transistor L.sub.4,3 and an M.sub.6.sup.th column and N.sub.1.sup.st row of second transistor L.sub.6,1 are located between the data line D2 and the data line D3. The second transistor L.sub.6,1 is coupled to the data line D2 by using the second transistor L.sub.4,3 and the second transistor L.sub.5,2.

(37) In an embodiment, each of the scanning lines G1, G2, G3 . . . may be coupled to the first transistor and the second transistor. For example, the scanning line G2 is coupled to the first transistors I.sub.1,1, I.sub.3,1, I.sub.5,1 . . . and the second transistors L.sub.2,1, L.sub.4,1, L.sub.6,1 . . . .

(38) The display panel 60 of this embodiment uses a one third source line driving (OTSD) pixel layout, which has fewer data lines compared with the embodiments of the display panels 10, 20, and 30, so that the consumption of pins and pads of an integrated circuit can be reduced, the area of a frame of the display panel can be smaller, and more costs can be reduced.

(39) FIG. 8 illustrates a partial sectional view of a display panel 70 according to an embodiment of the present disclosure.

(40) Referring to FIG. 8, FIG. 8 illustrates a partial sectional view of a corresponding first transistor I.sub.141 and a corresponding second transistor L.sub.142 of the display panel 70. The display panel 70 includes a substrate 101, a buffer layer 110, a first insulating layer 120, a second insulating layer 130, a first transistor I.sub.141, a second transistor L.sub.142, a first protective layer 150, a second protective layer 160, a reflective layer 170, a first pixel electrode 181, and a second pixel electrode 182. The substrate 101 includes a reflective region Rr and a transmissible region Tr. The buffer layer 110 is formed on the substrate 101. The first insulating layer 120 is formed on the buffer layer 110. The second insulating layer 130 is formed on the first insulating layer 120. The first protective layer 150 is formed on the second insulating layer 130. The first transistor I.sub.141 and the second transistor L.sub.142 are configured on the substrate 101, formed between the buffer layer 110 and the first protective layer 150, and separately located on the corresponding reflective region Rr and transmissible region Tr. The second protective layer 160 is formed on the first protective layer 150, the reflective layer 170 is formed on the second protective layer 160 of the reflective region Rr, and the first pixel electrode 181 is formed on the reflective layer 170.

(41) The first transistor I.sub.141 includes a first active layer I.sub.411, a first source 1412, a first drain 1413, and a first gate 1414. The first gate 1414 is located on a lower side of the first active layer I.sub.411. The first transistor I.sub.141 is also referred to as a bottom gate transistor. The second transistor L.sub.142 includes a second active layer 1421, a second source 1422, a second drain 1423, and a second gate 1424. The second gate 1424 is located on an upper side of the second active layer 1421. The second transistor L.sub.142 is also referred to as a top gate transistor. The first pixel electrode 181 and the second pixel electrode 182 are respectively coupled to the first drain 1413 and the second drain 1423 by using through holes 191 and 192.

(42) A material of the first active layer 1411 includes an oxide semiconductor, and the oxide semiconductor may be a mixture of oxides of group 2 to 4 elements in the periodic table of elements, such as IGZO, IZTO, IGTO, IZO, IGO, ZTO, and SnO. The material of the second active layer 1421 includes polysilicon. Therefore, the display panel 70 of this embodiment uses an oxide semiconductor transistor of a bottom gate in the visible region AA to match a polysilicon transistor of a top gate.

(43) In this embodiment, the substrate 101 may be made of glass. The buffer layer 110 may be made of an inorganic dielectric material. The first insulating layer 120 may be made of oxides, such as SiO. The first source 1412, the first drain 1413, the first gate 1414, the second source 1422, the second drain 1423, and the second gate 1424 may be made of metal.

(44) FIG. 9 illustrates a partial sectional view of a display panel 80 according to another embodiment of the present disclosure. The different from the embodiment of the display panel 70 in FIG. 8 may lie in the structure of the first transistor I.sub.241.

(45) Referring to FIG. 9, the first transistor I.sub.241 includes a first active layer 2411, a first source 2412, a first drain 2413, and a first gate 2414. The first gate 2414 is located on an upper side of the first active layer 2411. The first transistor I.sub.241 is also referred to as a top gate transistor. The second transistor L.sub.242 includes a second active layer 2421, a second source 2422, a second drain 2423, and a second gate 2424. The second gate 2424 is located on an upper side of the second active layer 2421. The second transistor L.sub.242 is also referred to as a top gate transistor. Therefore, the display panel 80 of this embodiment uses an oxide semiconductor transistor of a top gate in the visible region AA to match a polysilicon transistor of a top gate.

(46) A substrate 201, a buffer layer 210, a first insulating layer 220, a second insulating layer 230, a first protective layer 250, a second protective layer 260, a reflective layer 270, a first pixel electrode 281, and a second pixel electrode 282 in FIG. 9 are respectively similar to the substrate 101, the buffer layer 110, the first insulating layer 120, the second insulating layer 130, the first protective layer 150, the second protective layer 160, the reflective layer 170, the first pixel electrode 181, and the second pixel electrode 182 in FIG. 8. The first pixel electrode 281 and the second pixel electrode 282 are respectively coupled to the first drain 2413 and the second drain 2423 by using through holes 291 and 292.

(47) FIG. 10 illustrates a partial sectional view of a display panel 90 according to another embodiment of the present disclosure. The difference from the embodiment of the display panel 70 in FIG. 8 lies in the structure of the second transistor I.sub.342.

(48) Referring to FIG. 10, the first transistor I.sub.341 includes a first active layer 3411, a first source 3412, a first drain 3413, and a first gate 3414. The first gate 3414 is located on a lower side of the first active layer 3411. The first transistor I.sub.341 is also referred to as a bottom gate transistor. The second transistor I.sub.342 includes a second active layer 3421, a second source 3422, a second drain 3423, and a second gate 3424. The second gate 3424 is located on a lower side of the second active layer 3421. The second transistor I.sub.342 is also referred to as a bottom gate transistor. Therefore, the display panel 90 of this embodiment uses an oxide semiconductor transistor of a bottom gate in the visible region AA to match a polysilicon transistor of a bottom gate.

(49) A substrate 301, a buffer layer 310, a first insulating layer 320, a second insulating layer 330, a first protective layer 350, a second protective layer 360, a reflective layer 370, a first pixel electrode 381, and a second pixel electrode 382 in FIG. 10 are respectively similar to the substrate 101, the buffer layer 110, the first insulating layer 120, the second insulating layer 130, the first protective layer 150, the second protective layer 160, the reflective layer 170, the first pixel electrode 181, and the second pixel electrode 182 in FIG. 8. The first pixel electrode 381 and the second pixel electrode 382 are respectively coupled to the first drain 3413 and the second drain 3423 by using through holes 391 and 392.

(50) FIG. 11 illustrates a partial sectional view of a display panel 100 according to another embodiment of the present disclosure. The difference from the embodiment of the display panel 70 in FIG. 8 lies in the structures of the first transistor I.sub.441 and the second transistor L.sub.442.

(51) Referring to FIG. 11, the first transistor I.sub.441 includes a first active layer 4411, a first source 4412, a first drain 4413, and a first gate 4414. The first gate 4414 is located on an upper side of the first active layer 4411. The first transistor I.sub.441 is also referred to as a top gate transistor. The second transistor I.sub.442 includes a second active layer 4421, a second source 4422, a second drain 4423, and a second gate 4424. The second gate 4424 is located on a lower side of the second active layer 4421. The second transistor L.sub.442 is also referred to as a bottom gate transistor. Therefore, the display panel 100 of this embodiment uses an oxide semiconductor transistor of a top gate in the visible region AA to match a polysilicon transistor of a bottom gate.

(52) A substrate 401, a buffer layer 410, a first insulating layer 420, a second insulating layer 430, a first protective layer 450, a second protective layer 460, a reflective layer 470, a first pixel electrode 481, and a second pixel electrode 482 in FIG. 11 are respectively similar to the substrate 101, the buffer layer 110, the first insulating layer 120, the second insulating layer 130, the first protective layer 150, the second protective layer 160, the reflective layer 170, the first pixel electrode 181, and the second pixel electrode 182 in FIG. 8. The first pixel electrode 481 and the second pixel electrode 482 are respectively coupled to the first drain 4413 and the second drain 4423 by using through holes 491 and 492.

(53) The present disclosure provides a display panel. Because the display panel of the present disclosure includes a reflective region and a transmissible region, an oxide semiconductor transistor is selected for a first transistor I corresponding to the reflective region, and a polysilicon transistor is selected for a second transistor L corresponding to the transmissible region, so that by means of the feature of its low current leakage, the oxide semiconductor transistor can maintain an operation of a low frame rate when static images need to be rendered, to achieve a power-saving requirement, and by means of the feature of its high charging capability, the polysilicon transistor can execute an operation of a high frame rate when dynamic images need to be rendered, to achieve the objective of improving image quality of a video. Therefore, a display panel having excellent image quality and power-saving effects can be provided.

(54) In conclusion, although the present invention has been disclosed in foregoing embodiments, they are not used to limit the present invention. A person of ordinary skill in the art can make various variations and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.