METHOD FOR MANUFACTURING TELLURIUM-BASED SEMICONDUCTOR DEVICE, TELLURIUM-BASED SEMICONDUCTOR DEVICE MANUFACTURED THEREBY, AND THIN FILM TRANSISTOR

Abstract

A method for manufacturing a tellurium-based semiconductor device comprises the steps of: preparing a substrate; depositing, on the substrate, a tellurium-based semiconductor material including tellurium and a tellurium oxide so as to form a tellurium-based semiconductor layer; and forming a passivation layer on the tellurium-based semiconductor layer. According to the manufacturing method, heat treatment at a high temperature or cryogenic conditions are not required, and thus, it is possible to manufacture a semiconductor device through a practical process. In addition, since the crystallinity of the tellurium-based semiconductor layer is improved during the manufacturing process, it is possible to provide a p-type semiconductor device having excellent electrical characteristics such as electric field mobility and a current blink ratio.

Claims

1. A method for manufacturing a tellurium-based semiconductor device, comprising: (i) preparing a substrate; (ii) depositing a tellurium-based semiconductor layer comprising one or more of tellurium and a tellurium oxide on the substrate; and (iii) forming a passivation layer on the tellurium-based semiconductor layer.

2. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the substrate comprises an insulating layer thereon.

3. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the tellurium-based semiconductor layer comprises Te and TeO.sub.2.

4. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the tellurium-based semiconductor layer further comprises at least one metal selected from the group consisting of Sn, Al, Sb, Hf, La, Y, Zr, and Zn as a dopant or in the form of alloy.

5. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the deposition of the tellurium-based semiconductor layer is performed by sputtering, chemical vapor deposition, thermal vacuum deposition, electron beam deposition, or atomic layer deposition.

6. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the deposition of the tellurium-based semiconductor layer is performed under an oxygen partial pressure condition of 5 to 15 %.

7. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein a thickness of the tellurium-based semiconductor layer is 2 to 7 nm.

8. The method for manufacturing the tellurium-based semiconductor device of claim 1, further comprising, after the step (ii), performing heat treatment at 100 to 200° C.

9. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the passivation layer comprises at least one selected from the group consisting of Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, Ta.sub.2O.sub.5, La.sub.2O.sub.3, Y.sub.2O.sub.3, AlHfO.sub.x, HfZrO.sub.x, and AlZrO.sub.x.

10. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the formation of the passivation layer is performed by atomic layer deposition, chemical vapor deposition, thermal vacuum deposition, sputtering, or electron beam deposition.

11. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein the formation of the passivation layer is performed at a temperature of 100 to 200° C.

12. The method for manufacturing the tellurium-based semiconductor device of claim 1, wherein a thickness of the passivation layer is 1 to 30 nm.

13. A tellurium-based semiconductor device manufactured by the method of claim 1, comprising: a substrate; a tellurium-based semiconductor layer positioned on the substrate; and a passivation layer positioned on the tellurium-based semiconductor layer.

14. The tellurium-based semiconductor device of claim 13, wherein the tellurium-based semiconductor layer comprises Te and Te.sup.4+ at an atomic ratio of 80:20 to 90:10.

15. A thin film transistor comprising the tellurium-based semiconductor device of claim 13.

Description

DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 illustrates a schematic diagram of a thin film transistor according to one embodiment of the present invention.

[0029] FIG. 2 illustrates a transmission electron microscopy (TEM) image of a thin film transistor according to one embodiment of the present invention.

[0030] FIGS. 3A to 3C illustrate another TEM image of a thin film transistor according to one embodiment of the present invention. FIG. 3A shows a TEM image of an as-deposited tellurium-based semiconductor layer before heat treatment, FIG. 3B shows a TEM image of a tellurium-based semiconductor layer after heat treatment, and FIG. 3C shows a TEM image of a tellurium-based semiconductor layer after forming a passivation layer thereon.

[0031] FIGS. 4A and 4B illustrate an electrical transmission characteristic depending on a drain-source voltage (V.sub.DS) of a thin film transistor according to one embodiment of the present invention. FIG. 4A shows a transmission characteristic of the tellurium-based semiconductor having no passivation layer and FIG. 4B shows a transmission characteristic of the tellurium-based semiconductor having the passivation layer.

[0032] FIGS. 5A and 5B illustrate an electrical transmission characteristic depending on a gate voltage (V.sub.GS) of a thin film transistor according to one embodiment of the present invention. FIG. 5A shows a transmission characteristic of the tellurium-based semiconductor having no passivation layer and FIG. 5B shows a transmission characteristic of the tellurium-based semiconductor having the passivation layer.

[0033] FIGS. 6A to 6C illustrate X-ray diffraction (XRD) analysis results depending on oxygen partial pressure when depositing a tellurium-based semiconductor layer for a thin film transistor according to one embodiment of the present invention. FIG. 6A shows an XRD result an as-deposited tellurium-based semiconductor layer before heat treatment, FIG. 6B shows an XRD result of a tellurium-based semiconductor layer after heat treatment, and FIG. 6C shows an XRD result of a tellurium-based semiconductor layer after forming a passivation layer thereon.

[0034] FIG. 7 illustrates electrical transmission characteristics depending on oxygen partial pressure of a tellurium-based semiconductor layer having a thickness of 9 nm in a thin film transistor according to one embodiment of the present invention.

[0035] FIG. 8 illustrates electrical transmission characteristics depending on oxygen partial pressure of a tellurium-based semiconductor layer having a thickness of 3.5 nm in a thin film transistor according to another embodiment of the present invention.

MODE FOR INVENTION

[0036] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. In general, the nomenclature used herein is one well known and commonly used in the art.

[0037] In the present specification, when a constituent element such as a substrate or layer is described to be “on” another constituent element, this may include a case in which another constituent element is present therebetween as well as a case directly above the other constituent element.

[0038] The present invention relates to a method for manufacturing a tellurium-based semiconductor device, and the manufacturing method of the tellurium-based semiconductor device according to the present invention comprises (i) preparing a substrate; (ii) depositing a tellurium-based semiconductor layer comprising one or more of tellurium and a tellurium oxide on the substrate; and (iii) forming a passivation layer on the tellurium-based semiconductor layer.

[0039] In the present specification, a tellurium-based semiconductor is a concept that encompasses tellurium-containing semiconductor materials, such as tellurium, tellurium oxide, and doped or alloyed states thereof with other elements.

[0040] According to the present invention, when a tellurium-based semiconductor layer is deposited by using a tellurium-based material as a material for a semiconductor layer and a passivation layer is formed on the tellurium-based semiconductor layer, by using a phenomenon that crystals of hexagonal tellurium in the tellurium-based semiconductor layer are grown by the passivation layer and crystallinity is improved, electrical characteristics of semiconductor devices may be improved. In addition, according to the process of the present invention, heat treatment at a high temperature of 300° C. or higher or cryogenic conditions are not required, and a semiconductor line-friendly process is used.

[0041] Hereinafter, each step of the manufacturing method of the tellurium-based semiconductor device according to the present invention will be described in detail.

[0042] In the step (i), a type of the substrate is not particularly limited, and the substrate may be a base substrate generally used for manufacturing semiconductor devices. For example, as the substrate, glass, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polystyrene (PS), polycarbonate (PC), polyimide (PI), polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polyethylene (PE), silicon (Si), SiO.sub.2, and the like may be used.

[0043] Alternatively, the substrate may be an insulating layer formed on a base substrate of a semiconductor device. The insulating layer may be formed of a material with low electrical conductivity used as an interlayer insulating film for general semiconductor devices. For example, the insulating layer may be formed of a silicon oxide, a silicon nitride, a hafnium oxide, an aluminum oxide, a tungsten oxide, a tantalum oxide, a titanium oxide, a ruthenium oxide, or the like, or may be formed of an insulating polymer. For example, when the manufacturing method of the present invention is applied to forming a thin film transistor, the substrate may be a silicon oxide film formed on the surface of a silicon wafer.

[0044] In the step (ii), a tellurium-based semiconductor layer is formed by depositing a tellurium-based semiconductor material comprising one or more of tellurium and a tellurium oxide on the substrate.

[0045] The tellurium-based semiconductor material may comprise at least one of tellurium and tellurium oxide, and may specifically comprise Te, TeO.sub.2, or both. That is, in the tellurium-based semiconductor material, the tellurium atom may be in a state of Te as it is with an oxidation number of 0 (expressed as Te or Te.sup.0), a state having an oxidation number of +4 by configuring TeO.sub.2 (Te.sup.4+), or a state in which Te and Te.sup.4+ are mixed.

[0046] These tellurium-based semiconductor materials may be composed of 5p orbitals in which the maximum energy level of the valence band originates from the Te.sup.0 state, so that they may provide high mobility compared to conventionally known p-type oxide semiconductors having the maximum energy level in the valence band composed of 2p orbitals of oxygen.

[0047] In the present invention, a metal in a positive oxidation state, for example, one or more metals having an oxidation number of +2, +3, or +4 may be added to the tellurium-based semiconductor layer as a dopant or in the form of alloy, thereby controlling the density of holes. For example, Sn, Al, Sb, Hf, La, Y, Zr, Zn, or a combination thereof may be added to the tellurium-based semiconductor layer as a dopant or in the form of alloy.

[0048] Deposition of the tellurium-based semiconductor layer may be performed by various deposition techniques used in the art. Specifically, known deposition techniques such as sputtering, chemical vapor deposition, thermal evaporation deposition, E-beam evaporation deposition, and atomic layer deposition may be used, of which sputtering is the most preferred. For example, the tellurium-based semiconductor layer of the present invention may be deposited by using reactive sputtering in which tellurium is used as a target in a vacuum chamber and argon gas, which is a carrier gas, and oxygen gas, which is a reactive gas, are injected.

[0049] In the present invention, deposition of the tellurium-based semiconductor layer may be performed at a temperature of 0 to 150° C., preferably 20 to 100° C., and more preferably room temperature to 80° C. According to the present invention, it is possible to provide a semiconductor device having excellent physical properties even without using a cryogenic or high temperature process, thereby solving the problem of conventional tellurium deposition being performed at a cryogenic temperature.

[0050] In one embodiment of the present invention, the deposition of the tellurium-based semiconductor layer may be performed under the condition that the oxygen partial pressure is 2 to 23 %, preferably 5 to 15 %, and more preferably 7 to 10 %. The partial pressure of oxygen is defined as a percentage of the pressure of oxygen gas relative to the pressure of the total gas injected during the deposition process. Generally, as the oxygen partial pressure injected in the deposition process of the tellurium-based semiconductor material increases, the surface roughness of the deposited layer decreases, improving transmittance and energy band gap, while crystallinity deteriorates, and electrical characteristics such as a field mobility and a current on/off ratio tend to be deteriorated. In the present invention, it is found that when the tellurium-based semiconductor material is deposited under the oxygen partial pressure conditions in the above range and the passivation layer is formed thereon, the crystallinity and electrical characteristics are not lowered or partially increased while taking advantage of the oxygen injection.

[0051] In the step (ii), a state in which an additional post-process is not performed after depositing the tellurium-based semiconductor layer is referred to as “as-deposited”. In the as-deposited state, it may be in a mixed state of crystalline and amorphous, for example, a mixed state of hexagonal Te and amorphous TeO.sub.2.

[0052] Specifically, in the tellurium-based semiconductor layer before forming a passivation layer to be described later, some of the tellurium atoms may be in a Te state, and other some may be in a Te.sup.4+ state, and the Te and Te.sup.4+ (TeO.sub.2) may be present in a ratio of 40:60 to 78:22 based on the tellurium atom ratio.

[0053] The method of the present invention may further comprise the step of heat-treating the tellurium-based semiconductor layer after the step (ii). By the heat-treatment, the crystallinity of the tellurium-based semiconductor layer increases, the amorphous ratio decreases, and electrical characteristics such as an electric field mobility and a current on/off ratio are improved.

[0054] The heat-treatment may be performed at a temperature of about 50 to 250° C., preferably about 100 to 200° C., and more preferably 130 to 170° C. in an air, oxygen, or vacuum atmosphere. The heat-treatment may be performed for about 30 minutes to 2 hours, preferably about 50 minutes to 90 minutes. Conventionally, when forming the semiconductor layer, the heat-treatment is performed at a high temperature of 300° C. or higher, but in the present invention, even when the heat-treatment is performed at a lower temperature than that of the conventional art, it is possible to provide the semiconductor layer with improved crystallinity and electrical characteristics, so that it may be easily applied to 3D semiconductor manufacturing technology.

[0055] In one embodiment of the present invention, a thickness of the formed tellurium-based semiconductor layer may be 40 nm or less, preferably 1 to 20 nm, and more preferably 2 to 7 nm. Generally, when the thickness of the semiconductor layer is thin, there are advantages in that the current on/off ratio is excellent and the downsizing of the semiconductor device is advantageous, but there is a problem that the electric field mobility and on-current (a current when a voltage is applied) may be reduced. However, in the present invention, it can be confirmed that when the tellurium-based semiconductor layer is deposited in the above range, it not only shows an excellent current on/off ratio due to its thin thickness, but also overcomes the decrease in electric field mobility and on-current due to oxygen injection during the deposition process.

[0056] The tellurium-based semiconductor layer has a two-dimensional p-type semiconductor characteristic, and may be used as a channel layer of a thin film transistor described later, and may also be used as a channel layer of a photo transistor, an active layer of a photodetector, an active layer of a gas sensor, and the like, but is not limited thereto.

[0057] In the step (iii), the passivation layer serves to protect and stabilize the semiconductor layer and is formed to cover the semiconductor layer, and when there is another layer adjacent to the semiconductor layer, it is formed to cover a portion thereof together. For example, in the thin film transistor, the passivation layer may be formed to cover a semiconductor layer exposed between a drain electrode and a source electrode, and may be formed to cover portions of the drain electrode and the source electrode together. In this case, the passivation layer may also serve to insulate a metal wire.

[0058] According to the present invention, the crystallinity of the tellurium-based semiconductor layer may be improved by forming the passivation layer on the semiconductor layer, so that a semiconductor device with a high electric field mobility and high current on/off ratio may be manufactured. Specifically, in the tellurium-based semiconductor layer before the passivation layer is formed, semiconducting Te and amorphous TeO.sub.2 exist in a mixed form, and after the passivation layer is formed, the crystallinity of the hexagonal Te is improved, and amorphous TeO.sub.2 in the tellurium-based semiconductor layer is reduced to hexagonal Te, resulting in improved crystallinity of the tellurium-based semiconductor layer. Accordingly, after forming the passivation layer, the tellurium-based semiconductor layer may be in a mixed state of crystalline and amorphous or a crystalline state. This improvement in crystallinity is presumed to be due to crystal growth as interfacial energy is stabilized through the formation of the passivation layer.

[0059] From this point of view, the tellurium-based semiconductor layer after the passivation layer is formed may comprise Te.sup.0 and Te.sup.4+ (TeO.sub.2) at a ratio of 70:30 to 99:1, preferably 80:20 to 90:10 based on the tellurium atomic ratio.

[0060] In one embodiment of the present invention, the passivation layer may comprise a metal oxide such as Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, Ta.sub.2O.sub.5, La.sub.2O.sub.3, Y.sub.2O.sub.3, or a combination of the above metal oxides such as AlHfO.sub.x, HfZrO.sub.x, AlZrO.sub.x, among which Al.sub.2O.sub.3, HfO.sub.2, and ZrO.sub.2 are preferred and Al.sub.2O.sub.3 is most preferred.

[0061] In the present invention, the passivation layer may be formed by various deposition techniques used in the art. Specifically, known deposition techniques such as atomic layer deposition, chemical vapor deposition, thermal vacuum deposition, sputtering, and electron beam deposition may be used, and among them, atomic layer deposition may be preferably used. The deposition of the passivation layer may be performed at about 50 to 250° C., preferably about 100 to 200° C., and more preferably 130 to 170° C. in an air, oxygen, or vacuum atmosphere.

[0062] In the present invention, a thickness of the passivation layer may be 50 nm or less, preferably 1 to 30 nm, and more preferably 5 to 15 nm. When the thickness of the passivation layer is too thin, it is not sufficient to protect the semiconductor layer from external moisture or foreign substances, so that the electrical characteristics of the device may be deteriorated. Conversely, when the thickness is too thick, stress applied to the device may increase, resulting in deterioration of device performance.

[0063] The present invention also relates to a tellurium-based semiconductor device manufactured by the method.

[0064] The tellurium-based semiconductor device according to the present invention comprises a substrate; a tellurium-based semiconductor layer positioned on the substrate; and a passivation layer positioned on the tellurium-based semiconductor layer.

[0065] In the tellurium-based semiconductor device according to the present invention, a description of the substrate is the same as that of the manufacturing method, so a detailed description thereof will be omitted.

[0066] In the tellurium-based semiconductor device according to the present invention, the tellurium-based semiconductor layer has improved crystallinity by the passivation layer and has different physical properties from the tellurium-based semiconductor layer in the step (ii) of the manufacturing method. The tellurium-based semiconductor layer of the tellurium-based semiconductor device according to the present invention may be in a mixed state of crystalline and amorphous or in a crystalline state.

[0067] Specifically, the tellurium-based semiconductor layer may comprise Te and Te.sup.4+ at an atomic ratio of 80:20 to 90:10.

[0068] In the tellurium-based semiconductor device according to the present invention, a thickness of the tellurium-based semiconductor layer may be 40 nm or less, preferably 1 to 20 nm, and more preferably 2 to 7 nm. Generally, when the thickness of the semiconductor layer is thin, there are advantages of the excellent the current on/off ratio and the downsizing of the semiconductor device, but there is a problem that the electric field mobility and on-current may be reduced. However, in the present invention, when the thickness of the tellurium-based semiconductor layer is in the above range, it may not only show an excellent current on/off ratio, but also overcome the decrease in electric field mobility and on-current due to oxygen injection during the deposition process.

[0069] In the tellurium-based semiconductor device according to the present invention, a description of the passivation layer is the same as that of the manufacturing method, so a detailed description thereof will be omitted.

[0070] The present invention also relates to a thin film transistor comprising the tellurium-based semiconductor device.

[0071] The thin film transistor is a constituent element of an electronic circuit made of semiconductors, and serves to control flow of a current. Main constituent elements of the thin film transistor are a substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, an active layer forming a semiconductor channel, and a passivation layer, and it is driven by a principle of moving electrons from the source electrode to the drain electrode through the semiconductor channel by applying a voltage to the gate electrode. In the present invention, the tellurium-based semiconductor layer may be used as the active layer forming the semiconductor channel of the thin film transistor.

[0072] FIG. 1 illustrates a schematic diagram of a thin film transistor according to one embodiment of the present invention.

[0073] Referring to FIG. 1, a thin film transistor according to one embodiment of the present invention comprises a substrate 10; an insulating layer 20 positioned on the substrate 10; a tellurium-based semiconductor layer 30 positioned on the insulating layer 20; a source electrode 40 and a drain electrode 50 positioned on the tellurium-based semiconductor layer 30; and a passivation layer 60. In this case, the source electrode 40 and the drain electrode 50 are disposed to be spaced apart from each other at both end portions of the tellurium-based semiconductor layer 30. The passivation layer 60 may be formed to cover the tellurium-based semiconductor layer 30, and may also be formed to partially cover the source electrode 40 and the drain electrode 50.

[0074] In the thin film transistor, as the substrate, a silicon (Si) wafer, glass, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polystyrene (PS), polycarbonate (PC), polyimide (PI), polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polyethylene (PE), or the like may be used. The substrate may act as a gate electrode, or a gate electrode may be separately provided on the substrate.

[0075] For example, a gate electrode (not shown) may be positioned on the substrate. The gate electrode serves to control a current between the semiconductor channels, and is formed to extend in one direction on the substrate. As the gate electrode, a conductive metal such as aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy thereof, a metal oxide transparent electrode such as an indium tin oxide (ITO), or a polycrystalline silicon may be used.

[0076] The insulating layer may serve to separate the gate electrode and the semiconductor channel, and may be formed of a silicon oxide, a silicon nitride, a silicon oxynitride, aluminum oxide, an aluminum oxynitride, a hafnium oxide, a zirconium oxide, or the like, and may be formed of a high dielectric material (high-k) with a large dielectric constant as other materials.

[0077] The tellurium-based semiconductor layer is the active layer of the thin film transistor, and configures the semiconductor channel for moving electrons between the source electrode and the drain electrode. A description of the tellurium-based semiconductor layer is the same as that described above in the description of the tellurium-based semiconductor device, so a detailed description thereof will be omitted.

[0078] The source electrode is an electrode that supplies electrons, and the drain electrode is an electrode that receives electrons, and they may use a conductive metal such as aluminum, neodymium, silver, chromium, titanium, tantalum, molybdenum, or an alloy thereof, or a metal oxide transparent electrode such as an indium tin oxide (ITO).

[0079] The passivation layer is a layer that serves to protect the tellurium-based semiconductor layer and improve the crystallinity of the tellurium-based semiconductor layer. A description of the passivation layer is the same as that described in the description of the manufacturing method of the tellurium-based semiconductor device, so a detailed description thereof will be omitted.

[0080] The thin film transistor shown in FIG. 1 has a bottom gate/top contact structure, but the structure of the thin film transistor is not limited thereto, and a thin film transistor having a bottom gate/bottom contact structure, a top gate/top contact structure, or a top gate/bottom contact structure may also be implemented. In the top gate structure, the tellurium-based semiconductor layer may be positioned below the gate electrode and may be disposed to overlap the gate electrode, while in the bottom contact structure, the source/drain electrodes may be positioned below the tellurium-based semiconductor layer to be electrically connected to the tellurium-based semiconductor layer.

[0081] The thin film transistor according to the present invention is a p-type thin film transistor, and may configure a complementary TFT circuit, for example, an inverter together with an n-type thin film transistor. In this case, a CMOS device may be configured by using an oxide semiconductor material such as a ZnO, an IZO, an IGO, or an IGZO as an n-type thin film transistor. In addition, the p-type thin film transistor may be used as a switching element electrically connected to a pixel electrode of an organic light emitting diode or a liquid crystal display, or it may be used as a switching element electrically connected to one electrode of a memory device, for example, one electrode of a resistive-switching random access memory (RRAM), a phase-change random access memory (PRAM), or a magnetic random access memory (MRAM).

EXAMPLES

[0082] Hereinafter, the present invention will be described in more detail through examples. However, these examples show some experimental methods and compositions to illustratively explain the present invention, and the scope of the present invention is not limited to these examples.

Manufacturing Example 1: Manufacturing of Thin Film Transistor Comprising Tellurium-Based Semiconductor Layer

[0083] A p-type Si wafer, which was a gate electrode, was thermally oxidized to grow a 100 nm-thick SiO.sub.2 layer serving as a gate insulating layer on the p-type Si wafer.

[0084] A shadow mask was disposed on the SiO.sub.2 layer, and a TeO.sub.x thin film having a thickness of about 4 nm was deposited through sputtering at room temperature by using a Te target while supplying oxygen as a reaction gas and argon (Ar) as a carrier gas into a chamber. The sputtering was performed under the conditions of input power of 50 W and process pressure of 2 mTorr, and the oxygen partial pressure was controlled to 9 %.

[0085] A shadow mask was disposed on the TeO.sub.x thin film and an electrode pattern was deposited under an Ar atmosphere to form source/drain electrodes (ITO) at both end portions of the TeO.sub.x thin film.

[0086] After that, the TeO.sub.x thin film was heat treated at 150° C. for 1 hour, and an Al.sub.2O.sub.3 layer having a thickness of 10 nm was formed on the TeO.sub.x thin film exposed between the source/drain electrodes at 150° C. by using atomic layer deposition, so that a thin film transistor comprising a tellurium-based semiconductor layer was manufactured.

Experimental Example 1: Transmission Electron Microscopy (TEM) Image Analysis

[0087] TEM image analysis was performed to confirm the crystallinity of the tellurium-based semiconductor layer.

[0088] TEM images of an as-deposited tellurium-based semiconductor layer before heat treatment (a), a tellurium-based semiconductor layer after heat treatment (b), and a tellurium-based semiconductor layer after forming a passivation layer thereon (c) in Manufacturing Example 1 are shown in FIG. 2 and FIGS. 3A to 3C.

[0089] Referring to FIG. 2, in the case of the heat treatment after the deposition, it was confirmed that the crystallinity of hexagonal Te increased in the tellurium-based semiconductor layer compared to the as-deposited one, and in the case of forming the passivation layer thereon, the crystallinity thereof was further improved. It is presumed that the increase in the crystallinity of hexagonal Te by the formation of the passivation layer is related to the crystal growth resulting from the stabilization of the interfacial energy.

[0090] Referring to FIGS. 3A to 3C, when the tellurium-based semiconductor layer was the as-deposited or only heat treatment was performed after deposition, a mixture of semiconducting Te and amorphous TeO.sub.2 was observed, but when the passivation layer was formed thereon, amorphous TeO.sub.2 was not observed. Therefore, it was confirmed that amorphous TeO.sub.2 was reduced to hexagonal Te (two-dimensional Te, tellurene) by the formation of the passivation layer, and growth of metastable hexagonal Te was promoted compared to TeO.sub.2.

[0091] Through these results, it can be seen that the crystallinity of hexagonal Te in the tellurium-based semiconductor layer is grown by heat treatment after deposition and the crystallinity is improved, and the crystallinity may be further improved when a passivation layer is formed thereon.

Experimental Example 2: Electrical Characteristic Measurement

2-1. Electrical Transmission Characteristic

[0092] In order to confirm the transmission characteristic of the thin film transistor of Manufacturing Example 1, mobility (.Math..sub.FE.Lin, .Math..sub.FE.Sat) and current turn-off ratio (I.sub.ON/OFF) were measured while setting a voltage V.sub.DS between the drain and source electrodes to -0.1 V and -10 V, respectively, and the results are shown in FIG. 4B. For comparison, the same measurement was performed on the thin film transistor in which no passivation layer was formed on the tellurium-based semiconductor layer, and the results are shown in FIG. 4A.

[0093] Referring to FIGS. 4A and 4B, when the passivation layer was formed on the tellurium-based semiconductor layer, the electric field mobility .Math..sub.FE.Lin increased from 12.6 cm.sup.2/Vs to 16.0 cm.sup.2/Vs and .Math..sub.FE.Sat increased from 4.7 cm.sup.2/Vs to 8.8 cm.sup.2/Vs and the current on/off ratio increased from 1.1×10.sup.4 to 1.1×10.sup.5, compared to when it is not.

[0094] In addition, the hysteresis phenomenon was controlled from about 40 V to about 10 V, and the subthreshold was improved at the threshold voltage or less. In addition, it was confirmed that it had characteristics as a p-type thin film transistor, as it is turned on when a negative voltage is applied to the gate electrode.

[0095] That is, it was confirmed that a p-type semiconductor having excellent electrical characteristics may be obtained by forming a passivation layer on the tellurium-based semiconductor layer.

2-2. Electrical Output Characteristic

[0096] In order to compare the output characteristics of the thin film transistor of Manufacturing Example 1 before and after forming the passivation layer, I.sub.DS values with respect to V.sub.GS of 0 V, -10 V, -20 V, -30 V, -40 V, and -50 V were measured and the results were shown FIGS. 5A and 5B.

[0097] In FIGS. 5A and 5B, it can be seen that the output characteristics of the transistor in which the passivation layer was formed were improved by about 1.5 times. Therefore, it was confirmed that even in the output characteristics, a higher current value was obtained when the passivation layer was formed.

Manufacturing Example 2: Manufacture of Thin Film Transistor Comprising Tellurium-Based Semiconductor Layer by Controlling Layer Thickness and Oxygen Partial Pressure

[0098] A p-type Si wafer, which was a gate electrode, was thermally oxidized to grow a SiO.sub.2 layer with a thickness of 100 nm, which was a gate insulating layer, on the p-type Si wafer.

[0099] A shadow mask was disposed on the SiO.sub.2 layer, and TeO.sub.x thin films having a thickness of about 3.5 nm and 9 nm were respectively deposited through sputtering by using a Te target while supplying oxygen as a reaction gas and argon (Ar) as a carrier gas into a chamber. The sputtering was performed under the conditions of input power of 20 W and process pressure of 2 mTorr, and the oxygen partial pressure was controlled to 0 %, 9 %, 23 %, 33 % and 50 %, respectively.

[0100] A shadow mask was disposed on the TeO.sub.x thin film and an electrode pattern was deposited under an Ar atmosphere to form source/drain electrodes (ITO) at both end portions of the TeO.sub.x thin film.

[0101] After that, the TeO.sub.x thin film was heat treated at 150° C. for 1 hour, and an Al.sub.2O.sub.3 layer having a thickness of 10 nm was formed on the TeO.sub.x thin film exposed between the source/drain electrodes at 150° C. by using atomic layer deposition. Thus, a total of 10 types of thin film transistors manufactured by varying the thickness and oxygen partial pressure of the tellurium-based semiconductor layer were manufactured.

Experimental Example 3: X-Ray Diffraction (XRD) Crystallinity Analysis

[0102] XRD analysis was performed according to the oxygen partial pressure during the process for five types of thin film transistors having the tellurium-based semiconductor layer having the thickness of 3.5 nm in Manufacturing Example 2, and the crystallinity analysis results are shown in FIG. 6C. For comparison, XRD analysis was also performed on the thin film transistor having the as-deposited tellurium-based semiconductor layer and the thin film transistor in which only heat treatment was performed after depositing the tellurium-based semiconductor layer and no passivation layer was formed thereon, and the results are shown in FIGS. 6A and 6B.

[0103] Referring to FIG. 6A, when the tellurium-based semiconductor layer was as-deposited and when the oxygen partial pressure was 0%, it was deposited as hexagonal Te. As the oxygen partial pressure increased, the crystallinity decreased, and in particular, it was deposited in an amorphous state at 23% or more.

[0104] On the other hand, when heat treatment was performed after depositing the tellurium-based semiconductor layer, or when the passivation layer was formed thereon after heat treatment, a result that the hexagonal Te was grown as compared to the as-deposited state under the same oxygen partial pressure conditions was confirmed.

[0105] Through these results, it was confirmed that the crystallinity of the tellurium-based semiconductor layer was improved by the heat treatment after the deposition and the passivation layer formation.

Experimental Example 4: Electrical Transmission Characteristic Analysis

[0106] In order to confirm the electrical transmission characteristics of 10 types of thin film transistors of Manufacturing Example 2, the mobility (.Math..sub.FELin, .Math..sub.FE.Sat) and the current on/off ratio (I.sub.ON/OFF) were measured while the voltage VDS between the drain and source electrodes was applied at -0.1 V and -10 V, respectively. The results are shown in FIG. 7 and FIG. 8, and the specific values are shown in Table 1 below.

TABLE-US-00001 Te layer thickness Electrical characteristic Oxygen partial pressure 0% 9% 23% 33% 50% 9 nm .Math..sub.FE.Lin (cm.sup.2/Vs) 21.5 12.1 2.8 4.3 0.1 .Math..sub.FE.Sat (cm.sup.2/Vs) 10.8 3.7 6.6 1.8 0.04 I.sub.ON/OFF 2.0 × 10.sup.2 4.7 × 10.sup.2 1.1 × 10.sup.3 1.8 × 10.sup.3 1.2 × 10.sup.3 3.5 nm .Math..sub.FE.Lin (cm.sup.2/Vs) 5.9 ± 0.3 10.2 ± 1.1 2.5 ± 0.1 0.7 ± 0.1 - .Math..sub.FE.Sat (cm.sup.2/Vs) 3.6 ± 0.1 6.5 ± 0.7 1.6 ± 0.0 0.6 ± 0.1 - I.sub.ON/OFF (1.1 ± 0.1) × 10.sup.5 (1.1 ± 0.1) × 10.sup.5 (1.0 ± 0.1) × 10.sup.5 (7.0 ± 0.1) × 10.sup.4 -

[0107] Referring to FIG. 7 and Table 1, in the case of a thin film with a thickness of 9 nm, the current on/off ratio increased as the oxygen partial pressure increased, and the on-current and mobility tended to decrease. This result is presumed to be due to a decrease in intercalation of tellurium 5p orbitals according to an increase in oxygen 2p orbitals in the valence band maximum (VBM), which is a hole moving path.

[0108] On the other hand, in FIG. 8, the thickness 3.5 nm thin film showed an increased on-current and mobility when the oxygen partial pressure was 9% than when it was 0%. In addition, compared to the 9 nm thin film, the current on/off ratio of the 3.5 nm thin film was excellent about 10 to 10.sup.3 times. In other words, the 3.5 nm thin film showed excellent current on/off ratio due to its thin thickness, and when deposited under the condition of 9 % oxygen partial pressure, it overcame the problem of electric field mobility and on-current degradation due to oxygen injection during the process.

[0109] In addition, comparing the results of FIG. 8 with FIGS. 4, which is the results of electrical transmission characteristics of Experimental Example 2, it was confirmed that the on-current current and the mobility decreased as the input power of sputtering decreased from 50 W to 20 W during the manufacturing of the thin film transistor.

[0110] As above, specific features of the content of the present invention have been described in detail, for those skilled in the art, these specific descriptions are only preferred embodiments, and it is apparent that the scope of the present invention is not limited thereby. Accordingly, the substantial scope of the present invention should be defined by the appended claims and their equivalents.