SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device.

Claims

1. A semiconductor device comprising: a first die; a second die positioned on a top of the first die, wherein the second die is attached using a die attach adhesive or solder; an encapsulant deposited on a top of the semiconductor device, wherein the encapsulant is covering the first die and the second die; and metalized vias within the encapsulant, wherein the metalized vias are arranged to distribute terminals of the first die and terminals of the second die to the top side of the semiconductor device.

2. The semiconductor device as claimed in claim 1, wherein the first die is a GaN HEMT die.

3. The semiconductor device as claimed in claim 1, wherein the second die is a MOSFET die.

4. The semiconductor device as claimed in claim 1, wherein the semiconductor device is a power semiconductor device.

5. The semiconductor device as claimed in claim 2, wherein the second die is a MOSFET die.

6. The semiconductor device as claimed in claim 2, wherein the semiconductor device is a power semiconductor device.

7. The semiconductor device as claimed in claim 3, wherein the semiconductor device is a power semiconductor device.

8. The semiconductor device as claimed in claim 4, wherein the semiconductor device is a power semiconductor device.

9. The semiconductor device as claimed in claim 5, wherein the MOSFET die has a gate terminal and a source terminal; wherein the GaN HEMT die has a gate terminal of the and a drain terminal; and wherein the gate terminal and source terminal of the MOSFET die and the gate terminal and source terminal of the GaN HEMT die are distributed via the metalized vias to the top side of the semiconductor device.

10. The semiconductor device as claimed in claim 5, wherein the semiconductor device is a power semiconductor device.

11. The semiconductor device as claimed in claim 6, wherein the semiconductor device is a power semiconductor device.

12. A method of producing a semiconductor device, the method comprising the steps of: attaching a first die on a film carrier; attaching a second die on the first die using a die attach adhesive or solder; curing the die attach adhesive or solder; encapsulating the first die and the second die with a mold compound or other encapsulant; drilling vias within the encapsulant with a laser to the first die and second die pads; metallizing the vias to make electrical contacts for the first die and for the second die; sintering a metal film on the encapsulant to create terminals of the semiconductor device; and singulating the semiconductor device.

13. The method of manufacturing a semiconductor device as claimed in claim 12, wherein the metal film is a thick Cu film.

14. The method of manufacturing a semiconductor device as claimed in claim 13, wherein the method further comprises a step of depositing an organic solderability preservative on the thick Cu film so to prevent Cu oxidation.

15. The method of manufacturing a semiconductor device as claimed in claim 13, wherein the first die is a GaN HEMT die; and wherein the second die is a MOSFET die.

16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the first die is a GaN HEMT die; and wherein the second die is a MOSFET die.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale.

[0035] Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

[0036] FIGS. 1a and 1b show known semiconductor devices.

[0037] FIG. 2 shows a known semiconductor device.

[0038] FIG. 3 illustrates a semiconductor device according to an embodiment of the disclosure.

[0039] FIG. 4 illustrates a method of manufacturing a semiconductor device according to an embodiment of the disclosure.

[0040] FIG. 5 illustrates a semiconductor device according to an embodiment of the disclosure.

[0041] FIGS. 6a and 6b illustrate semiconductor devices according to embodiments of the disclosure.

DETAILED DESCRIPTION

[0042] FIG. 3 illustrates an embodiment of the present disclosure. A semiconductor package 100 comprises a GaN HEMT die 104. The GaN HEMT comprises an exposed back side 102. A MOSFET die 108 is positioned on the top side of the GaN HEMT die 104, and it is attached to the GaN HEMT die 104 by a die attach adhesive or solder 106. An encapsulant 110 is deposed on the top of the whole semiconductor package, i.e. on the top of both the GaN HEMT die 104 and the MOSFET die 108. Within the encapsulant 110 there are laser drilled and metalized vias 112. The Cu films of the package contact terminals 114 are placed on the top side of these vias 112. In FIG. 3 a top view of the semiconductor package 100 is also shown. The gate terminal of the MOSFET die 120, the source terminal of the MOSFET die 122, the gate terminal of the GaN HEMT die 124, the drain terminal of the GaN HEMT die 126 are visible in said top view of the semiconductor device.

[0043] Although the embodiment shown in FIG. 3 relates to a GaN HEMT die and a MOSFET die, the disclosure also covers all kinds of wide-bandgap semiconductor devices and packages with a cascode operation.

[0044] The disclosure relates to a near chip scale packaging approach enabling KGD stack-die assembly in a power module, which is clearly advantageous compared to an individual bare die assembly or conventional discrete packages.

[0045] The packaging according to the embodiments of the disclosure is suitable for packaging for WBG devices, for example D-mode GaN HEMT, SiC JFET, etc., which devices require cascoding of additional silicon MOSFET for safe normally-off operations.

[0046] The semiconductor devices according to the embodiments of the present disclosures are used in various products, e.g. a power module.

[0047] The exemplary embodiment shown in FIG. 3 is just one of the possibilities covered by the present disclosure. The scope of the disclosure includes all similar embodiments and variations.

[0048] The exemplary embodiment shown in FIG. 3, using the GaN HEMT die for illustration, has the following key features: [0049] A driver die is attached to a power die in a stack-die configuration. [0050] The stack-die assembly is encapsulated, with an exposed back side of the power die, or exposed 5 sides in another design around. [0051] The contact pads of the driver and power die are connected to the package terminals by laser drilled and metallized vias. [0052] The package terminals are formed by Cu sintering or alternative metal sintering, using printing or dispensing method.

[0053] An embodiment of the present disclosure is shown in FIG. 4. A method of manufacturing a semiconductor package comprises steps: [0054] Reference sign 202 in FIG. 4: [0055] attach a GaN HEMT die 104 on a film carrier [0056] attach a MOSFET die 108 on the GaN HEMT die 104 using a die attach adhesive 106 [0057] cure the die attach material [0058] Reference sign 204 in FIG. 4: [0059] encapsulate the stack-die assembly with a mold compound or other encapsulant 110 [0060] Reference sign 206 in FIG. 4: [0061] laser drill vias 112 to the die pads; multiple vias are possible to improve the performance of the semiconductor package [0062] Reference sign 208 in FIG. 4: [0063] metallize 113 the vias, making electrical contacts of the semiconductor package [0064] Reference sign 210 in FIG. 4: [0065] sinter a thick Cu film on the encapsulant 110, which creates the package terminal connections 114 to vias [0066] organic solderability preservative (OSP) can be applied so to prevent Cu oxidation [0067] Reference sign 212 in FIG. 4: [0068] singulate into individual units, e.g. a blade dicing

[0069] According to an embodiment of the present disclosure, within the cascode circuit, the source of the MOSFET die and the gate of the WBG die are connected together. Such a connection can be done on a module substrate surface. This is illustrated in FIG. 5.

[0070] As shown in FIG. 6a, a stack-die package can be flip chip bonded onto a module substrate using known board mounting methods, e.g. soldering, sintering, etc. Compatible contact metallization will be applied.

[0071] Furthermore, as shown in FIG. 6b, a stack-die package can be bonded onto a module substrate using common die attach method. The pads can be connected to substrate using Cu wire bonding.

[0072] According to an embodiment of the disclosure, the gate contact can be relocated to the backside of the wafer, which provides more flexibility in interconnection.

[0073] The disclosure is also applicable for vertical devices, e.g. a SiC FET. In this case the package back side is a drain pad.

[0074] According to an embodiment of the disclosure, instead of a lead frame carrier, a stack-die assembly can be directly processed on wafer level.

[0075] The disclosure also relates to a plurality of stack-die units. A dual stack-die package can be created by final singulation method. The dual stack-die can be further configured for specific application, e.g. a half-bridge, with new terminal pad geometry and connection routing on package top side, formed by new patterns of printed or dispensed Cu sintering materials.

[0076] Particular and preferred aspects of the disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

[0077] The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed disclosure or mitigate against any or all of the problems addressed by the present disclosure. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

[0078] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

[0079] The term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.