SEMICONDUCTOR DEVICE
20220102393 · 2022-03-31
Inventors
Cpc classification
H01L27/1266
ELECTRICITY
H01L27/1251
ELECTRICITY
International classification
Abstract
It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.
Claims
1. A display device comprising: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer; a first insulating layer; and a second insulating layer, wherein the first conductive layer comprises a channel formation region of the first transistor, wherein the second semiconductor layer and the third semiconductor layer are provided in a same layer and comprise an oxide semiconductor, wherein the first insulating layer is provided over the first semiconductor layer and under the second semiconductor layer and the third semiconductor layer, the first insulating layer comprising silicon nitride, wherein the second semiconductor layer comprises a channel formation region of a second transistor, wherein the third semiconductor layer does not comprise a channel formation region of a transistor, wherein a gate electrode of the first transistor is provided over the first semiconductor layer, wherein a gate electrode of the second transistor is provided under the second semiconductor layer, wherein the gate electrode of the first transistor and the gate electrode of the third transistor are in contact with a bottom surface of the first insulating layer, wherein the first insulating layer has a region functioning as a gate-insulating layer of the second transistor, wherein the gate electrode of the first transistor and the gate electrode of the second transistor are in contact with a top surface of the second insulating layer, wherein the second insulating layer has a region functioning as a gate-insulating layer of the first transistor, wherein the third semiconductor layer is in contact with a bottom surface of a first wiring layer electrically connected to the first transistor, wherein a second wiring layer is provided in a same layer as the first wiring layer, and wherein the second wiring layer does not have a region overlapping with a semiconductor layer provided in the same layer as the second semiconductor layer.
2. A display device comprising: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer; a first insulating layer; and a second insulating layer, wherein the first semiconductor layer comprises polycrystalline silicon, wherein the first conductive layer comprises a channel formation region of the first transistor, wherein the second semiconductor layer and the third semiconductor layer are provided in a same layer and comprise an oxide semiconductor, wherein the first insulating layer is provided over the first semiconductor layer and under the second semiconductor layer and the third semiconductor layer, the first insulating layer comprising silicon nitride, wherein the second semiconductor layer comprises a channel formation region of a second transistor, wherein the third semiconductor layer does not comprise a channel formation region of a transistor, wherein a gate electrode of the first transistor is provided over the first semiconductor layer, wherein a gate electrode of the second transistor is provided under the second semiconductor layer, wherein the gate electrode of the first transistor and the gate electrode of the third transistor are in contact with a bottom surface of the first insulating layer, wherein the first insulating layer has a region functioning as a gate-insulating layer of the second transistor, wherein the gate electrode of the first transistor and the gate electrode of the second transistor are in contact with a top surface of the second insulating layer, wherein the second insulating layer has a region functioning as a gate-insulating layer of the first transistor, wherein the third semiconductor layer is in contact with a bottom surface of a first wiring layer electrically connected to the first transistor, wherein a second wiring layer is provided in a same layer as the first wiring layer, and wherein the second wiring layer does not have a region overlapping with a semiconductor layer provided in the same layer as the second semiconductor layer.
3. A display device comprising: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer; a first insulating layer; and a second insulating layer, wherein the first semiconductor layer comprises single-crystal silicon, wherein the first conductive layer comprises a channel formation region of the first transistor, wherein the second semiconductor layer and the third semiconductor layer are provided in a same layer and comprise an oxide semiconductor, wherein the first insulating layer is provided over the first semiconductor layer and under the second semiconductor layer and the third semiconductor layer, the first insulating layer comprising silicon nitride, wherein the second semiconductor layer comprises a channel formation region of a second transistor, wherein the third semiconductor layer does not comprise a channel formation region of a transistor, wherein a gate electrode of the first transistor is provided over the first semiconductor layer, wherein a gate electrode of the second transistor is provided under the second semiconductor layer, wherein the gate electrode of the first transistor and the gate electrode of the third transistor are in contact with a bottom surface of the first insulating layer, wherein the first insulating layer has a region functioning as a gate-insulating layer of the second transistor, wherein the gate electrode of the first transistor and the gate electrode of the second transistor are in contact with a top surface of the second insulating layer, wherein the second insulating layer has a region functioning as a gate-insulating layer of the first transistor, wherein the third semiconductor layer is in contact with a bottom surface of a first wiring layer electrically connected to the first transistor, wherein a second wiring layer is provided in a same layer as the first wiring layer, and wherein the second wiring layer does not have a region overlapping with a semiconductor layer provided in the same layer as the second semiconductor layer.
4. The display device according to claim 1, further comprising: an interlayer insulating layer over the second semiconductor layer and the third semiconductor layer, wherein the interlayer insulating layer has a region functioning as an insulator of a capacitor.
5. The display device according to claim 2, further comprising: an interlayer insulating layer over the second semiconductor layer and the third semiconductor layer, wherein the interlayer insulating layer has a region functioning as an insulator of a capacitor.
6. The display device according to claim 3, further comprising: an interlayer insulating layer over the second semiconductor layer and the third semiconductor layer, wherein the interlayer insulating layer has a region functioning as an insulator of a capacitor.
7. The display device according to claim 1, wherein the gate electrode of the first transistor and the gate electrode of the second transistor are a single-film of an element selected from tantalum, titanium, molybdenum, tungsten, chromium, silicon, aluminium, nickel, carbon, tungsten, platinum, copper, gold, and manganese, a nitride film of any of the elements, an alloy film combining any of the elements, or a silicide film of any of the elements.
8. The display device according to claim 2, wherein the gate electrode of the first transistor and the gate electrode of the second transistor are a single-film of an element selected from tantalum, titanium, molybdenum, tungsten, chromium, silicon, aluminium, nickel, carbon, tungsten, platinum, copper, gold, and manganese, a nitride film of any of the elements, an alloy film combining any of the elements, or a silicide film of any of the elements.
9. The display device according to claim 3, wherein the gate electrode of the first transistor and the gate electrode of the second transistor are a single-film of an element selected from tantalum, titanium, molybdenum, tungsten, chromium, silicon, aluminium, nickel, carbon, tungsten, platinum, copper, gold, and manganese, a nitride film of any of the elements, an alloy film combining any of the elements, or a silicide film of any of the elements.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0091] In the accompanying drawings:
[0092]
[0093]
[0094]
[0095]
[0096]
[0097]
[0098]
[0099]
[0100]
[0101]
[0102]
[0103]
[0104]
[0105]
[0106]
[0107]
[0108]
[0109]
[0110]
[0111]
[0112]
[0113]
[0114]
[0115]
[0116]
[0117]
[0118]
[0119]
[0120]
[0121]
[0122]
[0123]
[0124]
[0125]
[0126]
[0127]
[0128]
[0129]
[0130]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment Modes
[0131] Embodiment Modes of the present invention will be hereinafter described in detail with reference to the accompanying drawings. However, it is easily understood by those skilled in the art that the present invention can be implemented in various different modes, and modes and details of the present invention can be modified in various ways without departing from the purpose and the scope of the present invention. Accordingly, the present invention should not be interpreted as being limited to the description of the embodiment modes. Note that in structures of the present invention described below, reference numerals denoting the same components are used in common in different drawings, and detailed description of the same portions or portions having similar functions is omitted.
Embodiment Mode 1
[0132] All or a part of a semiconductor device or a display device includes a TFT which is formed over a glass substrate in such manner that a silicon layer is separated from a single-crystal substrate and bonded (transferred) to the glass substrate, or a TFT formed over a glass substrate in such a manner that a single-crystal substrate is bonded to the glass substrate and separated from the glass substrate to form a silicon layer over the glass substrate. Not that the TFTs which is formed over a glass substrate in such manner that a silicon layer is separated from a single-crystal substrate and transferred to the glass substrate, or a TFT formed over a glass substrate in such a manner that a single-crystal substrate is bonded to a glass substrate and separated from the glass substrate to transfer a silicon layer which is part of the silicon substrate over the glass substrate are hereinafter referred to as single-crystal TFT.
[0133] Then, a non-single-crystal TFT is also formed at the same time as a single-crystal TFT. Examples of a non-single-crystal includes an amorphous semiconductor, a micro-crystal semiconductor (also referred to as a microcrystalline semiconductor, a semi-amorphous semiconductor, and a nanocrystal semiconductor).
[0134] Next, a manufacturing method is described with reference to drawings.
[0135] As shown in
[0136] Note that it is preferable that an insulating film be provided over the surface of the insulating substrate 101. The insulating film serves as a base film. That is, the insulating film is provided in order to prevent alkali metal such as Na or alkaline earth metals from the inside of the insulating substrate 101 from affecting characteristics of the semiconductor device adversely. The insulating film can have a single-layer structure or a stacked-layer structure of insulating films containing oxygen or nitrogen, such as silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxynitride (SiO.sub.xN.sub.y, x>y), or silicon nitride oxide (SiN.sub.xO.sub.y, x>y). In the case where the insulating film has a two-layer structure, it is preferable that a silicon nitride oxide film be formed for a first layer, and a silicon oxynitride film be formed for a second layer, for example. As another example, in the case where the insulating film has a three-layer structure, it is preferable that a silicon oxynitride film be used as a first insulating film, a silicon nitride oxide film be used as a second insulating film, and a silicon oxynitride film be used as a third insulating film.
[0137] However, it is also possible that the insulating film is not provided over the surface of the insulating substrate 101 without limiting to this.
[0138] Then, a semiconductor layer 102 is provided over the insulating substrate 101 which is provided with an insulating film, or the like. The semiconductor layer 102 may be provided over the entire surface or part of the surface of the insulating substrate 101. The semiconductor layer 102 is preferably single-crystal. However, the present invention is not limited to this. Single-crystal is preferable for an excellent current characteristic and high mobility.
[0139] Note that an arranging method of the semiconductor layer 102, or the like will be described in a different embodiment mode.
[0140] Next as shown in
[0141] The semiconductor layer 102 serves as an active layer of a transistor. However, the semiconductor layer 102 can serves as an electrode of a capacitor element, a resistor element, an active layer of a diode, or the like in some cases without being limited to this.
[0142] Next as shown in
[0143] The insulating layer 103 can be formed by a single-layer structure or a stacked-layer structure of a siloxane resin; a film, of silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxynitride (SiO.sub.xN.sub.y) (x>y), silicon nitride oxide (SiN.sub.xO.sub.y) (x>y), or the like; a film containing carbon, such as a DLC (diamond-like carbon); an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or an insulating film containing oxygen or nitrogen. Note that a siloxane resin corresponds to a resin having Si—O—Si bonds. Siloxane includes a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (such as an alkyl group or aromatic hydrocarbon) is used. Alternatively, a fluoro group, or a fluoro group and an organic group containing at least hydrogen can be used as a substituent.
[0144] A portion of the insulating layer 103 in contact with the semiconductor layer 102 is preferably silicon oxide (SiO.sub.x). A phenomenon of an electron being trapped or hysteresis effect can be prevented by using silicon oxide (SiO.sub.x).
[0145] Next as shown in
[0146] Next as shown in
[0147] The gate electrode 104A forms a transistor 203 together with the semiconductor layer 102 and the insulating layer 103. Since the gate electrode 104A is provided over the semiconductor layer 102, the transistor 203 is a top gate transistor.
[0148] Note that, the transistor 203 can have various structures. For example, the transistor 203 can be a single drain transistor. In this case, since the transistor 203 can be formed in a simple method, there are advantages of low manufacturing cost and high yield. Here, the semiconductor layer 102 has regions of different concentrations of an impurity, a channel formation region, a source region, and a drain region. By controlling the concentration of impurities in this manner, resistivity of the semiconductor layer can be controlled. In the source region and a drain region, an electrical connection state of the semiconductor layer 102 and the conductive film can be closer to ohmic contact. Note that as a method of forming the semiconductor layers each having different amount of impurities as selected, a method can be used in which the semiconductor layer is doped with an impurity using the gate electrode 104A as a mask.
[0149] Alternatively, in the transistor 203, the gate electrode 104A can be tapered at least certain degrees. In this case, since the transistor 203 can be formed in a simple method, there are advantages of low manufacturing cost and high yield. Here, the semiconductor layer 102 has regions of different concentrations of an impurity, a channel formation region, lightly doped drain (LDD) region, a source region and a drain region. By controlling the amount of impurities in this manner, resistivity of the semiconductor layer can be controlled. An electrical connection state of the semiconductor layer 102 and the conductive film connected thereto can be closer to ohmic contact. Moreover, since the transistor includes the LDD region, a high electric field is not easily applied to inside of the transistor, so that deterioration of the element due to hot carriers can be suppressed. Note that as a method of forming the semiconductor layers each including a different amount of an impurity as selected, a method where impurities are added to the semiconductor layer using the gate electrode 104A as a mask can be used. If the gate electrode 104A is tapered at more than certain degrees, the impurity can be added to the semiconductor layer through the gate electrode 104A with a gradient so that the LDD region can be easily formed.
[0150] Alternatively, the transistor 203 can have the gate electrode 104A formed of at least two layers, and a lower gate electrode can be longer than an upper gate electrode. In this case, a shape of the lower and upper gate electrodes can be called a hat shape. When the gate electrode 104A has a hat shape, an LDD region can be formed without addition of a photomask. Note that a structure where the LDD region overlaps with the gate electrode 104A is particularly called a GOLD (gate overlapped LDD) structure. As a method of forming the gate electrode 104A with a hat shape, the following method may be used.
[0151] First, when the gate electrode 104A is patterned, the lower and upper gate electrodes are etched by dry etching so that side surfaces thereof are inclined (tapered). Then, an inclination of the upper gate electrode is processed to be almost perpendicular by anisotropic etching. Thus, the gate electrode is formed such that the cross section is hat-shaped. After that, a channel region, an LDD region, a source region, and a drain region are formed by the semiconductor layer with an impurity element twice.
[0152] Note that a portion of the LDD region which overlaps with the gate electrode 104A is referred to as an Lov region, and a portion of the LDD region which does not overlap with the gate electrode 104A is referred to as an Loff region. The Loff region is highly effective in suppressing an off-current value, whereas it is not very effective in preventing deterioration in an on-current value due to hot carriers by relieving an electric field in the vicinity of the drain. On the other hand, the Lov region works effectively in preventing deterioration in the on-current value by relieving the electric field in the vicinity of the drain; however, it does not work effectively in suppressing the off-current value. Thus, it is preferable to form a transistor having a structure corresponding to characteristics required for each of the various circuits. For example, when the semiconductor device is used for a display device, a transistor having a Loff region is preferably used as a pixel transistor in order to suppress the off-current value. On the other hand, as a transistor in a peripheral circuit, a transistor having an Lov region is preferably used in order to prevent deterioration in the on-current value by relieving the electric field in the vicinity of the drain.
[0153] Alternatively, the transistor 203 can include sidewalls in contact with the side portion of the gate electrode 104A. When the transistor includes the sidewall, a region overlapping with the sidewall can be made to be an LDD region.
[0154] Alternatively, in the transistor 203, the semiconductor layer 102 can be doped using a mask so that an LDD (Loff) region can be formed. Thus, the LDD region can surely be formed, and an off-current value of the transistor can be reduced.
[0155] Alternatively, in the transistor 203, the semiconductor layer can be doped using a mask so that an LDD (Lov) region can be formed. Thus, the LDD region can surely be formed, and deterioration in an on-current value can be prevented by relieving the electric field in the vicinity of the drain of the transistor.
[0156] Note that the conductive layer 104 can be processed into a conductive film having various functions without being limited to the gate electrode. For example, various functions of the conductive film include a wiring or an electrode such as a wiring for forming a storage capacitor, a wiring for forming a scan line, a wiring for connecting circuits, or the like.
[0157] Next, as shown in
[0158] The insulating layer 201 can be formed by a single-layer structure or a stacked-layer structure of a siloxane resin; a film, of silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxynitride (SiO.sub.xN.sub.y) (x>y), silicon nitride oxide (SiN.sub.xO.sub.y) (x>y), or the like; a film containing carbon, such as a DLC (diamond-like carbon); an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or an insulating film containing oxygen or nitrogen. Note that a siloxane resin corresponds to a resin having Si—O—Si bonds. Siloxane includes a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (such as an alkyl group or aromatic hydrocarbon) is used. Alternatively, a fluoro group, or a fluoro group and an organic group containing at least hydrogen can be used as a substituent.
[0159] It is preferable that a portion of the insulating layer 201 in contact with a semiconductor layer 202, which is provided later, be silicon nitride (SiN.sub.x). The semiconductor layer 202 includes hydrogen in some case. In that case, reacting the hydrogen included in the semiconductor layer 202 and the insulating layer 201 can be prevented by using silicon nitride (SiN.sub.x) as the insulating layer 201.
[0160] Next, as shown in
[0161] The crystallinity of the semiconductor layer 202 is preferably amorphous, micro-crystal (also referred to as microcrystal, semi-amorphous, nanocrystal, or the like).
[0162] Next as shown in
[0163] In this case, the patterned semiconductor layer 202A serves as an active layer of a transistor. However, the present invention is not limited to this. The semiconductor layer can also serve as an interlayer film. In other words, intersection capacitance of the wiring can be reduced by providing a semiconductor layer, and disconnection of the wiring can be reduced by reducing a bumps. For example, a semiconductor layer 202B and a semiconductor layer 202C serve as interlayer films.
[0164] Next as shown in
[0165] The conductive layer 104 and the conductive layer 301 can have a single-layer structure of a conductive film or a stacked-layer structure of two or three conductive films. A conductive film can be used as a material of the conductive layer 104. For example, a single film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), aluminum (Al), nickel (Ni), carbon (C), tungsten (W), platinum (Pt), copper (Cu), tantalum (Ta), gold (Au), or manganese (Mn); a nitride film of the aforementioned element (typically, a tantalum nitride film, a tungsten nitride film, or a titanium nitride film); an alloy film in which the aforementioned elements are combined (typically, a Mo—W alloy or a Mo—Ta alloy); a silicide film of the aforementioned element (typically, a tungsten silicide film or a titanium silicide film); or the like can be used. Alternatively, as an alloy containing a plurality of such elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, or the like can be used. Note that the aforementioned single-element film, a nitride film, an alloy film, a silicide film or the like can have a single-layer structure or be combined to have a stacked-layer structure. For example, in the case of providing a stacked layer structure, a structure in which Al is provided between Mo and Ti can be employed. Thus, resistance of Al to heat or chemical reaction can be improved. In the case of silicon, it is preferable to include much impurity (P-type impurities or N-type impurities) to improve conductivity.
[0166] Next as shown in
[0167] Next as shown in
[0168] The semiconductor layer 202A can be formed using an amorphous semiconductor, a microcrystalline semiconductor, or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor layer may be used. SAS has an intermediate structure between an amorphous and a crystalline structure (including a single-crystal and a polycrystalline), and a third condition that is stable in term of free energy. Moreover, SAS includes a crystalline region with a short-range order and lattice distortion. A crystalline region of 0.5 to 20 nm can be observed at least in part of a film. When silicon is contained as a main component, Raman spectrum shifts to a wave number side lower than 520 cm.sup.−1. The diffraction peaks of (111) and (220) which are thought to be derived from the silicon crystalline lattice are observed by X-ray diffraction. SAS contains hydrogen or halogen of at least 1 atomic percent or more to compensate dangling bonds. SAS is formed by glow discharge decomposition (plasma CVD) of a material gas. As the material gas, Si.sub.2H.sub.6, SiH.sub.2Cl.sub.2, SiHCl.sub.3, SiCl.sub.4, SiF.sub.4, or the like as well as SiH.sub.4 can be used. Alternatively, GeF.sub.4 may be mixed. The material gas may be diluted with H.sub.2, or H.sub.2 and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. A dilution ratio is in the range of 2 to 1000 times. Pressure is in the range of approximately 0.1 to 133 Pa, and a power supply frequency is 1 to 120 MHz, preferably 13 to 60 MHz. A substrate heating temperature may be 300° C. or lower. A concentration of impurities in atmospheric components such as oxygen, nitrogen, and carbon is preferably 1×10.sup.20 cm.sup.−1 or less as impurity elements in the film. In particular, an oxygen concentration is 5×10.sup.19/cm.sup.3 or less, preferably 1×10.sup.19/cm.sup.3 or less. Here, an amorphous semiconductor layer is formed using a material containing silicon (Si) as its main component (e.g., Si.sub.xGe.sub.1-x) by a sputtering method, an LPCVD method, or a plasma CVD method. Then, the amorphous semiconductor layer is crystallized by a crystallization method such as a laser crystallization method, a thermal crystallization method using RTA or an annealing furnace, or a thermal crystallization method using a metal element which promotes crystallization.
[0169] Next as shown in
[0170] The insulating layer 401 can be formed by a single-layer structure or a stacked-layer structure of a siloxane resin; a film, of silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxynitride (SiO.sub.xN.sub.y) (x>y), silicon nitride oxide (SiN.sub.xO.sub.y) (x>y), or the like; a film containing carbon, such as a DLC (diamond-like carbon); an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or an insulating film containing oxygen or nitrogen. Note that a siloxane resin corresponds to a resin having Si—O—Si bonds. Siloxane includes a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (such as an alkyl group or aromatic hydrocarbon) is used. Alternatively, a fluoro group, or a fluoro group and an organic group containing at least hydrogen can be used as a substituent.
[0171] It is preferable that a portion of the insulating layer 401 in contact with the semiconductor layer 202, which is provided, be silicon nitride (SiN.sub.x). The semiconductor layer 202 includes hydrogen in some cases. In that case, reacting the hydrogen included in the semiconductor layer 202 and the insulating layer 401 can be prevented by using silicon nitride (SiN.sub.x) as the insulating layer 401.
[0172] Note that the insulating layer 401 preferably includes silicon nitride (SiN.sub.x). Silicon nitride (SiN.sub.x) has a function of blocking impurities. Therefore, a transistor can be protected from impurities.
[0173] Note that the insulating layer 401 preferably includes an organic film. Thus, the surface of the insulating layer 401 can be flattened. When the surface of the insulating layer 401 is flat, a pixel electrode formed thereover can also be flattened. When a pixel electrode becomes flat, a display device can be made appropriately.
[0174] Next as shown in
[0175] Next as shown in
[0176] The conductive layer 601 can have a single-layer structure of a conductive film or a stacked-layer structure of two or three conductive films. Further, the conductive layer 601 preferably includes a region which has high transmittivity of light and is light-transmitting or close to light-transmitting. Thus, the conductive layer 601 can serve as a pixel electrode of a light transmitting region. In addition, the conductive layer 601 preferably includes a region of high reflectivity. Thus, the conductive layer 601 can serve as a pixel electrode of a reflective region.
[0177] Note that it is preferable that the conductive layer 601 is a film including ITO, IZO, ZnO, or the like.
[0178] Next as shown in
[0179] In this case, a patterned conductive layer 601A serves as a pixel electrode as a patterned conductive layer. However, the present invention is not limited this. A conductive layer 601B and a conductive layer 601C serve as a wiring. The conductive layer 601B has a function of connecting the conductive layer 301C and the semiconductor layer 102. The conductive layer 601C has a function of connecting the conductive layer 301D and the semiconductor layer 102.
[0180] After that, a display device is completed through various steps in accordance with the kind of display devices. For example, an orientation film is formed, and liquid crystal is provided between a counter substrate having a color filter and the orientation film. Alternatively, an organic electroluminescence material is provided over the conductive layer 601A, and a cathode is provided thereover.
[0181] Note that, in
[0182] Note that in a similar manner to the conductive layer 301C, the conductive layer 301D, and the conductive layer 301F, a semiconductor layer may be provided under the conductive layers, or a semiconductor layer is not necessarily provided under the conductive layer 301E as shown in
[0183] Note that, in
[0184] Note that, in
[0185] Note that, in
[0186] Note that, in
[0187] The structures and manufacturing methods of transistors have been described above. Note that a wiring, an electrode, a conductive layer, a conductive film, a terminal, a via, a plug, or the like is preferably formed of one element or a plurality of elements of a group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), and oxygen (O), or a compound or an alloy material including one element or a plurality of such elements (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide to which silicon oxide is added (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al—Nd), magnesium silver (Mg—Ag), or molybdenum neodymium (Mo—Nb)). Alternatively, a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like is preferably formed of a substance or the like obtained by combining such compounds. Alternatively, such a wiring, an electrode, a conductive layer, a conductive film, a terminal are preferably formed to have a substance including a compound of silicon and one or more of the elements selected from the above group (silicide) (e.g., aluminum silicon, molybdenum silicon, nickel silicide); or a compound of nitrogen and one or more of the elements selected from the group (e.g., titanium nitride, tantalum nitride, or molybdenum nitride).
[0188] Note that silicon (Si) may include an n-type impurity (such as phosphorus) or a p-type impurity (such as boron). When silicon includes such impurity, conductivity is improved, so that the silicon can behave in a similar manner to a normal conductor. Thus, such silicon can be utilized easily as wirings or electrodes.
[0189] Silicon can be various types of silicon such as single-crystalline silicon, polycrystalline silicon, or microcrystalline silicon. Alternatively, silicon having no crystallinity such as amorphous silicon can be used. By using single-crystalline silicon or polycrystalline silicon, resistance of a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like can be reduced. By using amorphous silicon or microcrystalline silicon, a wiring or the like can be formed by a simple process.
[0190] Note that aluminum or silver has high conductivity, and thus can reduce a signal delay. Since aluminum or silver can be easily etched, aluminum or silver can be easily patterned and processed minutely.
[0191] Note that copper has high conductivity; therefore, signal delay can be decreased by using copper. In using copper, a stacked structure is preferably employed to enhance adhesiveness.
[0192] Molybdenum or titanium is preferable since molybdenum or titanium does not cause defects even if molybdenum or titanium is in contact with an oxide semiconductor (e.g., ITO or IZO) or silicon. Further, molybdenum or titanium is easily etched and has high heat resistance.
[0193] Tungsten is preferable since it has an advantage such as high heat resistance.
[0194] Neodymium is preferable because it has an advantage such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, heat resistance is improved, and thus, hillocks of aluminum are not easily generated.
[0195] Silicon is preferable since it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.
[0196] Note that ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (SnO), or cadmium tin oxide (CTO) can be used for a portion which transmits light because it has a light-transmitting property. For example, it can be used for a pixel electrode or a common electrode.
[0197] IZO is preferable since it is easily etched and processed. In etching IZO, residues of IZO are hardly left. Thus, when a pixel electrode is formed using IZO, defects (such as short-circuiting or orientation disorder) of a liquid crystal element or a light-emitting element can be reduced.
[0198] A wiring, an electrode, a conductive layer, a conductive film, a terminal, a via, a plug, or the like may have a single-layer structure or a multi-layer structure. By employing a single-layer structure, a manufacturing process of such a wiring, an electrode, a conductive layer, a conductive film, or a terminal can be simplified; the number of days for a process can be reduced; and cost can be reduced. Alternatively, by employing a multilayer structure, an advantage of each material is utilized and a disadvantage thereof is reduced so that a wiring, an electrode, or the like with high performance can be formed. For example, a low-resistant material (e.g., aluminum) is included in a multilayer structure, thereby reducing the resistance of such wirings. As another example, when a low heat-resistant material is interposed between high heat-resistant materials to form a stacked-layer structure, heat resistance of wirings or electrodes can be increased, utilizing advantages of a low heat-resistance material. For example, a layer including aluminum is preferably interposed between layers including molybdenum, titanium, neodymium, or the like as a stacked-layer structure.
[0199] If wirings or electrodes are in direct contact with each other, an adverse effect is caused to each other in some cases. For example, a material of a wiring, an electrode, or the like is mixed into a material of the other wiring, electrode, or the like, and properties of the materials are changed, so that the original object cannot be achieved. As another example, when a high-resistant portion is formed, a problem may occur, so that the high-resistant portion cannot be normally formed. In such cases, a reactive material is preferably interposed by or covered with a material which does not react easily to form a stacked-layer structure. For example, when ITO is connected to aluminum, titanium, molybdenum, or an alloy of neodymium is preferably disposed between the ITO and the aluminum. As another example, when silicon is connected to aluminum, titanium, molybdenum, or an alloy of neodymium is preferably disposed between the silicon and the aluminum.
[0200] Note that the term “wiring” indicates a portion including a conductor. The wiring may be extended in a long linear shape or may be short. Therefore, electrodes are included in such wirings.
[0201] Note that a carbon nanotube may be used for a wiring, an electrode, a conductive layer, a terminal, a via, a plug, or the like. Since a carbon nanotube has a light-transmitting property, it can be used for a portion which transmits light. For example, it can be used for a pixel electrode or a common electrode.
[0202] A cross-sectional view has been shown. Next, an example of a layout pattern is shown.
[0203] Note that a circuit shown in
[0204] In this manner, a circuit configured by the transistor 203 has high mobility and high current supply capacity; thus, it is preferable to be used as a driver circuit. On the other hand, since mobility of the transistor 303 is not high and the transistor 303 can be manufactured in a large size, it is preferable to be used as a pixel circuit.
[0205] Although this embodiment mode is described with reference to various drawings, the contents (or may be part of the contents) described in each drawing can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in another drawing. Further, much more drawings can be formed by combining each part in the above-described drawings with another part.
[0206] Similarly, the contents (or a part thereof) described in each drawing of this embodiment mode can be freely applied to, combined with, or replaced with the contents (or a part thereof) described in a drawing in another embodiment mode. Further, much more drawings can be formed by combining each part in the drawings in this embodiment mode with part of another embodiment mode.
[0207] Note that this embodiment mode has described just examples of embodying, slightly transforming, modifying, improving, describing in detail, or applying the contents (or part of the contents) described in other embodiment modes, an example of related part thereof, or the like. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.
Embodiment Mode 2
[0208] Next, an arranging method of the semiconductor layer used for the single-crystal TFT is described.
[0209]
[0210] Between the base substrate 9200 and the SOI layer 9202 described above, a bonding layer 9204 which has a smooth surface and forms a hydrophilic surface is provided. A silicon oxide film is suitable for the bonding layer 9204. In particular, a silicon oxide film formed by a chemical vapor deposition method using an organic silane gas is preferable. As an organic silane gas, a silicon-containing compound such as tetraethoxysilane (TEOS) (chemical formula: Si(OC.sub.2H.sub.5).sub.4), tetramethylsilane (TMS), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (chemical formula: SiH(OC.sub.2H.sub.5).sub.3), or trisdimethylaminosilane (chemical formula: SiH(N(CH.sub.3).sub.2).sub.3) can be used.
[0211] The bonding layer 9204 which has a smooth surface and forms a hydrophilic surface is provided with a thickness of 5 to 500 nm. With such a thickness, roughness of a surface on which the bonding layer 9204 is formed can be smoothed and smoothness of a growth surface of the film can be ensured. In addition, distortion between the base substrate 9200 and the SOI layer 9202 which are bonded to each other can be reduced. The base substrate 9200 may be provided with a similar silicon oxide film. That is, when the SOI layer 9202 is bonded to the base substrate 9200 which is a substrate having an insulating surface or an insulating substrate, the base substrate 9200 and the SOI layer 9202 can be firmly bonded to each other when the bonding layer 9204 formed of a silicon oxide film which is preferably formed using organic silane as a material is provided on either one or both surfaces of the base substrate 9200 and the SOI layer 9202 which are to be bonded.
[0212]
[0213]
[0214] Note that here, a silicon oxynitride film corresponds to a film which contains more oxygen than nitrogen, and for example, includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 50 to 70 at. %, 0.5 to 15 at. %, 25 to 35 at. %, and 0.1 to 10 at. %, respectively. In addition, a silicon nitride oxide film corresponds to a film which contains more nitrogen than oxygen and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 5 to 30 at. %, 20 to 55 at. %, 25 to 35 at. %, and 10 to 25 at. %, respectively. Note that the above range is a measurement result using Rutherford backscattering spectrometry (RBS) and hydrogen forward scattering (HFS). Note that the content percentages of the component atoms is not beyond 100 at. %
[0215]
[0216] A method for manufacturing such an SOI substrate is described with reference to
[0217] A semiconductor substrate 9201 shown in
[0218] In the case of irradiation with ions at a high dose, the surface of the semiconductor substrate 9201 is roughened in some cases. Therefore, a protective film against irradiation with ions, such as a silicon nitride film, a silicon nitride oxide film, or the like with a thickness of 50 to 200 nm may be provided on a surface with which ions are irradiated.
[0219] Next, as shown in
[0220]
[0221] In order to form a favorable bond, the surfaces may be activated. For example, the surfaces which are to form a bond are irradiated with an atomic beam or an ion beam. When an atomic beam or an ion beam is used, an inert gas neutral atom beam or inert gas ion beam of argon or the like can be used. Alternatively, plasma irradiation or radical treatment is performed. With such a surface treatment, a bond between different kinds of materials can be easily formed even at a temperature of 200 to 400° C.
[0222] After the base substrate 9200 and the semiconductor substrate 9201 are bonded to each other with the bonding layer 9204 interposed therebetween, heat treatment or pressure treatment is preferably performed. When heat treatment or pressure treatment is performed, bonding strength can be increased. Temperature of heat treatment is preferably lower than or equal to the upper temperature limit of the base substrate 9200. Pressure treatment is performed so that pressure is applied in a perpendicular direction to the bonded surface, in consideration of pressure resistance of the base substrate 9200 and the semiconductor substrate 9201.
[0223] In
[0224]
[0225]
[0226] After that, as shown in
[0227] In this manner, in accordance with this mode, even if a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate or the like, is used as the base substrate 9200, the SOI layer 9202 having strong adhesiveness of a bonded portion can be obtained. As the base substrate 9200, various glass substrates which are used in the electronics industry and are referred to as non-alkali glass substrates, such as aluminosilicate glass substrates, aluminoborosilicate glass substrates, and barium borosilicate glass substrates can be used. That is, a single-crystal semiconductor layer can be formed over a substrate which is longer than one meter on a side. When such a large-area substrate is used, not only a display device such as a liquid crystal display but also a semiconductor integrated circuit can be manufactured.
[0228] Note that a manufacturing method and an arrangement method of the semiconductor layer are not limited to this. An amorphous silicon film can be formed over an insulating substrate by a CVD method, or the like, and amorphous silicon film is crystallized by irradiated with laser (linear laser, continuous solid oscillation laser, or the like) or by applying heat or the like, so that polycrystalline silicon or microcrystalline silicon can be manufactured.
[0229] Although this embodiment mode is described with reference to various drawings, the contents (or may be part of the contents) described in each drawing can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in another drawing. Further, much more drawings can be formed by combining each part in the above-described drawings with another part.
[0230] Similarly, the contents (or may be part of the contents) described in each drawing of this embodiment mode can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in a drawing in another embodiment mode. Further, much more drawings can be formed by combining each part in the drawings in this embodiment mode with part of another embodiment mode. Note that this embodiment mode has described just examples of embodying, slightly transforming, modifying, improving, describing in detail, or applying the contents (or part of the contents) described in other embodiment modes, an example of related part thereof, or the like. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.
Embodiment Mode 3
[0231] In this embodiment mode, a peripheral portion of a liquid crystal panel is described.
[0232]
[0233] The backlight unit 5201 includes a diffusion plate 5202, a light guide plate 5203, a reflection plate 5204, a lamp reflector 5205, and a light source 5206.
[0234] The light source 5206 has a function of emitting light as necessary. For example, as the light source 5206, a cold cathode fluorescent lamp, a hot cathode fluorescent lamp, a light-emitting diode, an inorganic EL element, an organic EL element, or the like is used.
[0235]
[0236] A backlight unit 5211 shown in
[0237] A backlight unit 5221 shown in
[0238] A backlight unit 5231 shown in
[0239] A backlight unit 5241 shown in
[0240]
[0241] A backlight unit 5290 includes a diffusion plate 5291, a light-shielding plate 5292, a lamp reflector 5293, a light source 5294, and a liquid crystal panel 5295.
[0242] The light source 5294 has a function of emitting light as necessary. For example, as the light source 5294, a cold cathode fluorescent lamp, a hot cathode fluorescent lamp, a light-emitting diode, an inorganic EL element, an organic EL element, or the like is used.
[0243]
[0244] A polarizing film 5250 includes a protective film 5251, a substrate film 5252, a PVA polarizing film 5253, a substrate film 5254, an adhesive layer 5255, and a mold release film 5256.
[0245] When the PVA polarizing film 5253 is sandwiched by films to be base materials (the substrate film 5252 and the substrate film 5254) from both sides, reliability can be improved. Note that the PVA polarizing film 5253 may be sandwiched by triacetylcellulose (TAC) films with high light-transmitting properties and high durability. Note that each of the substrate films and the TAC films function as protective films of polarizer included in the PVA polarizing film 5253.
[0246] One of the substrate films (the substrate film 5254) is provided with the adhesive layer 5255 which is to be attached to a glass substrate of the liquid crystal panel. Note that the adhesive layer 5255 is formed by applying an adhesive to one of the substrate films (the substrate film 5254). The mold release film 5256 (a separate film) is provided to the adhesive layer 5255.
[0247] The protective film 5251 is provided to the other of the substrates films (the substrate film 5252).
[0248] A hard coating scattering layer (an anti-glare layer) may be provided on a surface of the polarizing film 5250. Since the surface of the hard coating scattering layer has minute unevenness formed by AG treatment and has an anti-glare function which scatters external light, reflection of external light in the liquid crystal panel can be prevented. Surface reflection can also be prevented.
[0249] Note that a treatment in which plurality of optical thin film layers having different refractive indexes are layered (also referred to as anti-reflection treatment or AR treatment) may be performed on the surface of the polarizing film 5250. The plurality of layered optical thin film layers having different refractive indexes can reduce reflectivity on the surface by an interference effect of light.
[0250]
[0251] In a pixel portion 5265, signal lines 5269 which are extended from a signal line driver circuit 5263 are provided. In addition, in the pixel portion 5265, scan lines 5260 which are extended from a scan line driver circuit 5264 are also provided. In addition, a plurality of pixels are arranged in matrix in cross regions of the signal lines 5269 and the scan lines 5260. Note that each of the plurality of pixels includes a switching element. Therefore, voltage for controlling inclination of liquid crystal molecules can be separately input to each of the plurality of pixels. A structure in which a switching element is provided in each cross region in this manner is referred to as an active matrix type. Note that the present invention is not limited to such an active matrix type and a structure of a passive matrix type may be used. Since the passive matrix type does not have a switching element in each pixel, a process is simple.
[0252] A driver circuit portion 5268 includes a control circuit 5262, the signal line driver circuit 5263, and the scan line driver circuit 5264. An image signal 5261 is input to the control circuit 5262. The signal line driver circuit 5263 and the scan line driver circuit 5264 are controlled by the control circuit 5262 in accordance with this image signal 5261. Therefore, the control circuit 5262 inputs a control signal to each of the signal line driver circuit 5263 and the scan line driver circuit 5264. Then, in accordance with this control signal, the signal line driver circuit 5263 inputs a video signal to each of the signal lines 5269 and the scan line driver circuit 5264 inputs a scan signal to each of the scan lines 5260. Then, the switching element included in the pixel is selected in accordance with the scan signal and the video signal is input to a pixel electrode of the pixel.
[0253] Note that the control circuit 5262 also controls a power source 5267 in accordance with the image signal 5261. The power source 5267 includes a unit for supplying power to a lighting unit 5266. As the lighting unit 5266, an edge-light type backlight unit or a direct-type backlight unit can be used. Note that a front light may be used as the lighting unit 5266. A front light corresponds to a plate-like lighting unit including a luminous body and a light conducting body, which is attached to the front surface side of a pixel portion and illuminates the whole area. By using such a lighting unit, the pixel portion can be uniformly illuminated at low power consumption.
[0254] As shown in
[0255] As shown in
[0256] Note that in this embodiment mode, various liquid crystal panels can be used for the liquid crystal panel. For example, a structure in which a liquid crystal layer is sealed between two substrates can be used as the liquid crystal panel. A transistor, a capacitor, a pixel electrode, an alignment film, or the like is formed over one of the substrates. A polarizing plate, a retardation plate, or a prism sheet may be provided on the surface opposite to a top surface of the one of the substrates. A color filter, a black matrix, a counter electrode, an alignment film, or the like is provided on the other of the substrates. A polarizing plate or a retardation plate may be provided on the surface opposite to a top surface of the other of the substrates. The color filter and the black matrix may be formed over the top surface of the one of the substrates. Note that three-dimensional display can be performed by providing a slit (a grid) on the top surface side of the one of the substrates or the surface opposite to the top surface side of the one of the substrates.
[0257] Each of the polarizing plate, the retardation plate, and the prism sheet can be provided between the two substrates. Alternatively, each of the polarizing plate, the retardation plate, and the prism sheet can be integrated with one of the two substrates.
[0258] Note that although this embodiment mode is described with reference to various drawings, the contents (or may be part of the contents) described in each drawing can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in another drawing. Further, even more drawings can be formed by combining each part with another part in the above-described drawings.
[0259] Similarly, the contents (or may be part of the contents) described in each drawing of this embodiment mode can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in a drawing in another embodiment mode. Further, even more drawings can be formed by combining each part with part of another embodiment mode in the drawings of this embodiment mode.
[0260] This embodiment mode shows an example of an embodied case of the contents (or may be part of the contents) described in other embodiment modes, an example of slight transformation thereof, an example of partial modification thereof, an example of improvement thereof, an example of detailed description thereof, an application example thereof, an example of related part thereof, or the like. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.
Embodiment Mode 4
[0261] In this embodiment mode, a pixel structure and an operation of a pixel which can be applied to a liquid crystal display device are described.
[0262] In this embodiment mode, as an operation mode of a liquid crystal element, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optical compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or the like can be used.
[0263]
[0264] A pixel 5600 includes a transistor 5601, a liquid crystal element 5602, and a capacitor 5603. A gate of the transistor 5601 is connected to a wiring 5605. A first terminal of the transistor 5601 is connected to a wiring 5604. A second electrode of the transistor 5601 is connected to a first electrode of the liquid crystal element 5602 and a first electrode of the capacitor 5603. A second electrode of the liquid crystal element 5602 corresponds to a counter electrode 5607. A second electrode of the capacitor 5603 is connected to a wiring 5606.
[0265] The wiring 5604 functions as a signal line. The wiring 5605 functions as a scan line. The wiring 5606 functions as a capacitor line. The transistor 5601 functions as a switch. The capacitor 5603 functions as a storage capacitor.
[0266] It is acceptable as long as the transistor 5601 functions as a switch, and the transistor 5601 may be either a P-channel transistor or an N-channel transistor.
[0267]
[0268] A pixel 5610 includes a transistor 5611, a liquid crystal element 5612, and a capacitor 5613. A gate of the transistor 5611 is connected to a wiring 5615. A first terminal of the transistor 5611 is connected to a wiring 5614. A second terminal of the transistor 5611 is connected to a first electrode of the liquid crystal element 5612 and a first electrode of the capacitor 5613. A second electrode of the liquid crystal element 5612 is connected to a wiring 5616. A second electrode of the capacitor 5613 is connected to the wiring 5616.
[0269] The wiring 5614 functions as a signal line. The wiring 5615 functions as a scan line. The wiring 5616 functions as a capacitor line. The transistor 5611 functions as a switch. The capacitor 5613 functions as a storage capacitor.
[0270] It is acceptable as long as the transistor 5611 functions as a switch, and the transistor 5611 may be a P-channel transistor or an N-channel transistor.
[0271]
[0272]
[0273] A pixel 5620 includes a transistor 5621, a liquid crystal element 5622, and a capacitor 5623. A gate of the transistor 5621 is connected to a wiring 5625. A first terminal of the transistor 5621 is connected to a wiring 5624. A second terminal of the transistor 5621 is connected to a first electrode of the liquid crystal element 5622 and a first electrode of the capacitor 5623. A second electrode of the liquid crystal element 5622 corresponds to a counter electrode 5627. A second electrode of the capacitor 5623 is connected to a wiring which is the same as a wiring connected to a gate of a transistor of the previous row.
[0274] A pixel 5630 includes a transistor 5631, a liquid crystal element 5632, and a capacitor 5633. A gate of the transistor 5631 is connected to a wiring 5635. A first terminal of the transistor 5631 is connected to the wiring 5624. A second terminal of the transistor 5631 is connected to a first electrode of the liquid crystal element 5632 and a first electrode of the capacitor 5633. A second electrode of the liquid crystal element 5632 corresponds to a counter electrode 5637. A second electrode of the capacitor 5633 is connected to the wiring which is the same as the wiring connected to the gate of the transistor of the previous row (the wiring 5625).
[0275] The wiring 5624 functions as a signal line. The wiring 5625 functions as a scan line of the N-th row. The wiring 5625 also functions as a scan line of the (N+1)th row. The transistor 5621 functions as a switch. The capacitor 5623 functions as a storage capacitor.
[0276] The wiring 5635 functions as a scan line of the (N+1)th row. The wiring 5635 also functions as a scan line of the (N+2)th row. The transistor 5631 functions as a switch. The capacitor 5633 functions as a storage capacitor.
[0277] It is acceptable as long as each of the transistor 5621 and the transistor 5631 functions as a switch, and each of the transistor 5621 and the transistor 5631 may be either a P-channel transistor or an N-channel transistor.
[0278]
[0279] A pixel 5659 includes a subpixel 5640 and a subpixel 5650. Although the case in which the pixel 5659 includes two subpixels is described, the pixel 5659 may include three or more subpixels.
[0280] The subpixel 5640 includes a transistor 5641, a liquid crystal element 5642, and a capacitor 5643. A gate of the transistor 5641 is connected to a wiring 5645. A first terminal of the transistor 5641 is connected to a wiring 5644. A second terminal of the transistor 5641 is connected to a first electrode of the liquid crystal element 5642 and a first electrode of the capacitor 5643. A second electrode of the liquid crystal element 5642 corresponds to a counter electrode 5647. A second electrode of the capacitor 5643 is connected to a wiring 5646.
[0281] The subpixel 5650 includes a transistor 5651, a liquid crystal element 5652, and a capacitor 5653. A gate of the transistor 5651 is connected to a wiring 5655. A first terminal of the transistor 5651 is connected to the wiring 5644. A second terminal of the transistor 5651 is connected to a first electrode of the liquid crystal element 5652 and a first electrode of the capacitor 5653. A second electrode of the liquid crystal element 5652 corresponds to a counter electrode 5657. A second electrode of the capacitor 5653 is connected to a wiring 5646.
[0282] The wiring 5644 functions as a signal line. The wiring 5645 functions as a scan line. The wiring 5655 functions as a signal line. The wiring 5646 functions as a capacitor line. Each of the transistor 5641 and the transistor 5651 functions as a switch. Each of the capacitor 5643 and the capacitor 5653 functions as a storage capacitor.
[0283] It is acceptable as long as each of the transistor 5641 and the transistor 5651 functions as a switch, and each of the transistor 5641 and the transistor 5651 may be either a P-channel transistor or an N-channel transistor.
[0284] A video signal input to the subpixel 5640 may be a value which is different from that of a video signal input to the subpixel 5650. In this case, the viewing angle can be widened because alignment of liquid crystal molecules of the liquid crystal element 5642 and alignment of liquid crystal molecules of the liquid crystal element 5652 can be varied from each other.
[0285] Note that although this embodiment mode is described with reference to various drawings, the contents (or may be part of the contents) described in each drawing can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in another drawing. Further, even more drawings can be formed by combining each part with another part in the above-described drawings.
[0286] Similarly, the contents (or may be part of the contents) described in each drawing of this embodiment mode can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in a drawing in another embodiment mode. Further, even more drawings can be formed by combining each part with part of another embodiment mode in the drawings of this embodiment mode.
[0287] This embodiment mode shows an example of an embodied case of the contents (or may be part of the contents) described in other embodiment modes, an example of slight transformation thereof, an example of partial modification thereof, an example of improvement thereof, an example of detailed description thereof, an application example thereof, an example of related part thereof, or the like. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.
Embodiment Mode 5
[0288] In this embodiment mode, a pixel structure of a display device is described. In particular, a pixel structure of a display device using an organic EL element is described.
[0289]
[0290]
[0291] A gate electrode of the first transistor 6005 is electrically connected to the first wiring 6006. One of a source electrode and a drain electrode of the first transistor 6005 is electrically connected to the second wiring 6007. The other of the source electrode and the drain electrode of the first transistor 6005 is electrically connected to a gate electrode of the second transistor 6008 and one electrode of the capacitor 6013. Note that the gate electrode of the first transistor 6005 includes a plurality of gate electrodes. Accordingly, leakage current in the off state of the first transistor 6005 can be reduced.
[0292] One of a source electrode and a drain electrode of the second transistor 6008 is electrically connected to the third wiring 6011, and the other of the source electrode and the drain electrode of the second transistor 6008 is electrically connected to the pixel electrode 6015. Accordingly, current flowing to the pixel electrode 6015 can be controlled by the second transistor 6008.
[0293] The organic conductive film 6017 is provided over the pixel electrode 6015, and the organic thin film 6018 (an organic compound layer) is provided thereover. The counter electrode 6012 is provided over the organic thin film 6018 (the organic compound layer). Note that the counter electrode 6012 may be formed over the entire surface to be connected to all the pixels in common, or may be patterned using a shadow mask or the like.
[0294] Light emitted from the organic thin film 6018 (the organic compound layer) is transmitted through either the pixel electrode 6015 or the counter electrode 6012.
[0295] In
[0296] In the case of bottom emission, it is preferable that the pixel electrode 6015 be formed of a light-transmitting conductive film. On the other hand, in the case of top emission, it is preferable that the counter electrode 6012 be formed of a light-transmitting conductive film.
[0297] In a light-emitting device for color display, EL elements having respective light emission colors of RGB may be separately formed, or an EL element with a single color may be applied over an entire surface and light emission of RGB can be obtained by using a color filter.
[0298] Note that the structures shown in
[0299] Note that although this embodiment mode is described with reference to various drawings, the contents (or may be part of the contents) described in each drawing can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in another drawing. Further, even more drawings can be formed by combining each part with another part in the above-described drawings.
[0300] Similarly, the contents (or may be part of the contents) described in each drawing of this embodiment mode can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in a drawing in another embodiment mode. Further, even more drawings can be formed by combining each part with part of another embodiment mode in the drawings of this embodiment mode.
[0301] This embodiment mode shows an example of an embodied case of the contents (or may be part of the contents) described in other embodiment modes, an example of slight transformation thereof, an example of partial modification thereof, an example of improvement thereof, an example of detailed description thereof, an application example thereof, an example of related part thereof, or the like. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.
Embodiment Mode 6
[0302] In this embodiment mode, examples of electronic devices are described.
[0303]
[0304]
[0305] Among the signals received by the tuner 9611, the audio signal is transmitted to an audio signal amplifier circuit 9615, and output thereof is supplied to a speaker 9617 through an audio signal processing circuit 9616. A control circuit 9618 receives control information on a receiving station (reception frequency) and sound volume from an input portion 9619, and transmits a signal to the tuner 9611 or the audio signal processing circuit 9616.
[0306]
[0307]
[0308] Next, a structural example of a mobile phone is described with reference to FIG. 29.
[0309] A display panel 9662 is detachably incorporated in a housing 9650. The shape and size of the housing 9650 can be changed as appropriate in accordance with the size of the display panel 9662. The housing 9650 which fixes the display panel 9662 is fitted in a printed wiring board 9651 to be assembled as a module.
[0310] The display panel 9662 is connected to the printed wiring board 9651 through an FPC 9663. The printed wiring board 9651 is provided with a speaker 9652, a microphone 9653, a transmitting/receiving circuit 9654, a signal processing circuit 9655 including a CPU, a controller, and the like, and a sensor 9661 (having a function to measure power, displacement, position, speed, acceleration, angular velocity, the number of rotations, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, current, voltage, electric power, radiation, a flow rate, humidity, gradient, oscillation, smell, or infrared ray). Such a module, an operation key 9656, a battery 9657, and an antenna 9660 are combined and stored in a housing 9659. A pixel portion of the display panel 9662 is provided to be viewed from an opening window formed in the housing 9659.
[0311] In the display panel 9662, the pixel portion and part of peripheral driver circuits (a driver circuit having a low operation frequency among a plurality of driver circuits) may be formed over the same substrate by using transistors, and another part of the peripheral driver circuits (a driver circuit having a high operation frequency among the plurality of driver circuits) may be formed over an IC chip. Then, the IC chip may be mounted on the display panel 9662 by COG (Chip On Glass). Alternatively, the IC chip may be connected to a glass substrate by using TAB (Tape Automated Bonding) or a printed wiring board. By employing such a structure, the power consumption of a display device can be reduced, and a portable phone device can be used for a longer period per charge. Cost reduction of the mobile phone can be achieved.
[0312] The mobile phone shown in
[0313]
[0314]
[0315]
[0316]
[0317]
[0318]
[0319]
[0320]
[0321]
[0322] As shown in
[0323] Next, application examples of a semiconductor device are described.
[0324]
[0325]
[0326] Note that the semiconductor device can be provided in various places as well as on a sidewall of the prefabricated bath unit 9742 shown in
[0327]
[0328] The display panels 9752 shown in
[0329] Note that as each of the display panels 9752, a display panel in which a display element is driven by providing a switching element such as an organic transistor over a film-like substrate so that an image is displayed can be used.
[0330] Note that although this embodiment describes the wall, the prefabricated bath unit, and the columnar object as examples of the structure, this embodiment mode is not limited to this, and the semiconductor device can be provided for various structures.
[0331] Next, an example is described in which the semiconductor device is incorporated in a moving object.
[0332]
[0333] Note that the semiconductor device can be provided in various positions as well as the car body 9761 shown in
[0334]
[0335]
[0336]
[0337] Note that the semiconductor device can be provided in various positions as well as the doors 9771, the glass windows 9773, and the ceiling 9774 which are shown in
[0338]
[0339]
[0340] Note that the semiconductor device can be incorporated in various positions as well as the ceiling 9781 shown in
[0341] Note that although this embodiment mode describes the train car body, the car body, and the airplane body as examples of moving objects, the present invention is not limited to them, and the semiconductor device can be provided in various objects such as a motorbike, a four-wheeled vehicle (including a car, a bus, and the like), a train (including a monorail, a railroad, and the like), and a vessel. Since display on display panels in a moving object can be switched instantly by external signals, the semiconductor device can be used for an advertisement display board for an unspecified number of customers, an information display board in an emergency, or the like by providing the semiconductor device in the moving object.
[0342] Note that although this embodiment mode is described with reference to various drawings, the contents (or may be part of the contents) described in each drawing can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in another drawing. Further, even more drawings can be formed by combining each part with another part in the above-described drawings.
[0343] Similarly, the contents (or may be part of the contents) described in each drawing of this embodiment mode can be freely applied to, combined with, or replaced with the contents (or may be part of the contents) described in a drawing in another embodiment mode. Further, even more drawings can be formed by combining each part with part of another embodiment mode in the drawings of this embodiment mode.
[0344] Note that this embodiment mode shows an example of an embodied case of the contents (or may be part of the contents) described in other embodiment modes, an example of slight transformation thereof, an example of partial modification thereof, an example of improvement thereof, an example of detailed description thereof, an application example thereof, an example of related part thereof, or the like. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.
[0345] This application is based on Japanese Patent Application serial No. 2007-173311 filed with Japan Patent Office on Jun. 29, 2007, the entire contents of which are hereby incorporated by reference.