Abstract
A testing device for testing a distance sensor includes a receiving element for receiving an electromagnetic free-space wave as a receive signal, and a radiating element for radiating a simulated reflection signal. The receive signal or a signal derived therefrom is routed via a time delay circuit, and is thus time-delayed to a time-delayed signal. The time-delayed signal or a signal derived therefrom is radiated as the simulated reflection signal. The time delay circuit has an analog delay path and a digital delay path. The analog delay path implements shorter time delays than the digital delay path, apart from a possible overlap region. An input switch is used to switch the receive signal or the signal derived therefrom to the input of the analog delay path or to the input of the digital delay path, and the signal becomes the time-delayed signal after passing through the connected delay path.
Claims
1. A testing device for testing a distance sensor operating with electromagnetic waves, comprising: a receiving element for receiving an electromagnetic free-space wave as a receive signal; and a radiating element for radiating a simulated electromagnetic reflection signal; wherein the receive signal or a signal derived from the receive signal is routed via a time delay circuit with a predeterminable time delay, and is thus time-delayed to a time-delayed signal; wherein the time-delayed signal or a signal derived from the time-delayed signal is radiated as the simulated reflection signal via the radiating element; wherein the time delay circuit has an analog delay path with a predeterminable time delay and a digital delay path with a likewise predeterminable time delay; wherein the analog delay path implements shorter time delays than the digital delay path, apart from a possible overlap region; and wherein an input switch is used to switch the receive signal or the signal derived from the receive signal either to the input of the analog delay path or to the input of the digital delay path, and the signal becomes the time-delayed signal after passing through the connected delay path.
2. The testing device according to claim 1, wherein the output of the analog delay path or the output of the digital delay patch is contacted by an output switch, and at least an indirect connection is thus established between the contacted output of the delay path concerned and the radiating element.
3. The testing device according to claim 2, wherein a control device synchronously controls the input switch and the output switch so that either the analog delay path is contacted on the input side and output side or the digital delay path is contacted on the input side and output side.
4. The testing device according to claim 1, wherein the output of the analog delay section is contacted by an input of an output summing unit and the output of the digital delay section is contacted by a further input of the output summing unit, the sum signal is formed by the output summing unit from the output signal of the analog delay path and the output signal of the digital delay path, and the output of the output summing unit is connected at least indirectly to the radiating element.
5. The testing device according to claim 4, wherein a bridging device above the input switch ensures that the receive signal or a signal derived from the receive signal is connected both to the input of the analog delay path and to the input of the digital delay path.
6. The testing device according to claim 1, wherein the analog delay path has a plurality of analog delay sub-paths which can be connected in series, a plurality of switches and a switching logic; and wherein the switching logic is able to be preset with a time delay, and the switching logic connects the delay sub-paths in series with the switches in such a manner that the predetermined time delay is achieved in the best possible manner.
7. The testing device according to claim 6, wherein the lengths of the analog delay sub-paths behave like powers of two with respect to one another.
8. The testing device according to claim 1, wherein the digital delay path, viewed from its input to its output and connected in series, has an analog-to-digital converter, a digital delay element with a switching logic and a digital-to-analog converter; wherein a delay time can be predetermined for the switching logic and the switching logic internally switches the digital delay element such that the predetermined delay time is achieved in the best possible manner; and wherein at least one of the digital delay element and the switching logic is implemented by an FPGA.
9. The testing device according to claim 8, wherein the analog delay path has a mixer and an oscillator; and wherein the receive signal or the signal derived from the receive signal is frequency-shifted by the mixer and the oscillator signal in such a way that the output signal of the analog delay path and the output signal of the digital delay path have the same frequency.
10. The testing device according to claim 1, wherein the receive signal, before being time-delayed, is mixed down with a mixer to a lower intermediate frequency and the low-frequency signal thus derived from the receive signal is then time-delayed.
11. The testing device according to claim 1, wherein a Doppler generator is interposed between the outputs of the analog delay path and the digital delay path and the radiating element, which Doppler generator frequency shifts the time-delayed signal by a predeterminable Doppler frequency and thus generates the derived signal.
12. The testing device according to claim 1, wherein the analog delay path implements time delay up to a maximum time delay and the digital delay path implements time delay up to a minimum time delay; wherein the maximum time delay of the analog delay path is greater than the minimum time delay of the digital delay path, so that an overlap range of the time delays exists; and wherein a control device controls the input switch in such a manner that, in the event of changing predetermined time delays in the overlap range, the time delays are switched back and forth with a hysteresis between the analog delay path and the digital delay path, and the input switch is only switched from the analog delay path to the digital delay path in the range of the maximum time delay and vice versa is only switched from the digital delay path to the analog delay path in the range of the minimum time delay.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In detail, there is a plurality of possibilities for designing and further developing the testing device. This is shown in conjunction with the drawings in the following figures.
[0028] FIG. 1 illustrates a known testing device for testing a distance sensor operating with electromagnetic waves.
[0029] FIG. 2 illustrates a testing device with an analog delay path, a digital delay path as well as an input switch and an output switch.
[0030] FIG. 3 illustrates a testing device with an analog and a digital delay path as well as an output summing unit.
[0031] FIG. 4 illustrates a testing device with an analog and a digital delay path as well as a bridging device for the input switch.
[0032] FIG. 5 illustrates a testing device with a more detailed representation of the analog delay path as well as the digital delay path.
[0033] FIG. 6 illustrates a testing device having an analog and a digital delay path and a mixer in the analog delay path, a mixer in the input area of the overall circuit for generating an intermediate frequency and a mixer in the output area of the overall circuit for upmixing the frequency of the delayed signal.
[0034] FIG. 7 illustrates a design of the control device for controlling the input switch and for switching between the analog delay path and the digital delay path with a hysteresis.
DETAILED DESCRIPTION
[0035] FIGS. 1 to 7 each show a testing device 1 for testing a distance sensor 2 operating with electromagnetic waves, which is only schematically shown in FIG. 1. The distance sensor 2 radiates an electromagnetic free-space wave in the direction of the testing device 1 and receives a simulated electromagnetic reflection signal S.sub.TX generated by testing device 1. The testing device 1 has a receiving element 3 for receiving the free space wave radiated by the distance sensor 2 and the testing device 1 has a radiating element 4 for radiating the simulated electromagnetic reflection signal S.sub.TX. The distance sensor 2 itself does not belong to the testing device 1. The receive signal S.sub.RX or a signal S′.sub.RX derived from the receive signal S.sub.RX is routed via a time delay circuit 5, wherein a time delay in a certain range can be predetermined for the time delay circuit 5. The input signal of the time delay circuit 5 is thus time-delayed to a time-delayed signal S.sub.delay. The time-delayed signal S.sub.delay or a signal S′.sub.delay derived from the time-delayed signal S.sub.delay is then radiated as the simulated reflection signal S.sub.TX via the radiating element 4.
[0036] In FIG. 1 it is indicated that the time delay t.sub.delay,soll to be achieved is to be supplied to the time delay circuit 5 as information. For the implementation of the testing device 1 shown here, the exact technical implementation of how exactly this information is supplied to the time delay circuit 5 is not of importance. Usually, the specification for the time delay to be set comes from an environment simulator that simulates the scene to be simulated with surrounding objects and provides corresponding position, velocity and/or acceleration information of the surrounding objects. If, for example, it is known that the distance of the object to be simulated from the distance sensor to be tested is 30 m, a corresponding time delay is calculated taking into account the speed of light as the signal propagation time of an electromagnetic wave and t.sub.delay,soll is specified as the time delay.
[0037] In the testing devices 1 shown in FIGS. 2 to 6, it is now provided in each case that the time delay circuit 5 has an analog delay path 5a with a predeterminable time delay t.sub.delay,soll and a digital delay path 5b with a predeterminable time delay t.sub.delay,soll. The delay times t.sub.delay,soll are shown in FIGS. 2 and 5 and, for better clarity, they are not shown separately in the other figures, but here too there are, of course, time delays t.sub.delay,soll, which are specified accordingly. The predeterminable time delays t.sub.delay,soll can be the same for the analog delay path 5a and for the digital delay path 5b, but they can also differ from each other.
[0038] The delay paths 5a, 5b are implemented in such a manner that the analog delay path 5a implements shorter time delays than the digital delay path 5b, apart from a possible overlap area, in which a corresponding time delay t.sub.delay could be implemented by both delay paths 5a, 5b.
[0039] An input switch 6 connects the receive signal S.sub.RX or the signal S′.sub.RX derived from the receive signal S.sub.RX either to the input of the analog delay path 5a or to the input of the digital delay path 5b. After passing through the connected delay path, the signal then becomes the time-delayed signal S.sub.delay. Due to the alternative application of either the analog delay path 5a or the digital delay path 5b, only one of the two delay paths 5a, 5b is active. If the input switches 6 are controlled sensibly, only that delay path will be operated which is capable of implementing a corresponding predetermined time delay t.sub.delay,soll. This measure also prevents interference, for example in the form of signal cross-talk, between the delay paths.
[0040] FIG. 2 also shows that the output of the analog delay path 5a is contacted or the output of the digital delay path 5b is contacted by an output switch 7. In this manner, at least an indirect connection is established between the contacted output of the affected delay path 5a, 5b and the radiating element 4. In conjunction with the input switch 6, it can thus be ensured that only one of the two delay paths 5a, 5b, i.e., either the analog delay path 5a or the digital delay path 5b, has a signal effect on the output of the testing device 1, i.e., on the radiating element 4. For this, as also shown in FIG. 2, a control device 8 is provided which synchronously controls the input switch 6 and the output switch 7, so that—as already mentioned—either the analog delay path 5a is contacted on the input side and output side or the digital delay path 5b is contacted on the input side and output side. To improve the clarity of the illustrations, FIGS. 5 and 6 do not show the control device 8 with regard to the control of the input switch 6 or the output switch 7. Of course, the control device 8 must also be present here in order to control the input switch 6 and/or the output switch 7.
[0041] As an alternative to using the output switch 7, an output summing unit 9 is provided in the embodiments in FIGS. 3 and 4. The output of the analog delay path 5a is contacted by an input of the output summing unit 9 and the output of the digital delay path 5b is contacted by another input of the output summing unit 9. The output summing unit 9 forms the sum signal from the output signal of the analog delay path 5a and the output signal of the digital delay path 5b. The output of the output summing unit then transmits the delayed sum signal—at least indirectly—to the radiating element 4. As a result of this measure, no output switch is initially required.
[0042] In a further design, however, the use of the output summing unit 9 is of particular importance, as shown in FIG. 4. FIG. 4 shows that a bridging device 10 above the input switch 6 ensures that the receive signal S.sub.RX (or a signal S′.sub.RX derived from the receive signal S.sub.RX) is connected both to the input of the analog delay path 5a and to the input of the digital delay path. In this exceptional case, the analog delay path 5a and the digital delay path 5b are actually operated in parallel and simultaneously. The control of the bridging device 10, which is formed by two switching elements in the illustration according to FIG. 4, is also carried out by the control device 8 in the illustration. Simultaneous application of both the analog delay path 5a and the digital delay path 5b makes sense if the two delay paths 5a, 5b are to be given different time delays t.sub.delay,soll. In this case, two objects with different distances can be simultaneously simulated by the testing device 1. This is a special case because the testing devices 1 shown having a receiving element 3 and a radiating element 4 are used to simulate a surrounding object with a certain azimuthal deflection with respect to the main orientation of the distance sensor. Several of the testing devices 1 described here are used in a test bench for this, wherein the testing devices 1 can be deflected azimuthally with respect to the distance sensor to be tested. The fact that two surrounding objects are arranged in exactly the same azimuthal direction and do not obscure each other, so that two distance signals would actually be expected, is a rare event in the environment simulation.
[0043] FIG. 5 shows a possible implementation of the analog delay path 5a and the digital delay path 5b in more detail. It can be seen that the analog delay path 5a has a plurality of analog delay sub-paths 11 which can be connected in series, a plurality of switches 12 (here only dashed lines are indicated) and a switching logic 13. A time delay t.sub.delay,soll can be predetermined for the switching logic 13. On the basis of this information, the switching logic 13 connects the delay sub-paths 11—at least partially—with switches 12 one after the other in such a manner that the predetermined time delay t.sub.delay,soll is achieved in the best possible manner. The variation of the lengths of the analog delay sub-paths 11 is a special feature of the implementation of the analog delay path 5a shown in FIG. 5. The lengths of the analog delay sub-paths 11 behave like powers of two with respect to one another, i.e., they are binary parts. The length of a certain delay sub-path 11 thus doubles at the transition to the next longer delay sub-path 11. This clever division allows the number of required delay subpaths 11 to be kept to a minimum, and the proportion of switching points is also considerably reduced compared to other solutions (for example, if only identically long delay sub-paths are used). This reduces the effort involved in implementing the analog delay path 5a and also parasitic effects—e.g., reflections on the switching points—are minimized during signal routing.
[0044] FIG. 5 further shows that the digital delay path 5b, seen from its input to its output and connected in series, comprises an analog-to-digital converter 14, a digital delay element 15 with a switching logic and a digital-to-analog converter 16. A time delay t.sub.delay,soll is also predeterminable for the switching logic, wherein the switching logic internally connects the digital delay element 15 in such a manner that the predetermined delay time t.sub.delay,soll is set in the best possible manner. In this case, the digital delay element 15 is implemented by a Field Programmable Gate Array, as is the switching logic. The digital delay path 5b represents a sampling system so that the analog-to-digital converter 14, the digital delay element 15 with the switching logic and also the digital-to-analog converter 16 operate in a time-discrete grid.
[0045] The embodiment shown in FIG. 6 is based on the knowledge that the sampling of the receive signal S.sub.RX or the receive signal S′.sub.RX derived from the receive signal S.sub.RX already carried out by the analog-to-digital converter causes periodically repeating spectra of the sampled receive signal when a frequency spectrum of the sampled signal is taken into account. This effect can therefore be used to process the sampled signal at a frequency different from the center frequency of the analog signal. In this case, an appropriate band-pass or low-pass filter is used to extract the desired frequency range. In order to obtain a signal with the same frequency at the output of the analog delay path 5a as at the output of digital delay path 5b, it is provided in the testing device 1 according to FIG. 6 that the analog delay path 5a comprises a mixer 17 and an oscillator 18, wherein the mixer 17 and the oscillator signal of the oscillator 18 are used to frequency shift the receive signal S.sub.RX or the signal S′.sub.RX derived from the receive signal S.sub.RX in such a manner that the output signal of the analog delay path 5a and the output signal of the digital delay path 5b have the same frequency, meaning the center frequency. This has the advantage that the downstream signal processing does not have to be designed differently or variably, depending on whether a signal is received from the analog delay path 5a or from the digital delay path 5b, rather one and the same components can then be used for further signal processing.
[0046] FIG. 6 also shows that the receive signal S.sub.RX is mixed down to a lower intermediate frequency by a mixer 19 before it is time-delayed, and the low-frequency signal S′.sub.RX derived from the receive signal S.sub.RX is then time-delayed. This measure is also possible with all other embodiments shown in the figures.
[0047] What is not shown in the figures, although it is implemented in a preferred design, is that a Doppler generator is connected between the outputs of the analog delay path 5a and the digital delay path 5b on the one hand and the radiating element 4 on the other hand, which Doppler generator frequency shifts the time-delayed signal S.sub.delay by a predeterminable Doppler frequency and thus generates the derived signal S′.sub.delay. This measure can also be used to simulate radial velocity components of the simulated environment objects.
[0048] FIG. 7 shows a special switching strategy of the control device 8. Here it is assumed that the analog delay path 5a implements time delays t.sub.delay up to a maximum time delay t.sub.analog,max and that the digital delay path 5b implements time delays t.sub.delay up to a minimum time delay t.sub.digital,min. The maximum time delay t.sub.analog,max of the analog delay path 5a is greater than the minimum time delay t.sub.digital,min of the digital delay path 5b, so that there is an overlap range from t.sub.digital,min to t.sub.analog,max in which both delay paths 5a, 5b can equally provide a corresponding signal delay. It is now provided that the control device 8 controls the input switch 6 in such a manner that, in the event of changing predetermined time delays t.sub.delay,soll in the overlap range of the time delays, the time delays are switched back and forth between the analog delay path 5a and the digital delay path 5b with a hysteresis. It is shown in FIG. 7, that it is only switched from the analog delay path (5a) to the digital delay path (5b) in the range of the maximum time delay t.sub.analog,max and, vice versa, it is only switched from the digital delay path (5b) to the analog delay path (5a) in the range of the minimum time delay t.sub.digital,min. This avoids frequent switching back and forth between the analog delay path 5a and the digital delay path 5b, so that negative effects are also reduced during switching between the two delay paths 5a, 5b.
