Semiconductor package with top circuit and an IC with a gap over the IC

Abstract

A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Claims

1. A packaged integrated circuit (IC), comprising: a leadframe including a die pad and leads around the die pad; an analog IC having first bond pads on its active top side; a second circuit including second circuit bond pads attached to the analog IC by an attachment layer configured as a ring with a hollow center that provides an inner gap; wherein a bottom side of the analog IC or a bottom side of the second circuit is attached to the die pad; bond wires coupling some of the first bond pads or some of the second circuit bond pads to the leads, and a second coupling between others of the second circuit bond pads and others of the first bond pads, and a mold compound for encapsulating the second circuit and the analog IC.

2. The packaged IC of claim 1, wherein the bottom side of the analog IC is attached to the die pad, and wherein the bottom side of the second circuit is mounted on the active top side of the analog IC.

3. The packaged IC of claim 2, wherein the analog IC includes a voltage reference circuit, and wherein the second circuit comprises at least one filter capacitor that is coupled for low pass filtering an output from the voltage reference circuit.

4. The packaged IC of claim 3, wherein the gap is over the voltage reference circuit.

5. The packaged IC of claim 1, wherein the attachment layer occupies 2% to 20% of an area of a top one of the second circuit and the analog IC.

6. The packaged IC of claim 1, wherein the analog IC includes a silicon substrate, and wherein the second circuit comprises a silicon substrate.

7. The packaged IC of claim 1, wherein the second coupling is a flipchip coupling for coupling the second circuit bond pads on the second circuit to the others of the first bond pads on the analog IC.

8. The packaged IC of claim 1, wherein the analog IC is attached to the die pad, and wherein the second circuit is flipchip mounted on the active top side of the analog IC.

9. The packaged IC of claim 1, wherein the second circuit comprises an active circuit including at least one transistor.

10. The packaged IC of claim 1, wherein the analog IC comprises a clock generator, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an operational amplifier, or a sensor.

11. A packaged integrated circuit (IC), comprising: a leadframe including a die pad and leads around the die pad; an analog IC die having first bond pads on its active top side comprising a silicon substrate that includes a voltage reference circuit on the active top side, that has its bottom side attached to the die pad; a second circuit comprising a silicon substrate including at least one filter capacitor including second circuit bond pads connected to top and bottom electrodes that is coupled for low pass filtering an output from the voltage reference circuit attached to the top side of the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap, wherein the gap is over the voltage reference circuit; bond wires coupling at least some of the first bond pads to the leads and a second coupling between others of the second circuit bond pads and others of the first bond pads, and a mold compound for encapsulating the packaged IC.

12. A method of making a packaged integrated circuit (IC), comprising: providing a leadframe including a die pad and leads around the die pad; providing an analog IC having first bond pads on its active top side; attaching bond pads of a second IC to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap; attaching a bottom side of the analog IC or a bottom side of the second IC to the die pad; coupling some of the first bond pads or some of the second IC bond pads to the leads with bond wires, and a second coupling between others of the second IC bond pads and others of the first bond pads, and encapsulating the second IC and the analog IC with a mold compound.

13. The method of claim 12, wherein the bottom side of the analog IC is attached to the die pad, and wherein the bottom side of the second IC is mounted on the active top side of the analog IC.

14. The method of claim 13, wherein the analog IC includes a voltage reference circuit, and wherein the second IC comprises at least one filter capacitor that is coupled for low pass filtering an output from the voltage reference circuit.

15. The method of claim 14, wherein the gap is over the voltage reference circuit.

16. The method of claim 12, wherein the attachment layer occupies 2% to 20% of an area of a top one of the second IC and the analog IC.

17. The method of claim 12, wherein the analog IC includes a silicon substrate, and wherein the second IC comprises a silicon substrate.

18. The method of claim 12, wherein the second coupling is a flipchip coupling for coupling the second IC bond pads on the second IC to the others of the first bond pads on the analog IC.

19. The method of claim 12, wherein the analog IC is attached to the die pad, and wherein the second IC is flipchip mounted on the active top side of the analog IC.

20. The method of claim 12, wherein the second IC comprises an active circuit including at least one transistor.

21. The method of claim 12, wherein the analog IC comprises a clock generator, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an operational amplifier, or a sensor.

22. A method of making a packaged integrated circuit (IC), comprising: providing a leadframe including a die pad and leads around the die pad; providing an analog IC die having first bond pads on its active top side comprising a silicon substrate that includes a voltage reference circuit on the active top side, that has its bottom side attached to the die pad; providing a second IC die comprising a silicon substrate including at least one filter capacitor including second IC die bond pads connected to top and bottom electrodes that is coupled for low pass filtering an output from the voltage reference circuit attached to the top side of the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap, wherein the gap is over the voltage reference circuit; coupling with bond wires at least some of the first bond pads to the leads and a second coupling between others of the second IC die bond pads and others of the first bond pads, and encapsulating the packaged IC with a mold compound.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:

(2) FIG. 1A is a top perspective view depiction of an example packaged IC comprising an analog IC including sensitive circuitry and a dual-function second circuit as a top circuit attached to a top surface of the analog IC with a gap over the analog IC, according to an example aspect.

(3) FIG. 1B is a top perspective view depiction of an example packaged IC comprising an analog IC including sensitive circuitry such as a voltage reference circuit and a dual-function second circuit attached to a top surface of the analog IC with a gap over the analog IC, where the second circuit is flipchip attached to the analog IC, according to an example aspect.

(4) FIG. 2A is a cross sectional depiction of the packaged IC shown in FIG. 1A, according to an example aspect.

(5) FIG. 2B is a cross sectional depiction of a packaged IC shown in FIG. 1B that has the filter capacitor flipchip attached to bond pads on the IC, according to an example aspect.

(6) FIG. 2C shows yet another packaged IC arrangement where the top circuit is shown as an analog IC that contains a stress sensitive component comprising a sensitive circuit or sensor, and the bottom die on the die pad is an analog or mixed signal circuit that interfaces with the stress sensitive component.

(7) FIG. 3 shows an example mixed signal stacked die device including sensitive circuitry shown as a mixed signal IC comprising successive-approximation-register (SAR) ADC with a voltage reference circuit which generates a reference voltage output V.sub.REF that has a dual-function second circuit shown as filter capacitors coupled for low pass filtering the voltage reference circuit's reference voltage output that is attached to the mixed signal IC with a gap over the mixed signal IC.

DETAILED DESCRIPTION

(8) Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure.

(9) This Disclosure includes packaged semiconductor devices including an analog IC (e.g., having a voltage reference circuit) and a second circuit (e.g., a large area high capacitance density filter capacitor) attached to an analog IC with a gap over the stress sensitive circuitry of the analog IC. The area of the second circuit can be less than the area of the analog IC die, or more than the area of the analog IC. The second circuit provides a dual-function by isolating the stress sensitive regions on the surface of the analog IC die 110 from stress resulting from the mold compound, and also provides a circuit function such as a low pass filter for filtering noise signals in the voltage reference output without the inherent leakage current errors that would be experienced if these circuit nodes where to be conventionally coupled to a filter capacitor on a PCB. The substrate of the analog IC and the substrate of the second circuit can be matched, such as both comprising silicon, so that their coefficient of thermal expansion (CTE) can be essentially identical, which avoids the CTE induced stress into the analog IC due to the second circuit.

(10) FIG. 1A is a top perspective view depiction of an example packaged IC 100 comprising an analog IC die (analog IC) 110 and a dual-function second circuit 120 with second circuit bond pads attached by an attachment layer 125 to a top surface of the analog IC 110. The packaged IC 100 comprises a leadframe including a die pad 105 and leads 106 around the die pad 105 that the analog IC 110 is mounted on with a die attach adhesive 115. Although not shown, the leads 106 can be on all 4 sides of the package. The disclosed integration of the second circuit 120 within the package avoids problems such as output voltage inaccuracy due to PCB leakage in the case the analog IC 110 includes a voltage reference circuit and the system design conventionally includes a filter capacitor on a PCB.

(11) The second circuit 120 is shown including second circuit bond pads 120a, 120b shown attached to the top side of the analog IC die 110 by the attachment layer 125. The second circuit 120 can comprise a silicon, glass, ceramic, or an alumina substrate. The attachment layer 125 generally occupies 2% to 20% of an area of the top one of the second circuit 120 (as shown in FIG. 1A) and analog IC 110 (see FIG. 2C described below). The second circuit 120 can comprise an active circuit including transistor(s), or a passive circuit such as an inductor or filter capacitor.

(12) The attachment layer 125 can generally be any attachment arrangement with a gap that provides a mechanical bond. The attachment layer 125 is formed in a ring with an inner gap (see gap 126 in FIG. 2A described below) that can comprise a printable low modulus die attach material, such as DOW 7920 which comprises polydimethylsiloxane and silica, where the gap creates an open cavity stress-free region over a portion of the analog IC 110. Although the packaged IC 100 includes an encapsulating mold compound (see the mold compound 220 in FIG. 2A described below), the mold compound is not shown in FIG. lA to avoid obscuring package IC 100 features. Moreover, although the second circuit 120 is shown having a planar bottom side, the second circuit 120 can also have a back side cavity that can increase the distance between the back side of the second circuit 120 over the cavity and the top side of the analog IC 110.

(13) The attachment layer 125 configured as a ring having an inner gap generally can comprise a printable low modulus elastomer, a glass-to-glass peripheral fusion or anodic bond, where the attachment layer 125 secures the second circuit 120 to the analog IC 110 top side up or with a flip chip arrangement with solder balls or solder capped pillars. The electrical connections between the second circuit bond pads 120a and 120b of the second circuit 120 and the first bond pads 111 on the analog IC 110 can comprise conventional wire bonding for the second circuit 120 top side up arrangement as shown as bond wires 131 in FIG. 1A and in FIG. 2A described below, or a flipchip attachment for the second circuit 120 with solder ball 127 connections or solder tipped pillars that also functions as a mechanical attachment shown in FIG. 1B and FIG. 2B described below. The electrical connections between the first bond pads 111 on the analog IC 110 and the leads 106 can also comprise bond wires 131.

(14) The analog IC 110 can comprise a relatively sensitive circuit such as a clock generator, an ADC, a DAC, an operational amplifier, or a sensor. In the case of a sensor, for example, a hall sensor on the analog IC 110 needs to be essentially free of stress to minimize offset errors. In applications where external magnetic flux is accurately measured by nulling at the hall sensor with a bucking coil, where the coil current at null is a representation of the external flux magnitude, the second circuit 120 can be a bucking coil/inductor.

(15) Other sensors that can benefit from disclosed aspects include anisotropic magneto resistor types as well as temperature sensors. The IC may have needed stable performance of for example ˜50 ppm or less from thermal hysteresis, high-temperature operating life (HTOL), and temperature coefficient (TC) lumped together. Normally the unpackaged electrical circuit may have a “pure” TC just due to the circuit design. That TC may be trimmed (e.g., laser trimmed) to a very small number. Packaging stress adds additional TC to the device. That TC is also “mixed” with thermal hysteresis because the materials that are mechanically stressed are hysteretic in that they may mechanically relax with repeated thermal excursions. The second circuit 120 is generally an IC die (e.g., silicon die) that can comprise an active circuit including at least one transistor, and/or passive circuitry such as at least one capacitator, inductor, or resistor.

(16) FIG. 1B is a top perspective view depiction of an example packaged IC 150 comprising an analog IC 110 including sensitive circuitry such as a voltage reference circuit and a dual-function second circuit 120 attached to a top surface of the analog IC 110 with a gap (see gap 126 in FIG. 2B described below) over the analog IC. The second circuit bond pads 120a, 120b of the second circuit 120 are flipchip attached by solder balls 127 to some of the first bond pads 111 on the analog IC 110 (see FIG. 2B). The solder balls 127 are generally in the gap provided by the attachment layer 125 and spaced away from attachment layer 125. Solder balls 127 can be replaced by solder capped pillars.

(17) FIG. 2A is a cross sectional depiction of the packaged IC 100 shown in FIG. 1A, according to an example aspect. Mold compound is shown as 220. The attachment layer 125 provides an open center gap 126 which acts as a mold barrier during molding to enable being free of mold compound 220 that is between the sensitive surface circuit regions of the analog IC 110 and the second circuit 120. This essentially eliminates the effect of mold compound 220 surface stress on the analog IC 110 having the gap 126 because the gap 126 provides a low stress environment for the portion of the analog IC 110 with the gap 126 thereover. This arrangement is analogous to a relatively costly open cavity ceramic package.

(18) FIG. 2B is a cross sectional depiction of a packaged IC 150 shown in FIG. 1B that has the second circuit bond pads 120a, 120b of the second circuit 120 flipchip attached by solder balls 127 to some of the first bond pads 111 on the analog IC 110, according to an example aspect. Packaged IC 150 also creates an environment for the analog IC 110 over the gap 126 that is similar to an open cavity ceramic package.

(19) Another arrangement can combine aspects shown in FIG. 2A and FIG. 2B by having a disclosed top circuit that includes through silicon vias (TSVs) to provide the interconnect to connect to the first bond pads 111 on the analog IC 110. In this arrangement there are solder balls or solder capped pillars to make the die-to-die connection as in a flipchip arrangement, but where the second circuit would be top side up, not flipped. In such a configuration, there can be a combination of wire bonds (to make connections to the leadframe) and solder balls or pillars to connect the TSVs to bond pads on the analog IC 110.

(20) FIG. 2C shows yet another packaged IC 180 arrangement where the top circuit is shown as a mixed signal IC 110′ contains a stress sensitive component comprising a sensitive circuit or sensor, and the bottom die on the die pad 105 is an second circuit 120′ that comprises an analog or mixed signal circuit that interfaces with the stress sensitive component. This arrangement involves a flip chip configuration. An air gap is created between the bottom die shown as second circuit 120′ and the top die being mixed signal IC 110′ that is flipchip die attached which serves as a stress buffer for the stress sensitive component on the mixed signal IC 110′. In this arrangement, the second circuit 120′ being the bottom die can also be a larger sized passive element, that is physically larger than the mixed signal IC 110′ that has the sensitive circuit being protected. The second circuit 120′ has second circuit bond pads 120a, 120b and 120c, where the first bond pads 111 of the mixed signal IC 110′ are attached by the solder balls to the second circuit bond pads 120a and 120b, and the second circuit bond pads 120c are bonded by bond wires 131 to the leads 106.

(21) This Disclosure also includes a semiconductor assembly method described for the case the second circuit is on top of the analog IC that comprises providing a leadframe (generally provided as a LF sheet) including a die pad and leads around the die pad, an analog IC die 110 having first bond pads 111 on its active top side with its bottom side attached to the die pad. A second circuit 120 with second circuit bond pads 120a is attached to the active top side of the analog IC die's first bond pads 111 by solder balls 127 or pillars and held in place by an attachment layer 125 that is configured (e.g., a printed elastomer) as a ring with a hollow center providing an inner gap 126. Bond wires are added for coupling at least some of the bond pads 111 to the leads 106. The second circuit 120 and IC die 110 are encapsulated (e.g., using injection molding) by molding a mold compound, wherein the attachment layer 125 prevents the mold compound from entering the gap 126.

(22) FIG. 3 shows an example mixed signal stacked die device 300 that includes sensitive circuitry shown as a mixed signal IC 110′ comprising a SAR ADC 310 with a voltage reference circuit 315 comprising a voltage reference generator 315a that is known to be sensitive circuitry which provides a pre-buffered reference voltage output (V.sub.REF) that is coupled to a buffer 315b (with its output resistance shown as R.sub.O) which provides a buffered output shown as V.sub.REF that is used as an input by the SAR ADC 310 (shown as a V.sub.REF input). There is a dual-function second circuit 120′ comprising at least one filter capacitor shown as C.sub.L1 which together with a resistor shown as R 318 generally on the voltage reference circuit 315 provides a low pass filter for filtering the output from the voltage reference generator 315a to provide V.sub.REF′. R 318 is generally a high value resistance (e.g., several k ohms to several giga ohms) that makes the circuit sensitive to DC leakage, particularly in conventional arrangements (not shown) where C.sub.L1 is external.

(23) The V.sub.REF output from the buffer 315b is also shown low pass filtered by filter capacitors shown as C.sub.L2 and C.sub.L3 hooked in parallel that together with their associated equivalent series resistance (ESR) provide low pass filtering for V.sub.REF. Filter capacitors C.sub.L2 and C.sub.L3 along with the resistor shown as ESR are part of another disclosed second circuit shown as 120″.

(24) For a disclosed packaged device for the mixed signal stacked die device 300, the arrangement can follow the packaged IC 100 in FIG. 1A or the packaged IC 150 in FIG. 1B described above, where the attachment layer 125 secures the second circuit 120′ and second circuit 120″ to the top of the mixed signal IC 110′ that provides a gap 126 which would be over the voltage reference circuit 315. The gap 126 being free of mold compound in the packaged IC formed between the voltage reference circuit 315 of the mixed signal IC 110′ and the second circuits 120′, 120″ creates a low stress environment for the voltage reference circuit 315, similar to a costly open cavity ceramic package. Although the second circuits 120′ and 120″ are described above both being on top of the voltage reference circuit 315, one or both of the second circuits 120′, 120″ can cover the SAR ADC 310, as both of these circuits are generally stress sensitive.

(25) In operation, the SAR ADC 310 converts an analog input voltage received shown as Vin to a digital code shown only by example for simplicity as a 3 bit digital output (shown as Dout). The overall mixed signal IC 300 accuracy and repeatability depend on how effectively the SAR ADC 310 executes this conversion process. The ADC's 310 actual transfer function has an offset-voltage error and a gain error. The ADC's 310 output code is directly proportional to the Vin level and inversely proportional to the combination of the Vref value plus the gain error. The DC shift of the voltage reference generator 315a inversely impacts the gain accuracy of the ADC 310, which is minimized by the gap 126 within the attachment layer 125 that secures the second circuit 120′ to the top of the mixed signal IC 110′ being over the voltage reference circuit 315, along with minimizing the parasitics due to the second circuit 120′ being within the package with the mixed signal IC 110′ as opposed to conventionally being mounted on a PCB.

(26) Applied to ICs with reference voltage circuits, for a given voltage reference circuit topology, compared to conventional arrangements having filter capacitors on the PCB, disclosed packaged ICs having filter capacitor(s) within the package provides a lower reference voltage shift due to mainly reduced parasitics, lower sensitivity to humidity changes due to the gap being absent of hydroscopic mold compound, less thermal hysteresis as the gap helps the A CTE, as well as better long term Vref stability because the stress induced by the package mold compound changes over time. Initially this is due to additional curing of the mold compound, but also there is relaxation of stress with thermal cycling. Soldering vaporizes moisture absorbed in the hydroscopic material, shifting its stress. Soldering is in itself a thermal hysteresis cycle which changes stress. Attachment to the PCB adds an additional stress due to CTE mismatch of the PCB coupled to the IC via the mold compound and leadframe. Disclosed arrangements for reference circuits also provide higher Vref accuracy by avoiding errors due to PCB leakage.

(27) Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different packaged IC devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

(28) Those skilled in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the above-described aspects without departing from the scope of this Disclosure.