Semiconductor device with field stop layer and semiconductor device manufacturing method thereof

Abstract

First and second n-type field stop layers in an n.sup.− drift region come into contact with a p.sup.+ collector layer. The first n-type field stop layer has an impurity concentration reduced toward an n.sup.+ emitter region at a steep gradient. The second n-type field stop layer has an impurity concentration distribution in which impurity concentration is reduced toward the n.sup.+ emitter region at a gentler gradient than that in the first n-type field stop layer and the impurity concentration of a peak position is less than that in the impurity concentration distribution of the first n-type field stop layer. The impurity concentration distributions of the first and second n-type field stop layers have the same peak position. The first and second n-type field stop layers are formed using annealing and first and second proton irradiation processes which have the same projected range and different acceleration energy levels.

Claims

1. A semiconductor device, comprising: a semiconductor substrate of a first-conductivity-type including a drift region and having a front surface and a rear surface; a first semiconductor layer that is provided in a surface layer of the rear surface of the semiconductor substrate; a second semiconductor layer of the first-conductivity-type: (a) that is provided in the semiconductor substrate so as to come into contact with a front surface side of the first semiconductor layer and a rear surface side of the drift region and that has a front surface and a rear surface; (b) that has a doping concentration that is higher than that of the semiconductor substrate; (c) that has a first impurity concentration distribution gradient proximate to the front surface side of the first semiconductor layer that has an impurity concentration that decreases from the rear surface of the semiconductor substrate toward the front surface of the semiconductor substrate; (d) that has a second impurity concentration distribution gradient proximate to the rear surface side of the drift region that has an impurity concentration that decreases from the rear surface of the semiconductor substrate toward the front surface of the semiconductor substrate, and that has a slope that is substantially less than that of the first impurity concentration distribution gradient; and (e) that contains hydrogen atoms as donors; and a first electrode that comes into contact with the first semiconductor layer, wherein the first impurity concentration distribution gradient and the second impurity concentration distribution gradient are connected at a position close to a depth of 3 μm from the front surface side of the first semiconductor layer and configured such that: (1) an impurity concentration of the second semiconductor layer decreases substantially continuously from the front surface side of the first semiconductor layer to a depth of 20 μm toward the rear surface side of the drift region; and (2) the second impurity concentration distribution gradient has an absolute value which is less than that of the first impurity concentration distribution gradient, and wherein an absolute value of the second impurity concentration distribution gradient close to said position is larger than an absolute value of the second impurity concentration distribution gradient close to the depth of 20 μm from the front surface side of the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein one of or both of a region which has the first impurity concentration distribution gradient and a region which has the second impurity concentration distribution gradient includes the hydrogen atoms as donors.

3. The semiconductor device according to claim 1, wherein the rear surface of the semiconductor substrate is positioned in a depth region and the depth region has a hydrogen concentration that is equal to or more than 0.1 times a maximum hydrogen concentration in a depth direction of the semiconductor substrate.

4. The semiconductor device according to claim 1, further comprising: a second-conductivity-type semiconductor region that is selectively provided in a surface layer of the front surface of the semiconductor substrate; a first-conductivity-type semiconductor region that is selectively provided in the second-conductivity-type semiconductor region; a second electrode that comes into contact with the second-conductivity-type semiconductor region and the first-conductivity-type semiconductor region; and a control electrode that is provided on a surface of a portion of the second-conductivity-type semiconductor region which is interposed between the semiconductor substrate and the first-conductivity-type semiconductor region, with an insulating film interposed therebetween, wherein the first semiconductor layer is of the second-conductivity-type.

5. The semiconductor device according to claim 1, wherein the first-conductivity-type is an n-type, and wherein the hydrogen atoms of the second semiconductor layer have a concentration distribution that has a substantial peak in the rear surface of the semiconductor substrate.

6. The semiconductor device according to claim 1, wherein the second semiconductor layer adjoins the drift region.

7. The semiconductor device according to claim 1, wherein the second impurity concentration distribution gradient has a length from a start point to an end point thereof that is longer than that of the first impurity concentration distribution gradient.

8. The semiconductor device according to claim 1, wherein the semiconductor device constitutes a bipolar transistor structure; wherein the first semiconductor layer is of a second-conductivity-type and is a collector layer, and wherein the first electrode is a collector electrode.

9. The semiconductor device according to claim 1, wherein the semiconductor device constitutes a diode structure, wherein the first semiconductor layer is of the first-conductivity-type and is a cathode layer, and wherein the first electrode is a cathode electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view illustrating the cross-sectional structure of a semiconductor device according to Embodiment 1;

(2) FIG. 2 is a characteristic diagram illustrating an impurity concentration distribution of a field stop layer of the semiconductor device illustrated in FIG. 1;

(3) FIG. 3 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 1 which is being manufactured;

(4) FIG. 4 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 1 which is being manufactured;

(5) FIG. 5 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 1 which is being manufactured;

(6) FIG. 6 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 1 which is being manufactured;

(7) FIG. 7-1 is a characteristic diagram illustrating the impurity concentration distribution along the cutting line A1-A2 of FIG. 5;

(8) FIG. 7-2 is a characteristic diagram illustrating the impurity concentration distribution of the semiconductor device according to Embodiment 1;

(9) FIG. 8 is a cross-sectional view illustrating the cross-sectional structure of a semiconductor device according to Embodiment 2;

(10) FIG. 9 is a characteristic diagram illustrating the electrical characteristics of a semiconductor device according to Example 1;

(11) FIG. 10 is a characteristic diagram illustrating the electrical characteristics of a semiconductor device according to Example 2; and

(12) FIG. 11 is a cross-sectional view illustrating the cross-sectional structure of a semiconductor device according to the related art.

DETAILED DESCRIPTION

(13) Hereinafter, preferred embodiments of a semiconductor device and a semiconductor device manufacturing method according to the invention will be described in detail with reference to the accompanying drawings. In the specification and the accompanying drawings, in the layers or regions having “n” or “p” appended thereto, an electron or a hole means a majority carrier. In addition, symbols “+” and “−” added to n or p mean that impurity concentration is higher and lower than that of the layer without the symbols. In the description of the following embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and the description thereof will not be repeated. In addition, the term “impurity concentration” means net doping concentration by donors and acceptors which are electrically activated in a semiconductor unless otherwise noted.

Embodiment 1

(14) The cross-sectional structure of a planar gate IGBT, which is an example of a semiconductor device according to Embodiment 1, will be described. FIG. 1 is a cross-sectional view illustrating the cross-sectional structure of the semiconductor device according to Embodiment 1. FIG. 2 is a characteristic diagram illustrating an impurity concentration distribution of a field stop layer of the semiconductor device illustrated in FIG. 1. In FIG. 2, a depth of 0 μm indicates the boundary between a p.sup.+ collector layer 8 and an n-type field stop layer 10. The semiconductor device according to Embodiment 1 illustrated in FIG. 1 includes an active region 100a in which a current flows when the semiconductor device is turned on and an edge termination structure region 100b which surrounds the active region 100a, reduces the electric field on the front surface side of an n.sup.− drift region 1, and holds a breakdown voltage.

(15) In the active region 100a, a p base region 2 is provided in a surface layer of the front surface of a semiconductor substrate which will be the n.sup.− drift region 1. An n.sup.+ emitter region 3 is selectively provided in the p base region 2 so as to be exposed from the front surface of the semiconductor substrate. A gate electrode 5 is provided on the surface of a portion of the p base region 2 which is interposed between the n.sup.− drift region 1 and the n.sup.+ emitter region 3, with a gate oxide film 4 interposed therebetween. An emitter electrode 6 comes into contact with the n.sup.+ emitter region 3 and the p base region 2 which are provided in the front surface of the semiconductor substrate. The emitter electrode 6 is electrically insulated from the gate electrode 5 by an interlayer insulating film 7.

(16) In the edge termination structure region 100b, a field limiting ring (FLR) 11, which is a floating p-type region, is provided in the surface layer of the front surface of the semiconductor substrate which will be the n.sup.− drift region 1. A field plate (FP) 12 is provided on the front surface of the semiconductor substrate so as to come into contact with the FLR 11. In addition, the p.sup.+ collector layer 8 is provided in a surface layer of the rear surface of the semiconductor substrate, which will be the n.sup.− drift region 1, so as to extend from the active region 100a to the edge termination structure region 100b. The collector electrode 9 is provided on the rear surface of the semiconductor substrate so as to come into contact with the p.sup.+ collector layer 8.

(17) The n-type field stop layer 10 is provided in the n.sup.− drift region 1 so as to come into contact with the p.sup.+ collector layer 8. The impurity concentration of the n-type field stop layer 10 is higher than that of the n.sup.− drift region 1. The n-type field stop layer 10 includes first and second n-type field stop layers 10a and 10b. It is preferable that the first and second n-type field stop layers 10a and 10b each have an impurity concentration distribution in which the peak position of impurity concentration is the boundary between the p.sup.+ collector layer 8 and the collector electrode 9, that is, the rear surface of the semiconductor substrate after the semiconductor device is completed. When a proton (H.sup.+) is radiated to the rear surface of a semiconductor wafer and an annealing process is performed, a composite defect of the radiated hydrogen atom and a peripheral vacancy is formed and is changed into a donor to generate a hydrogen-related donor. The n-type field stop layer 10 is formed using the hydrogen-related donor, which will be described below.

(18) The first n-type field stop layer 10a has an impurity concentration distribution in which impurity concentration is reduced toward the n.sup.+ emitter region 3 at a steeper gradient than that in the second n-type field stop layer 10b and the impurity concentration of a peak position is higher than that in the impurity concentration distribution of the second n-type field stop layer 10b. The second n-type field stop layer 10b has an impurity concentration distribution in which impurity concentration is reduced toward the n.sup.+ emitter region 3 at a gentler gradient than that in the first n-type field stop layer 10a and the impurity concentration of a peak position is lower than that in the impurity concentration distribution of the first n-type field stop layer 10a. A plurality of n-type field stop layers with an impurity concentration distribution in which the impurity concentration of a peak position is about intermediate between the impurity concentration of the first n-type field stop layer 10a and the impurity concentration of the second n-type field stop layer 10b may be provided between the first n-type field stop layer 10a and the second n-type field stop layer 10b.

(19) Specifically, as illustrated in FIG. 2, the first n-type field stop layer 10a has a higher impurity concentration than the second n-type field stop layer 10b and is provided in a portion of the n.sup.− drift region 1 that is shallower than the second n-type field stop layer 10b from the boundary with the p.sup.+ collector layer 8. The depth of the first n-type field stop layer 10a from the boundary with the p.sup.+ collector layer 8 may be in the range of, for example, 5 μm to 10 μm. The second n-type field stop layer 10b is provided in a portion of the n.sup.− drift region 1 that is deeper than the first n-type field stop layer 10a from the boundary with the p.sup.+ collector layer 8. The depth of the second n-type field stop layer 10b from the boundary with the p.sup.+ collector layer 8 may be, for example, 30 μm.

(20) As such, the n-type field stop layer 10 includes the first and second n-type field stop layers 10a and 10b with different impurity concentration distributions in which the impurity concentrations of the peak position are different from each other and are reduced toward the n.sup.+ emitter region 3 at different gradients. In this way, the n-type field stop layer 10 is formed which has an impurity concentration distribution in which impurity concentration at a predetermined depth from the boundary with the p.sup.+ collector layer 8 is higher than that in Conventional Example 1 represented by a dotted line in FIG. 7-1, which will be described below, and impurity concentration in a region of the semiconductor substrate that is deeper than the p.sup.+ collector layer 8 is lower than that in Conventional Example 1. Conventional Example 1 is a semiconductor device including one n-type field stop layer 41 which is formed by one proton irradiation operation such that the breakdown voltage is equal to that of the semiconductor device according to Embodiment 1.

(21) Next, a method for manufacturing the semiconductor device according to Embodiment 1 illustrated in FIG. 1 will be described. FIGS. 3 to 6 are cross-sectional views illustrating the cross-sectional structure of the semiconductor device according to Embodiment 1 which is being manufactured. FIG. 7-1 is a characteristic diagram illustrating an impurity concentration distribution along the cutting line A1-A2 of FIG. 5. An example in which the first and second n-type field stop layers 10a and 10b are formed so as to have the same peak position in the impurity concentration distribution will be described. First, as illustrated in FIG. 3, a MOS structure including the p base region 2, the n.sup.+ emitter region 3, the gate oxide film 4, and the gate electrode 5 is formed on the front surface of the semiconductor substrate which will be the n.sup.− drift region 1. Then, the emitter electrode 6 is formed so as to come into contact with the p base region 2 and the n.sup.+ emitter region 3.

(22) Then, as illustrated in FIG. 4, an absorber 20 for adjusting the projected range of protons is provided above the rear surface of the semiconductor substrate, with a predetermined gap therebetween. The absorber is a plate member which is made of, for example, aluminum. Then, a first proton irradiation process 21 for forming the first n-type field stop layer 10a is performed for the entire rear surface of the semiconductor substrate in a projected range Rp which is adjusted by the absorber 20. The projected range Rp of the first proton irradiation process 21 is adjusted to a position which will be a thinned rear surface of the semiconductor substrate, depending on the thickness of the absorber 20. In the first proton irradiation process 21, for example, acceleration energy may be 2 MeV and a dose may be 1×10.sup.13/cm.sup.2. It has been known that the acceleration energy is adjusted by the acceleration voltage of a cyclotron or a linear accelerator for proton irradiation.

(23) Then, as illustrated in FIG. 5, a second proton irradiation process 22 for forming the second n-type field stop layer 10b is performed on the entire rear surface of the semiconductor substrate through an absorber 20a with a different thickness from that used in the first proton irradiation process 21. The projected range of the second proton irradiation process 22 is adjusted by the absorber 20a so as to be equal to the projected range Rp of the first proton irradiation process 21. The acceleration energy of the second proton irradiation process 22 is more than the acceleration energy of the first proton irradiation process 21. Therefore, when the absorber 20 of the first proton irradiation process 21 is used, the projected range of protons in the semiconductor substrate in the second proton irradiation process 22 is greater than the projected range Rp of the first proton irradiation process 21. In order to equalize the projected range of the second proton irradiation process 22 to the projected range Rp of the first proton irradiation process 21, the thickness of the absorber 20a used in the second proton irradiation process 22 needs to be greater than that of the absorber 20 used in the first proton irradiation process 21. In the second proton irradiation process 22, for example, acceleration energy may be 8 MeV and a dose may be 1×10.sup.13/cm.sup.2. In each proton irradiation process, for example, the acceleration energy may be changed in the range of 1 MeV to 20 MeV, preferably, in the range of 2 MeV to 8 MeV. Then, annealing is performed to change (activate) the crystal defects formed by the first and second proton irradiation processes 21 and 22 into donors. The annealing may be performed for each proton irradiation process or it may be performed only after at least the last proton irradiation process. The annealing may be performed at a temperature of, for example, 300° C. to 500° C. for 1 to 10 hours.

(24) After the crystal defects are changed into the donors, the first and second n-type field stop layers 10a and 10b that have the position of the rear surface of the semiconductor substrate, which will be thinned in the subsequent process, as the peak position of impurity concentration are formed with a predetermined half width in the semiconductor substrate. The impurity concentration distributions of the first and second n-type field stop layers 10a and 10b after the change to the donors will be described below. Then, as illustrated in FIG. 6, the rear surface of the semiconductor substrate is ground such that only an n-type layer 23, which extends from the peak position of impurity concentration to the boundary with a portion of the n.sup.− drift region 1 that is close to the n.sup.+ emitter region 3, in the n-type layer formed by the first and second proton irradiation processes 21 and 22 remains as the n-type field stop layer 10. Then, the p.sup.+ collector layer 8, which is a connection portion with the collector electrode 9, and the collector electrode 9 which comes into contact with the p.sup.+ collector layer 8 are formed on the rear surface of the semiconductor substrate by a general method. In this way, the planar gate IGBT illustrated in FIG. 1 is completed.

(25) In the above-mentioned semiconductor device manufacturing method, when the first and second n-type field stop layers 10a and 10b which have different peak positions in the impurity concentration distribution are formed, the thickness of the absorber 20 and the absorber 20a is appropriately adjusted. In addition, when the first and second n-type field stop layers 10a and 10b which have different peak positions in the impurity concentration distribution are formed, the rear surface of the semiconductor substrate after the change to the donors is ground such that the first n-type field stop layer 10a or the second n-type field stop layer 10b and the surface layer (p.sup.+ collector layer 8) of the rear surface of the semiconductor substrate satisfy the following positional relationship.

(26) As illustrated in FIG. 7-1, the first n-type field stop layer 10a formed by the first proton irradiation process 21 and the second n-type field stop layer 10b formed by the second proton irradiation process 22 are formed in the semiconductor substrate after the change to the donors such that the peak positions in the impurity concentration distributions overlap each other. In the impurity concentration distribution of the first n-type field stop layer 10a, the peak position is high, the rate of decrease in impurity concentration from the peak position is high, and the half width is narrow. In the impurity concentration distribution of the second n-type field stop layer 10b, the peak position is low, the rate of decrease in impurity concentration from the peak position is low, and the half width is wide. Therefore, since the n-type layer 23 which extends from the peak position of the impurity concentration to the end close to the n.sup.+ emitter region 3 remains as the n-type field stop layer 10, it is possible to obtain the n-type field stop layer 10 with the desired impurity concentration distribution illustrated in FIG. 2.

(27) FIG. 7-2 is a characteristic diagram illustrating the impurity concentration distribution of the semiconductor device according to Embodiment 1. FIG. 7-2 illustrates the positional relationship between the first n-type field stop layer 10a or the second n-type field stop layer 10b and the surface layer of the rear surface of the semiconductor substrate in the invention. The vertical direction indicates impurity concentration (a position represented by N0 indicates the concentration of the substrate) and the horizontal direction indicates the depth from the rear surface D0 of the semiconductor substrate after the semiconductor device is completed. The rear surface D0 of the semiconductor substrate after the semiconductor device is completed indicates the position of the rear surface of the semiconductor substrate, which is polished and thinned during a process, in the completed semiconductor device. In addition, a portion on the left side of the rear surface D0 of the semiconductor substrate after the semiconductor device is completed is a portion of the semiconductor substrate which is removed by polishing during a process. A p.sup.+ collector layer (not illustrated) is formed in a surface layer of the rear surface D0 of the semiconductor substrate after the semiconductor device is completed (hereinafter, referred to as a surface layer of the rear surface of the semiconductor substrate).

(28) When the surface layer of the rear surface of the semiconductor substrate (p.sup.+ collector layer) is within the range of the first n-type field stop layer 10a or the second n-type field stop layer 10b, that is, a region with a higher concentration than the semiconductor substrate, it is possible to obtain the effect of the invention. Preferably, as represented by reference numeral B3, the surface layer of the rear surface of the semiconductor substrate is within a region with impurity concentration that is equal to or more than 0.1 times the peak concentration (the maximum concentration) Np of each field stop layer. More preferably, as represented by reference numeral B2, the surface layer of the rear surface of the semiconductor substrate is within a region with impurity concentration that is equal to or more than 0.5 times the peak concentration (the maximum concentration) Np of each field stop layer. Reference numeral B1 indicates a case in which the rear surface D0 of the semiconductor substrate after the semiconductor device is completed has impurity concentration that is equal to the peak concentration Np of each field stop layer. As a comparative example, a case in which the surface layer of the rear surface of the semiconductor substrate after the semiconductor device is completed is within a region with a lower concentration than the semiconductor substrate is represented by a coarse dotted line. When the substrate concentration N0 is higher than 0.1 Np or 0.5 Np, the surface layer of the rear surface of the semiconductor substrate is preferably in the region with a higher concentration than the semiconductor substrate.

(29) The first and second proton irradiation processes 21 and 22 may be reversed. That is, the first proton irradiation process 21 may be performed after the second proton irradiation process 22. The first and second proton irradiation processes 21 and 22 may be performed for the front surface of the semiconductor substrate. When the first and second proton irradiation processes 21 and 22 are performed for the front surface of the semiconductor substrate, it is easy to adjust the projected range Rp of the first and second proton irradiation processes 21 and 22. In addition, for the acceleration energy of the first and second proton irradiation processes 21 and 22, as described above, the acceleration energy of the second proton irradiation process 22 may be more than that of the first proton irradiation process 21. For example, the acceleration energy can be changed in the range of 1 MeV to 10 MeV. In the first and second proton irradiation processes 21 and 22, a dose can be changed in the range of 1×10.sup.12/cm.sup.2 to 1×10.sup.15/cm.sup.2.

(30) As described above, according to Embodiment 1, the first and second proton irradiation processes with the same projected range Rp and different acceleration energy levels can be performed to form the first and second n-type field stop layers which have the same peak position of impurity concentration in the depth direction of the semiconductor substrate and have different impurity concentrations at the peak position and different impurity concentration distributions. Therefore, the second proton irradiation process can be performed with acceleration energy less than that of the first proton irradiation process to form the second n-type field stop layer without a defect in a deep portion which is arranged on the n.sup.+ emitter region side from the rear surface of the semiconductor substrate. Thus, it is possible to suppress a reduction in lifetime while providing a donor region in which the defect caused by proton irradiation is changed into a donor. As a result, it is possible to suppress an increase in the switching speed due to a significant reduction in lifetime when the semiconductor device is turned off.

(31) Since the second n-type field stop layer with few defects is formed in the deep portion which is arranged on the n.sup.+ emitter region side from the rear surface of the semiconductor substrate, it is possible to reduce the amount of leakage current when a reverse bias is applied. In addition, it is possible to form the second n-type field stop layer with an impurity concentration distribution, in which impurity concentration is reduced toward the n.sup.+ emitter region at a gentle gradient, in the deep portion which is arranged on the n.sup.+ emitter region side from the rear surface of the semiconductor substrate. Therefore, it is possible to suppress oscillation during switching.

(32) According to Embodiment 1, the first proton irradiation process can be performed with acceleration energy more than that of the second proton irradiation process to form the first n-type field stop layer with a higher impurity concentration than the second n-type field stop layer in a portion of the n-type field stop layer which comes into contact with the collector layer. Therefore, the second n-type field stop layer has an impurity concentration distribution in which impurity concentration is reduced toward the n.sup.+ emitter region at a gentle gradient, which makes it possible to smoothly prevent the expansion of the depletion layer which is spread from the pn junction between the p base region and the n.sup.− drift region during switching. The first n-type field stop layer has a higher impurity concentration than the second n-type field stop layer, which makes it possible to prevent the depletion layer from reaching the p.sup.+ collector layer.

Embodiment 2

(33) FIG. 8 is a cross-sectional view illustrating the cross-sectional structure of a semiconductor device according to Embodiment 2. The semiconductor device according to Embodiment 2 differs from the semiconductor device according to Embodiment 1 in that it is a diode instead of the IGBT.

(34) As illustrated in FIG. 8, in an active region 100a, a p.sup.+ anode region 32 is selectively provided in a surface layer of a front surface of an n.sup.− semiconductor substrate 31. An anode electrode 33 comes into contact with the p.sup.+ anode region 32. Reference numeral 34 is an interlayer insulating film. An n.sup.+ cathode layer 35 is provided in a surface layer of a rear surface of the n.sup.− semiconductor substrate 31 and an n-type field stop layer 10 is provided in a region that is deeper than the n.sup.+ cathode layer 35 from the rear surface.

(35) Similarly to Embodiment 1, the n-type field stop layer 10 includes first and second n-type field stop layers 10a and 10b. A cathode electrode 36 comes into contact with the n.sup.+ cathode layer 35. A method for manufacturing the semiconductor device according to Embodiment 2 is the same as the method for manufacturing the semiconductor device according to Embodiment 1 except for the element structure of the diode formed by a general method.

(36) As described above, according to Embodiment 2, it is possible to obtain the same effect as that in Embodiment 1. In addition, according to Embodiment 2, when the first and second n-type field stop layers 10a and 10b are provided in the diode, it is possible to suppress a reduction in carrier concentration in the vicinity of the cathode layer. Therefore, it is possible to suppress hard recovery due to the noise of the diode and to obtain a high breakdown voltage.

Example 1

(37) FIG. 9 is a characteristic diagram illustrating the electrical characteristics of the semiconductor device according to Example 1. FIG. 9 illustrates the waveform of a leakage current when a reverse bias is applied. An IGBT (hereinafter, referred to as Example 1) including the first and second n-type field stop layers 10a and 10b was manufactured by the semiconductor device manufacturing method according to Embodiment 1. For comparison, Conventional Example 1 represented by the dotted line in FIG. 7-1, in which one n-type field stop layer was formed by one proton irradiation process such that the breakdown voltage was equal to that in Example 1, was manufactured. Then, in Example 1 and Conventional Example 1, a leakage current was measured when the reverse bias was applied.

(38) As illustrated in FIG. 9, in Conventional Example 1, it was verified that, since the region, which extended from the rear surface of the semiconductor substrate to the deep region on the emitter region side and had a large number of defects, was formed by one proton irradiation process, the leakage current increased due to a diffusion current that was caused by the defects in an early stage when a forward current increased (a portion represented by reference numeral 42). Conventional Example 1 has a high risk of thermal runaway during a high-temperature operation. In contrast, in Example 1, it was verified that, since the second n-type field stop layer 10b with few defects was provided in the deep region that was arranged on the emitter region side from the rear surface of the semiconductor substrate, it was possible to suppress an increase in leakage current while maintaining the breakdown voltage, as compared to Conventional Example 1.

Example 2

(39) FIG. 10 is a characteristic diagram illustrating the electrical characteristics of a semiconductor device according to Example 2. FIG. 10 illustrates the reverse recovery waveform of a free wheeling diode (FWD). An FWD (hereinafter, referred to as Example 2) including first and second n-type field stop layers 10a and 10b was manufactured by the semiconductor device manufacturing method according to Embodiment 2. For comparison, Conventional Example 2, in which one n-type field stop layer was formed by one proton irradiation process such that the breakdown voltage was equal to that in Example 2, was manufactured. Then, in Example 2 and Conventional Example 2, a surge voltage and a reverse current during reverse recovery were measured.

(40) As illustrated in FIG. 10, in Conventional Example 2, it was verified that the region, which extended from the rear surface of the semiconductor substrate to a deep region on the emitter region side and had a large number of defects acting as a lifetime killer, was formed by one proton irradiation process, hard recovery occurred in a variation di/dt in reverse recovery current over time (a portion represented by reference numeral 51) and the surge voltage increased (a portion represented by reference numeral 52). In contrast, in Example 2, it was verified that, since the second n-type field stop layer 10b with few defects was provided in the deep region that was arranged on the anode region side from the rear surface of the semiconductor substrate, it was possible to reduce the number of defects acting as the lifetime killer in the deep region on the anode region side and soft recovery could be achieved.

(41) The invention is not limited to the above-described embodiments, but various changes and modifications of the invention can be made. For example, three or more proton irradiation processes with different acceleration energy levels may be performed to form three or more n-type field stop layers which have the same peak position of impurity concentration and different impurity concentrations at the peak position. In addition, the invention can be applied to various semiconductor devices in which the field stop layer can be provided. In Embodiment 1, the planar gate IGBT is given as an example of the semiconductor device. However, the invention may be applied to, for example, a trench gate IGBT.

INDUSTRIAL APPLICABILITY

(42) As described above, the semiconductor device and the semiconductor device manufacturing method according to the invention are useful for a semiconductor device that is used in a power conversion device, such as a converter or an inverter.

EXPLANATIONS OF LETTERS OR NUMERALS

(43) 1 n.sup.− DRIFT REGION 2 p BASE REGION 3 n.sup.+ EMITTER REGION 4 GATE OXIDE FILM 5 GATE ELECTRODE 6 EMITTER ELECTRODE 7 INTERLAYER INSULATING FILM 8 p.sup.+ COLLECTOR LAYER 9 COLLECTOR ELECTRODE 10 n-TYPE FIELD STOP LAYER 10a FIRST n-TYPE FIELD STOP LAYER 10b SECOND n-TYPE FIELD STOP LAYER 20, 20a ABSORBER 22 SECOND PROTON IRRADIATION 23 n-TYPE SEMICONDUCTOR LAYER EXTENDING FROM PEAK POSITION OF IMPURITY CONCENTRATION TO END OF N.sup.+ EMITTER REGION 3