Semiconductor apparatus having through silicon via structure and manufacturing method thereof

Abstract

A semiconductor apparatus having through silicon via structure and a manufacturing method thereof to enable the significant process and cost reduction and the improvement of performance of through silicon via by forming barrier and seed metal layers with electroless plating, the barrier layer applied in forming through silicon via with wet electroless plating thereby enabling structural uniformity and improvement in electrical properties with less process cost and higher yield to meet the both performance and economic objectives. The instant invention enables the formation of TSV with smaller diameter of the opening and, if necessary, omitting the formation of copper seed layer. Direct copper plating on the barrier layer is possible and this reduces the number of processes, charges the inside of via at once through copper plating to bring more improvements in electrical properties as effect.

Claims

1. A semiconductor apparatus comprising: a substrate having through silicon via; an insulation layer; a cobalt-based barrier layer formed with an electroless plating process on said insulation layer of said through silicon via wherein there further comprises a barrier layer with a conductivity of 80.sub.u Ohm/cm or below and wherein there is an additional organosilane layer for enhancement of adhesion between said insulation and said barrier layer.

2. The semiconductor apparatus as defined in claim 1 wherein said cobalt-based barrier layer has a thickness of 30 to 150 nm and is made of Co, Co—W or a combination thereof.

3. The semiconductor apparatus as defined in claim 1 wherein there is an additional crystal layer for enhancement of electroless plating between said insulation layer and said barrier layer.

4. The semiconductor apparatus as defined in claim 1 further comprising at the lower part of said substrate including said insulation layer there is an exposed pad layer at its lower part wherein said through silicon via is extended.

5. The semiconductor apparatus as defined in claim 4 wherein said insulation layer where said through silicon via is connected further comprises an opening area with undercut on said exposed area of the exposed pad layer.

6. The semiconductor apparatus as defined in claim 5 wherein said barrier layer including said opening area with undercut includes uniform formation at the inner side of said through silicon via including said exposed pad layer.

7. The semiconductor apparatus as defined in claim 1 further comprising the additional inclusion of a metal filling structure of said through silicon via by electroplating on said barrier layer.

8. The semiconductor apparatus as defined in claim 1 wherein there is the additional inclusion of a seed layer with electroless plating for electroplating of a filling substance of said through silicon via on said barrier layer.

9. The semiconductor apparatus as defined in claim 8 wherein there is the additional inclusion of a metal filling structure of said through silicon via with electroplating on said seed layer.

10. A method of manufacturing a semiconductor apparatus comprising the steps of: preparing the substrate of said semiconductor apparatus by cleaning and drying said substrate having an insulation layer inside of a through silicon via; forming a cobalt-based barrier with ultrasonic electroless plating on said insulation layer of the inner part of said through silicon via; washing and drying said substrate with ultrasonic deionized water wherein said preparing and barrier cleaning steps are conducting at 100˜0.1 mbar vacuum state and comprise the additional steps of: completely sinking said substrate into deionized water; cleaning said semiconductor apparatus for several seconds to minutes; injecting N.sub.2; and drying said semiconductor apparatus.

11. The method as defined in claim 10 wherein said preparing step further comprises using a mixture of peroxides at 1050% on sulfuric acid to clean said substrate for 10 seconds to 20 minutes.

12. The method as defined in claim 10 further comprising the step of; providing deposition of organosilane with wet ultrasonic process for enhancement of adhesion of said insulation layer inside said through silicon via of said substrate; ultrasonic cleaning of said substrate before said barrier layer is formed.

13. The method as defined in claim 12 wherein deposition of the organosilane step injects a mixture of 0.1˜10% of silane on DSMO (dimethyl sulfoxide), and the temperature is maintained at 30˜80 degrees C. to provide ultrasonic vibration, and said substrate is applied on a cell and recollected.

14. The method as defined in claim 12 wherein said ultrasonic has a conductivity of 2˜8 ms/cm, a frequency of 15˜55 KHz and an energy of 5˜30 W/L and a pH between 1.0˜4.0.

15. The method as defined in claim 12 wherein said ultrasonic cleaning process of the substrate further comprises the step of filling a cell with methanol, applying said cell into a tank filled with deionized water, providing ultrasonic vibration and applying it to said substrate for several seconds to minutes.

16. The method as defined in claim 10 wherein deposition of Pd crystal with wet ultrasonic process on said insulation layer at the inner side of the through silicon via on the substrate to activate electroless plating of the barrier layer before the barrier layer forming stage and additional activation process of deposited Pd crystal in another cell.

17. The method as defined in claim 16 wherein said Pd crystal deposition process further comprises filling the mixture of 0.1˜10% of hydrochloric acid to deionized water on the cell, applying the Pd powder of 50˜200 mg/L to provide ultrasonic vibration, applying the substrate on the cell and recollecting it.

18. The method as defined in claim 16 further comprising an activation process of the deposited Pd crystal by applying dimethylamineborane at 300˜700 mg/L to provide ultrasonic vibration, applying the substrate on the cell and recollecting it.

19. The method as defined in claim 16 where at the barrier layer forming stage a mixture of 0.1˜20% of citric acid is injected on cobalt chloride plating fluid, maintaining the temperature at 30˜80 degrees C. to provide ultrasonic vibration, applying the substrate on the cell and recollecting it.

20. The method as defined in claim 19 wherein said cobalt chloride plating fluid is replaced in the barrier layer forming stage with one or more mixture of cobalt sulfate, sodium hypophosphite, sodium gluconic acid and glycine of claim 19.

21. The method as defined in claim 19 wherein the ultrasound has ah frequency of 15˜55 KHz and an energy of 5˜30 W/L.

22. The method as defined in claim 10 further comprising the inclusion of a metal filling step for the through silicon via with electroplating with the barrier layer of the substrate as electrode after the barrier cleanup stage.

23. The method as defined in claim 10 further comprising the step of forming a seed layer with ultrasonic electroless plating on the barrier layer of the substrate after the barrier layer cleanup step.

24. The method as defined in claim 23 further comprising the step of a metal filling stage of the through silicon via with electroplating of the seed layer of the substrate as electrode after the seed layer cleanup step.

25. The method as defined in claim 23 further comprising the step of injecting a mixture of 10˜50 g/L of EDTA, 0.5˜1.0 g/L of PEG, 10˜50 g/L of glyoxylic acid and 10˜50 mg/L of bipyridyl on 10˜50 g/L of copper sulfate, maintaining the temperature at 30˜80 degrees C. and a constant circulation of the mixture to provide ultrasonic vibration, applying the substrate on the cell and collecting.

26. The method as defined in claim 25 wherein the ultrasound has a frequency of 15˜55 KHz and an energy of 5˜30 W/L.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is an example of a laminated chip structure by traditional TSV.

(2) FIGS. 2A-2G are examples of through via formation by traditional TSV.

(3) FIGS. 3A-3E are examples of semiconductor apparatuses having through silicon via structure through the instant manufacturing method.

(4) FIG. 4 is a partial drawing of a manufactured semiconductor apparatus having through silicon via structure produced according to the embodiment of present invention.

(5) FIG. 5 is a block diagram presenting the process in process toll according to the embodiment of present invention.

(6) FIG. 6 is a flowchart of the clean process according to the embodiment of present invention.

(7) FIG. 7 is a flowchart of the DIW cleaning and drying process according to the embodiment of present invention.

(8) FIG. 8 is a flowchart of the ultrasonic organosilane vapor-deposition process according to the embodiment of present invention.

(9) FIG. 9 is a flowchart of the ultrasonic cleaning process according to the embodiment of present invention.

(10) FIG. 10 is a flowchart of the ultrasonic Pd crystal vapor-deposition process according to the embodiment of present invention.

(11) FIG. 11 is a flowchart of ultrasonic the Pd crystal activation process according to the embodiment of present invention.

(12) FIG. 12 is a flowchart of the electroless barrier layer plating process according to the embodiment of present invention.

(13) FIG. 13 is a flowchart of the electroless seed layer plating process according to the embodiment of present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

(14) Turning to the drawings, the preferred embodiment is illustrated and described by reference characters that denote similar elements throughout the several views of the instant invention.

(15) The preferred embodiment of the instant invention is illustrated in detail in the attached drawings and embodiments.

(16) Firstly, FIG. 3A or 3E present semiconductor apparatuses utilizing through silicon via structure's manufacturing method. From this, the substrate structure in FIG. 3A is identical to the one in FIG. 2 with the previously given example with the traditional technology.

(17) As shown by the figure, it is an example of via last process to form a TSV on a chip that is composed of a silicon substrate (31), an insulation layer (32), a pad layer (33) and an insulation layer (34). From the given example, the insulation layers (32, 34) are dielectric layers with a silicon oxide film (SiO.sub.2) and the pad layer (33) is a metal electrode to be connected with the TSV to be formed.

(18) FIG. 3B illustrates an exposure of the lower part of insulation layer (32) in constructing a hole or trench-shaped via with high aspect ratio on silicon substrate (31) through DRIE process or a UV laser.

(19) FIGS. 3A and 4B can be implemented through traditional ordinary TSV process.

(20) FIG. 3C applies selective wet etching process on an oxide insulation layer (32) to the via of the structure formed in FIG. 3B, processes wet etching on the insulation layer (32) at the lower part of the via and safely exposes its lower insulation layer (33). In this process, undercut occurs in the upper insulation layer (32), but this enhances the electrical connectivity and physical ruggedness between the post-formed TSV and pad layer (33).

(21) FIG. 3D prepares an insulation layer (35) by forming silicon oxide film (SiO.sub.2) with chemical vapor-deposition method on the side of the via which is used as the dielectric layer for electrical insulation from the filling substance of the via after forming the via to pad layer (33) as above. This chemical vapor-deposition generates an insulation layer (35) only on the silicon substrate (31), but not on the exposed pad layer (33) as described.

(22) FIG. 3E presents features of the current invention, which forms a barrier layer (36) with an electroless plating process on the structure formed with undercut as described in FIG. 3D. The barrier layer (36) is reliably formed with uniform thickness and high step coverage on the via with undercut with complexity and high aspect ratio.

(23) The barrier layer (36) uses either Ni and NiB as substances or Co and Co—W which is different from PVD using Ti and TiN or CVD using Ta, TaN. It applies electroless plating process for uniform formation and forms 30˜150 nm of thickness through the process adding ultrasonic vibration at appropriate temperature and pH.

(24) Current TSV diameters are formed in single digits˜three digit/μm, and uniform formation with extremely thin thickness is possible and 30˜150 nm of membrane structure is possibly provided with sufficient blocking feature to prevent diffusion of the filling metal in via to silicon substrate.

(25) This means that extremely low conductivity is possible compared to existing Ti or Ta type barrier layers. For example, the existing TiN(PVD) normally used in the current provides conductivity at the degree of 100˜250.sub.u Ohm/cm and TaN(CVD) provides conductivity at the degree of 100˜250.sub.u Ohm/cm. However, the NiB or Co—W according to the embodiment of current invention provides 20˜80.sub.u Ohm/cm. In other words, an improvement of 20%˜1000% in conductivity can be made and this enables dramatic enhancement of the performance of TSV.

(26) The Ni and NiB barrier layer and the Co and Co—W layer with electroless plating process formed by the instant invention provides higher adhesiveness compared to the existing sputtering or chemical vapor deposition. The plating is performed under ultrasonic conditions with higher uniformity and at least 50% of step coverage and half of less stress than the existing process to provide high reliability.

(27) Providing a uniform barrier layer on via with high aspect ratio means the barrier layer can be used as electrode for electroplating without a seed layer to be used in electroplating of filling metal of via. In other words, the barrier layer according to the embodiments in current invention is used now as an electrode for post-electroplating and can reliably form a metal filling structure (e.g. Cu Fill) to fill the via without a separate seed layer.

(28) Naturally, more seed layers can be formed with the identical ultrasonic electroless plating on the barrier layer. In this case, the uniformity and quality of the seed layer increases and this enables enhancement of the performance of TSV by uniform formation of metal filling structure to fill the via with electroplating without electrode.

(29) FIG. 4 is a drawing of the part of the actually manufactured semiconductor apparatus having through silicon via structure. SiO2 insulation layer (35) on silicon substrate (31) and NiB or Co or Co—W barrier layer with electroless plating (36) at 50 nm of thickness on the insulation layer are presented.

(30) Superior step coverage and uniform thickness of 50 nm on the top and side are presented.

(31) Therefore, none of occurrence of the issues in existing dry process due to poor step coverage and non-uniform thickness is found. The equipment cost in this process is significantly lower than dry process due to the comparatively simple process of wet process with fewer processes, thereby enabling cost reduction and an increase in yield.

(32) FIG. 5 is a block diagram (100) presenting the process according to the embodiment of present invention. The block diagram includes a total of 12 cell blocks defining the steps in performing the formation of seed layer as described. It is composed of total of 10 cell blocks in performing the formation of barrier layer excepting the production of the seed layer.

(33) Firstly, the insulation layer inserts a cassette with silicon substrate having via formed in the inside to wet process equipment through front opening unified pod (“FOUP”) (101).

(34) The silicon substrate goes under pre-wet and drying process with DIW in cell 1 (111) and clean process removes containments. The cell 1 and 2 may be omitted but if applied, various contaminants that may be found on the substrate before electroless plating are effectively removed.

(35) After this, basic preparation is ready for actual electroless plating through recleaning with DIW, inserting N.sub.2 and drying of the substrate at cell 3 (113). Then, ultrasonic electroless barrier lamination may be done in cell 9 (119), but the process to activate the insulation layer inside of the via can be additionally done through cell 4 (114) or cell (118) to increase the efficiency of this electroless barrier lamination.

(36) Ultrasonic organosilane deposition is performed by applying the substrate on cell 4 (114) after cleaning and drying it through cell 3 (113). This ultrasonic organosilane deposition is performed to increase the adhesion of barrier layer to be plated under appropriate temperature condition and the vapor-deposition provides ultrasonic vibration to increase the degree of uniformity of the organosilane.

(37) An organosilane layer is formed on the inner wall of the insulation layer of the via and then the substrate is cleaned through ultrasonic cleaning process at cell 5 (115) and deposition is performed with palladium (Pd) crystal through wet ultrasonic process at the inner part of via where the organosilane is formed at cell 6 (116).

(38) Then, cell 7 (117) activates the palladium crystal layer.

(39) When the palladium crystal is formed at the inner side of the via where the barrier is to be plated and activated with separate processes, the palladium crystal works as a catalyst and the electroless barrier plating efficiency and properties are improved.

(40) After that, the substrate is cleaned and dried with DIW at cell 8 (118) to prepare the actual ultrasonic electroless barrier plating process.

(41) Performing two stages of the process activating the insulation layer at the inner side of via before performing actual electroless barrier plating enables to provide a barrier layer with improvements in all elements, which determines the performance of TSV, such as the barrier's degree of uniformity, electrical properties, step coverage, stress, adhesion, etc.

(42) The barrier layer's thickness is only 30˜150 nm and the organosilane layer or Pd crystal layer is minutely formed at the surface of the insulation layer inside via and this is understood to not be a process to form a separate layer but a plated side activation process. Each of the actual processes takes only several minutes to a couple of dozen minutes and is considered as one preparation process to form a barrier, which need not be classified as a sperate membrane stage.

(43) The cell 9 (119) forms a barrier at 30˜150 nm thickness with electroless plating with Ni, NiB, Co or Co—W or a combination thereof by maintaining the appropriate temperature with ultrasonic vibration on the activated substrate for plating. Naturally, decreasing or increasing thickness is possible.

(44) Because this formation of barrier layer enables having metal layers of via through electroplating, it directly proceeds to cell 12 (120) to clean and dry the substrate and recollects the cassette where the silicon substrate is located from the wet process equipment through wafer carrier (102) in the process.

(45) If the aim is to form more seed layers, the substrate formed barrier layer through cell 9 (119) can be delivered to cell 10 (131) to proceed electroless seed layer plating on the barrier layer. For instance, uniform formation in seed layer can be induced by applying ultrasonic vibration during electroless copper seed layer plating. Then, the formed silicon substrate that is cleaned and dried at cell 12 (120) to seed layer through wafer carrier (102) in the process can be recollected.

(46) And then, the via can be filled in uniform condition without gaps by plating Cu and other metals with electroplating process with the barrier or seed layer as electrode to optimize the performance of TSV.

(47) FIG. 6 or 13 are examples of the condition in process for each cell explained in FIG. 5. The volume of cell is 1,000 ml in the premise, this presents deposition of NiB or Co—W barrier layer with electroless plating is performed on the insulation layer of the inner via and the process of electroless plating of Cu seed layer on the barrier layer selectively.

(48) FIG. 6 is a flowchart of the clean process according to the embodiments of the current invention and includes the process preparing 10˜50% of hydrogen peroxide type compound on sulfuric acid type compound, completely sinking the substrate into the compound for 10 seconds to 20 minutes and recollecting the wafer.

(49) The compound may be replaced with the mixed compound of hydrochloric acid and hydrogen peroxide or sulfuric acid and hydrogen peroxide.

(50) FIG. 7 is a flowchart of the cleaning and drying process with DIW according to the embodiments of current invention. As described, it has 100˜0.1 mbar vacuum state, inserts DIW and sink the substrate on the DIW, cleans the wafer from several seconds to minutes, recollects the wafer and dries it by blowing N.sub.2.

(51) FIG. 8 is a flowchart of ultrasonic organosilane deposition process according to the embodiments of current invention. It includes the process of mixing silane at 0.1˜10% to DSMO (Dimethyl Sulfoxide), maintaining the temperature at 30˜80 degrees C., providing ultrasonic vibration, completely sinking substrate on the cell for several seconds to minutes (e.g. about 10 minutes) and recollecting it.

(52) From this, the ultrasound provided as above should have a conductivity of 2˜8 ms/cm, a frequency of 15˜55 KHz, an energy of 5˜30 W/L and the pH of solution where the ultrasound is provided should be the set value between 1.0˜4.0,

(53) FIG. 9 is a flowchart of ultrasonic cleaning process according to the embodiment of present invention. To completely clean the substrate after the ultrasonic organosilane process, it fills the cell with methyl alcohol, applies it to a tank filled with DIW to provide ultrasonic vibration, completely sinks the substrate on the cell, keeps it several seconds to minutes and recollects it. In this case, the ultrasound may be provided with a frequency of 15˜55 KHz and an energy of 5˜30 W/L as well.

(54) FIG. 10 is a flowchart of ultrasonic Pd crystal deposition process according to the embodiment of present invention. It includes the process filling a cell with the solution with 0.1˜10% of hydrochloric or similar acids to DIW, providing ultrasonic vibration after applying 50˜200 mg/L of Pd powder (Palladium (11)), completely sinking the substrate on the cell and recollecting it after several seconds to minutes.

(55) FIG. 11 is a flowchart of ultrasonic Pd crystal activation process according to the embodiment of present invention, it includes the process mixing 300˜700 mg/L of DMAB (dimethylamineborane) to DIW to apply, providing ultrasonic vibration, applying substrate on the cell and collecting it after several seconds to minutes.

(56) Acetoin, dimethylamineborane, glycine, acetol or other modifiers may replace the dimethylamineborane.

(57) FIG. 12 is a flowchart of electroless barrier layer plating process according to the embodiment of present invention. It includes the process mixing 0.1˜20% of citric acid to nickel sulfate to inject, providing ultrasonic vibration at 30-80 degrees of temperature, completely sinking substrate on the cell and collecting it after a minute to several minutes.

(58) The plating fluid used in electroless plating for the nickel film can include nickel sulfate, sodium hypophosphite, sodium gluconic acid and glycine. The plating fluid in electroless plating for cobalt film can use cobalt chloride, malic acid and glycine.

(59) The citric acid can be replaced by tartaric acid, malic acid, oxalic acid, succinic acid, lactic acid, etc.

(60) Maintaining pH at set value between 6.0˜10.0 though methylethanolamine is recommended during the process. In here, methylethanolamine may be replaced by amines, glycols, glycol ethers, polyglycol ethers or the combination as common solvent of the group with two or more of same.

(61) Maintaining 15˜55 KHz of frequency and 5˜30 W/L of energy for the ultrasonic to be provided in the process is recommended.

(62) FIG. 13 is a flowchart of the electroless seed layer plating process according to the embodiment of present invention. It includes injecting the mixture of 10˜50 g/L of EDTA (ethylenediaminetetraacetic acid, 0.5˜1.0 g/L of PEG (polypropyleneglycol), 10˜50 g/L of glyoxylic acid, 10˜50 mg/L of bipyridyl to 10˜50 g/L of copper sulfate to a cell, maintaining 30˜80 degrees C. of temperature and constant circulation of the mixture to provide ultrasonic vibration, completely sinking substrate on the cell and recollecting it after a minute to 20 minutes. In this case, the ultrasound is recommended to be provided with frequency of 15˜55 KHz and energy of 5˜30 W/L as well.

(63) In here, the copper sulfate plating fluid, EDTA plating fluid may be replaced with similar type of other plating fluids, PEG may be replaced with a surfactant such as block copolymer or polypropyleneglycol, the glyoxylic acid may be replaced with similar reducers, the bipyridyl may be replaced with corrosion inhibitor such as benzene triazole, caffeine, theophiline, bipyridyl or triazole.

(64) While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is understood that the invention is not limited to the disclosed embodiments, but on contrary, is intended to cover various modifications and equivalent arrangements by a person of ordinary skill in the art to which the inventions pertain within the spirit and scope of the appended claims.

(65) The invention illustratively disclosed herein suitably may be practiced in the absence of any element which is not specifically disclosed herein.

(66) The discussion included in this patent is intended to serve as a basic description. The reader should be aware that the specific discussion may not explicitly describe all embodiments possible and alternatives that are implicit. Also, this discussion may not fully explain the generic nature of the invention and may not explicitly show how each feature or element can actually be representative or equivalent elements. Again, these are implicitly included in this disclosure. Where the invention is described in device-oriented terminology, each element of the device implicitly performs a function. It should also be understood that a variety of changes may be made without departing from the essence of the invention. Such changes are also implicitly included in the description. These changes still fall within the scope of this invention.

(67) Further, each of the various elements of the invention and claims may also be achieved in a variety of manners. This disclosure should be understood to encompass each such variation, be it a variation of any apparatus embodiment, a method embodiment, or even merely a variation of any element of these. Particularly, it should be understood that as the disclosure relates to elements of the invention, the words for each element may be expressed by equivalent apparatus terms even if only the function or result is the same. Such equivalent, broader, or even more generic terms should be considered to be encompassed in the description of each element or action. Such terms can be substituted where desired to make explicit the implicitly broad coverage to which this invention is entitled. It should be understood that all actions may be expressed as a means for taking that action or as an element which causes that action. Similarly, each physical element disclosed should be understood to encompass a disclosure of the action which that physical element facilitates. Such changes and alternative terms are to be understood to be explicitly included in the description.