Dual processor power saving architecture communications system

Abstract

A communications system has a low power connectivity processor and a high performance applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Claims

1. A communications system comprising: a low power connectivity processor coupled to a low power front end, the low power front end comprising a first baseband processor operative to receive wireless packets when enabled, and a first Media Access Controller (MAC) coupled to the first baseband processor; an applications processor coupled to a performance front end, the performance front end comprising a second baseband processor operative to receive wireless packets when enabled, and a second MAC coupled to the second baseband processor; and a power controller coupled to the low power connectivity processor and to the applications processor; the low power connectivity processor having a maximum power consumption which is less than one tenth of a maximum power consumption of the applications processor, the applications processor having an instruction execution rate capability which is at least ten times greater than the instruction execution rate capability of the low power connectivity processor; the power controller applying power to, and enabling, the low power connectivity processor and also the low power front end during intervals when the low power front end is receiving wireless packets lower than a data rate threshold; and the power controller applying power to, and enabling, the applications processor and the performance front end when the performance front end is receiving wireless packets greater than the data rate threshold.

2. The communications system of claim 1 where the data rate threshold is the reception of Wireless Local Area Network (WLAN) Multiple Input Multiple Output (MIMO) packets.

3. The communications system of claim 1 where the performance front end has a wireless packet data rate capability which is at least ten times greater than the low power front end.

4. The communications system of claim 3 where the low power front end is operative for both Bluetooth and Wireless Local Area Network (WLAN) packets.

5. The communications system of claim 1 where the data rate threshold is between 10 Mbps and 100 Mbps data throughput rate.

6. The communications system of claim 1 where the data rate threshold is exceeded for communications using at least one wireless protocol comprising: an IEEE standard 802.11n, 802.11ac, 802.11ax, or 802.11be.

7. The communications system of claim 1 where the low power connectivity processor is at least one of a Cortex-M® processor, an ARM® processor, or a processor configured to use a RISC-V architecture.

8. The communications system of claim 1 where power is removed from the low power connectivity processor and the low power front end when the applications processor and the performance front end are active.

9. The communications system of claim 1 where power is not applied to the applications processor and the performance front end until the low power front end detects wireless packets which are greater than the data rate threshold.

10. The communications system of claim 1 where all the wireless packets are at least one of: Wireless Local Area Network (WLAN) packets, Bluetooth packets, Zigbee packets, Long Term Evolution (LTE) mobile wireless packets, 3G mobile wireless packets, or 4G mobile wireless packets.

11. A communications system comprising: a low power connectivity processor operative to process wireless packets; a low power front end comprising a first baseband processor operative to receive wireless packets and a first Media Access Controller (MAC) coupled to the first baseband processor; an applications processor; a performance front end comprising a second baseband processor operative to receive wireless packets and a second MAC coupled to the second baseband processor; and a power controller coupled to the low power connectivity processor and to the applications processor; the power controller operative to enable the low power connectivity processor and the low power front end upon detection of wireless packets of a first class of packet type, the power controller operative to enable the applications processor and the performance front end upon receipt of wireless packets of a second class of packet type.

12. The communications system of claim 11 where the first class of packet type is Bluetooth.

13. The communications system of claim 11 where the second class of packet type is at one of: an IEEE standard 802.11n, 802.11ac, 802.11ax, or 802.11be.

14. The communications system of claim 11 where the second class of packet type has a data rate less than a threshold which is from 10 Mbps to 100 Mbps, and the second class of packet type is greater than the threshold.

15. The communications system of claim 11 where the power controller examines a packet type field of a wireless packet received by the first MAC to determine the first class of packet type.

16. A method for wireless communications operative on a communications system comprising a low power front end including a first baseband processor and a first Media Access Controller (MAC) coupled to a low power connectivity processor operative to process wireless packets, a performance front end including a second baseband processor and a second MAC coupled to an applications processor, and a power controller coupled to the low power connectivity processor and to the applications processor, the method comprising: receiving a wireless packet on the first MAC; examining a packet type field provided by the first MAC; and enabling power to the applications processor and the performance front end only when the packet type field matches a performance packet type associated with a computational complexity greater than the low power connectivity processor can process, and not enabling power to the applications processor and the performance front end when the packet type field does not match the performance packet type.

17. The method for wireless communications of claim 16 where the performance packet type is a Multiple Input Multiple Output (MIMO) Wireless Local Area Network (WLAN) packet type.

18. The method for wireless communications of claim 16 where the performance packet type is at least one of: an IEEE standard 802.11n, 802.11ac, 802.11ax, or 802.11be.

19. The method for wireless communications of claim 16, where the first baseband processor is operative to receive Bluetooth packets or WLAN packets which are not MIMO packets, and the second baseband processor is operative to receive the MIMO packets.

20. The method for wireless communications of claim 16 where the low power connectivity processor is at least one of a Cortex-M® processor, an ARM® processor, or a processor configured to use a RISC-V architecture.

21. The method for wireless communications of claim 16 where the performance packet type has a data rate in excess of 100 Mbps.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a block diagram for a communication system.

(2) FIG. 2 shows a block diagram for an adaptive communication system.

(3) FIG. 3 shows a block diagram for a power saving communications system.

(4) FIG. 4 shows a time diagram for example processing of packets.

DETAILED DESCRIPTION OF THE INVENTION

(5) FIG. 1 shows an example communication system for portable electronics. A high performance application processor 130 is coupled to high performance Double Data Rate (DDR) memory 120 for program execution, high performance NAND architecture flash 122 for program storage, a display interface 124 for high quality graphics, a graphical processing unit 126 for fast rendering, and a display/touchscreen 128. The high performance application processor 130 is also coupled to a first transceiver 135 and second RF transceiver 151 for receiving and transmitting packets. The first transceiver 135 is typically any of a Bluetooth, WLAN, Zigbee, LTE, 3G, 4G, or other wireless protocol interface, and the second transceiver 151 is a wireless protocol interface for a different protocol than the first transceiver. Typically, one of the transceivers is WLAN or Bluetooth, and the second transceiver is a wireless telephone protocol such as LTE, 3G, or 4G for providing simultaneous connectivity to each type of protocol.

(6) A battery 142 is managed by a power distribution 140, which selectively enables various subsystems as required to manage power consumption, and a charge controller 144 manages the rate of charge from an external power source (not shown) to battery 142.

(7) The NAND flash 122 provides persistent storage for a variety of executable instructions known as programs, tasks, or processes which are executed by high performance application processor 130. Typical programs and processes which are saved in NAND flash 122 are the openGL graphical library 102, wireless drivers 103, TCP/IP stack 104, Bluetooth stack 106, security functions 108 for WLAN and TCP, network configuration details 110, audio, display, and other device drivers 112 associated with instructions specific to hardware and which are either provided by the hardware manufacturer or integrated into the operating system for the application processor 130, and user-downloaded applications of which there may be many types, shown as 114, 116, and 118.

(8) Users of mobile electronics have come to expect the rich functionality provided by the architecture of FIG. 1, and the largest deployment of such devices re smartphones.

(9) As wearable electronics such as watches and virtual reality glasses (augmented reality AR and virtual reality VR) become more popular, it is desired to provide a similarly rich user experience and maximizing the battery 142 life of the wearable device. A particular impediment to this trajectory is battery 142 capacity and size. The huge packaging size reduction from a mobile phone to a watch or VR/AR glasses can be scaled for the microelectronic integrated circuits, which can be packaged more compactly. However, in a typical mobile smartphone, the battery is half of the package volume, and governs the usable interval between charges. In exchange for rich functionality, mobile phone users are content to exchange small size for a single day of use (or less) between recharging events. Even the “low power mode” of smartphones (a mode typically enabled when the remaining charge of the battery reaches below 20% of full capacity) is not sufficient for these new uses. As wearable electronics scale to smaller and smaller sizes, a different communications and processing architecture and system is required.

(10) FIG. 2 shows an alternative connection architecture and communication system 200, where the low power connectivity system 202 with low power connectivity front end 204 (which may be an SOC) and high performance connectivity front end 222, which is also referred to as a “performance front end” in contrast with “low power front end” 204. Each low power connectivity front end 204 and high performance connectivity front end 222 is typically operative on the same communications protocol, but operate exclusively from each other depending on protocol type. The low power connectivity front end 204 comprises RF processing 206 receiving and transmitting wireless packets, coupled to baseband processing 208 which is specific to the particular communications protocols it supports, and media access controller (MAC) 210 which provides a digital interface 217 for receiving and transmitting data. Similarly, the performance front end comprises RF processing 224 which may support MIMO with multiple antennas 221, which is coupled to baseband processing 226 which provides more sophisticated signal processing for MIMO and high data rate modulation and demodulation, and high speed media access controller (MAC) 228 with digital interface 231. First low power connectivity front end 204, and low power connectivity processor 212 are optimized for low power consumption and provide minimal functionality for a particular communication protocol. An example low power connectivity processor 212 is an ARM® processor, or a Cortex-M® series processor, both licensed by Arm Holdings (www.arm.com), or a microcontroller architecture based on the open source RISC-V (www.riscv.org). For example use with WLAN, low power connectivity front end 204 SOC is operative for single channel (non-MIMO or SISO) modes with data rates on the order of 10 Mbps to 100 Mbps, which are at least a factor of 10 lower than the high performance connectivity of high performance connectivity front end (or SOC) 222. By contrast, the high performance connectivity front end 222 will provide the capacity of a much higher bandwidth capacity protocol, such as 2×2 MIMO or 3×3 MIMO, or the IEEE protocols 802.11n, 802.11ac, 802.11ax, or 802.11be MIMO approaching 1 Gbps data rate capacity or more. In one example of the invention, the selection of the performance front end is made on a performance packet type, where a performance packet type is one with a maximum available data transfer rate in excess of 10 Mbps or alternatively, in excess of 100 Mbps. When enabled, the high performance connectivity front end 222 will require greater power associated with the faster clocking rates associated with higher data rates. High performance connectivity front end 222 typically supports 2×2, 3×3 MIMO of current standards, and 4×4 MIMO in the future. The high performance connectivity front end (or SOC) 222 and application processor 230 may be operative to support a channel bandwidth of 80 Mhz and data throughput ranges on the order of a gigabit per second, transitioning to 10 Gbps in the future over a 160 Mhz channel. The application processor is typically coupled to block read NAND flash, which copies instructions to high speed double data rate (DDR) RAM, which is sufficiently sized to provide data buffers for high speed TCP/IP data transmission and reception, shown collectively as block 232.

(11) When the high performance application processor 230 is enabled, data bus 216 may couple data from low power connectivity processor 212 or via data bus 217 from the low power connectivity front end (or SOC) 204. The flexibility of data paths 217 and 216 allow the application processor 230 to handle MAC layer data directly, or via path 216 to accept data flows such as TCP traffic or Bluetooth traffic (for 204 in a Bluetooth mode) from low power connectivity processor 212.

(12) An additional distinction between the application processor 230 and low power connectivity processor 212 is the processor architecture of each. Low power connectivity processor 212 is typically a simple microcontroller or network processor having a single core and executing code from low power NOR flash directly from the flash memory 214. The data for the low power processor is held in comparatively small on-chip RAM (such as 32 MB) that is included with the microcontroller or network low power connectivity processor 212, and this power savings approach limits the processing speed of the low power connectivity processor 212 and limits the number of supported connections (TCP or Bluetooth) to on the order of 10 connections. The low power connectivity processor 212 typically has a pipeline or CPU clock rate which is on the order of 100 Mhz, or alternatively, less than 1/10th the clock or pipeline rate of the high performance application processor 230. The operating system for the low power connectivity processor 212 is a single thread simple OS Real Time Operating System (RTOS) such as freeRTOS, which handles a comparatively small number of tasks on a single threaded processor (or a processor with a small number of threads, less than 2 or 3), whereas the operating system for the high performance application processor 230 is multi-threaded, supporting at least twice as many threads as the low power connectivity processor 212, and typically on the order of thousands or more connections than low power connectivity processor 212, or alternatively at least two orders of magnitude more connections (such as TCP sockets) than the low power connectivity processor 212.

(13) Application processor 230 is a multi-core high performance processor coupled to a large DDR (high speed) RAM with is on the order of 16 GB to 32 GBGB or RAM, the application processor 230 having 6-10 pipeline stages, or alternatively at least twice as many as the low power processor 213. The high performance application processor 230 is coupled to a large NAND flash memory of 16 GB or more for program storage, which is typically 2-3 orders of magnitude greater than the on-chip memory of low power connectivity processor 212, has a clock rate which is at least 10× the clock rate of the low power connectivity processor 212, and uses a rich multi-featured operating system such as Android OS, Apple iOS, Linux, or other multi-threaded operating system.

(14) In one example of the invention, the ultra-low power connectivity processor 212 is integrated as a subsystem of the high performance application processor 230, where each of the low power connectivity front end 204, high performance connectivity front end (or SOC) 222, low power connectivity processor 212, high performance application processor 230 and associated peripherals can be separately enabled and powered for selective power savings.

(15) In a preferred mode of operation, the wireless connectivity system 200 of FIG. 2 enables only low power connectivity system 202 for incoming and outgoing network connections. If the required connection exceeds the capability or capacity of the low power connectivity system 202, the high performance connectivity front end (or SOC) 222 and application processor 230 are enabled for only the required duration of time to service the task requiring its capability, after which the high performance connectivity front end (or SOC) 222 and application processor 230 are powered down and operation resumes with the low power connectivity system 202.

(16) In one example of the invention, 1×1 WLAN communications are handled by the low power connectivity front end 204 and MAC layer data (via 217) or TCP data (via 216) are handled by the high performance application processor 230.

(17) In another example of the invention, the ultra-low power connectivity system 202 is operative with 1×1 WLAN communications, and handles up to 10 WLAN connections and also performs TCP termination and TCP/TLS SSL connections using low power connectivity processor 212 such that the high performance application processor 230 is not enabled for these types of connections.

(18) In another example of the invention, low power connectivity system 202 which may be a system-on-a-chip (SOC) handles Bluetooth communications and high performance connectivity SOC handles all WLAN connections.

(19) In another example of the invention, 2×2, 3×3 and 4×4 MIMO communications are handled exclusively by the high performance connectivity front end 222 and application processor 230, and other types of connections are handled by the low power connectivity front end 204 and low power connectivity processor 212.

(20) In another example of the invention, the low power connectivity front end 204 handles 1×1 WLAN communications, and the high performance application processor is enabled for only brief intervals sufficient to establish secure WLAN connections (such as the security supplicant task), TCP/TLS and SSL connection establishment, or other connection setup or teardown functions beyond the capability of the low power connectivity processor 212, and the application processor 230 is disabled for all other operations.

(21) FIG. 2 shows a connection architecture which provides connectivity using a minimal power consumption for any configuration, and for any networking protocol such as WLAN which has high performance modes and low performance modes, each protocol having a low power and low performance transceiver such as low power connectivity system 202 and a high performance connectivity front end 222. Each of 204, 212/214, 222, and 230/232 are separately enabled using minimum power consumption metrics to satisfy the tasks at hand.

(22) FIG. 3 shows a block diagram for a processor architecture for handling application layer tasks as an extension of the network processing of FIG. 2. Identically numbered references correspond to the function performed by the reference number in the other figures. Low power connectivity processor 212 is now coupled to a low power application processor 302, which has “mini-” versions representing subsets of functions provided by the application programs and processes of the application processor 340, each processor having the corresponding executable code compiled for the instruction set of the applicable processor. An “A” suffix for the drivers 304A to 320A refers to the “mini” functionality for low power application processor 302 and “B” suffix for the full function high performance application processor 340. The ‘B’ suffix code (executable program) is preferably stored in high performance NAND flash of application processor 340, and the ‘A’ suffix code is preferably stored in the execute-in-place (XIP) NOR flash of application processor 302. Because of the low processing overhead for Bluetooth communications within the capability of Application processor 302, FIG. 3 shows Bluetooth driver 308 present for low power application processor 302 only. Mini-WLAN driver 304A handles only network parameters associated with the supported protocols of low power connectivity front end 204, while WLAN driver 304B handles the full network stack for high performance connectivity 222, including a configuration which uses interface 217. Mini-TCP/IP stack 306A supports on the order of 10 network connections, whereas full TCP/IP Stack 306B supports on the order of thousands of network connections. Similarly, the respective security supplicants 310A and 310B, network management 312A and 312B, audio and display drivers 314A and B provide respective interface functionality that allows the low power application processor 302 or high performance application processor 340 to control display/touchscreen 330 and audio/sensors 332.

(23) The applications handled by low power application processor 302 and high performance application processor 340 are distinct in operation from the operations associated with the “A” and “B” drivers. Incoming network packets to the low power connectivity front end 204 handled by low power network connectivity processor 212 may be of a notification nature and providing information to display 336 (with or without a required touchscreen 336 response), and the response may invoke additional tasks which are beyond the capability of low power application processor 302. For example, in the case of a wearable watch (or mobile phone), an incoming text message may result in a notification presented by the low power application processor 330 to the display touchscreen 330. If the text message is answered on the wearable, this may be handled by the low power application processor and mini-app such as 316A, whereas if the message includes a video or other task requiring high computational performance beyond the application processor 302 capability, the low power application processor 302 may wake up the high performance application processor 340, which receives the notification via interface 334 and takes over the task until completion. The same handoff may occur on the network layer between 204/212 and 222/340. Each application 316A, 318A, 320A will be divided into “mini” (computationally simple) aspects which are in the capability of, and performed by the low power application processor 302, and aspects which are handled by the high performance processor 340, typically selected on the basis of being with or beyond the CPU capacity of the low power application processor 302. This method saves power because the low power processor 302 has less than 1/10th of the processing capability of the application processor 340 as measured by at least one of: speed of execution, size of RAM memory, stage clock speed, or size of flash storage.

(24) In the block diagram of FIG. 3, either the low power application processor 302 or the high performance application processor 340 may write to the display 336 or read the touchscreen 336, or present audio 332 or read a sensor 332. In this manner, the “A” suffix “mini” application and “B” suffix full applications each are able to access peripherals associated with their respective capability and available tasks, such as the display/touchscreen and sound/sensors of the system of FIG. 3, with the low power application processor 302 handling as many tasks as possible, thereby saving considerable power compared to the architecture of FIG. 1 where the application processor handled all tasks. An examination of typical application use by the inventors shows that out of a 24 hour interval, the low power application processor 302 is able to handle 90% or more of the tasks, consuming approximately ⅓th of the power of the application processor 340, and the high performance (and greater power consumption) processor 340 is available when needed for the remaining 10% or less of time processing tasks, resulting in no loss of performance while reducing power consumption. The high performance processor is ordinarily powered down until needed, with power controller 341 controlling the application of power to the high performance (and high power consumption) processor 340, high performance connectivity front end 222, and associate components, such that they are powered up and enabled only when required. Similar power savings are in effect with 204/212 and 222/340 based on network requirements.

(25) In a music application, the music may be stored in NAND flash 334 by the high performance application processor during an earlier download, such as by adding the music tracks to a digital library stored in NAND flash 334. In a music player mini-application 318A, the low power application processor 302 may periodically read from the NAND flash 334 to buffer music, since the NAND flash 334 consumes negligible power, thereby providing very low power consumption during the music player operation using exclusively the low power application processor 302. The low power application processor 302 and mini-application 318A may then completely run the music player application, including showing the selected song and providing music controls (play, skip, go back, etc.) via touchscreen 336 and direct interface.

(26) Other ‘mini’ applications can handle incoming notifications using the Wi-Fi interface over the low power connectivity front end 204 and low power connectivity processor 212, including text messages, chats, or phone calls, all of which can be exclusively performed using the low power application processor 302 and associated mini-application rather than the fully featured version operative on the high performance application processor 340, preferably with the low power WLAN/BT interface 204/212.

(27) In another example of the invention, an additional LTE or 3G/4G wireless telephony interface (not shown) may be interfaced to low power connector network connectivity processor 212 for use with low power application processor 302. In this example, the LTE/3G/4G telephone interface may operate using the low power application processor 302 and associated mini-app 320A for the phone call, and activate the high performance application processor 340 and associated full app 320B for a video call or other high CPU utilization task which is beyond the capability of low power application processor 302.

(28) FIG. 4 shows a series of examples operating on a mobile phone 401 which includes connectivity processor 403, display/touchscreen 405, and application processor 407 is shown in a powerdown state. Mobile phone 401 receives a Facebook notification 402 such as via SISO WLAN, which is handled by connectivity processor 403 which sends a display notification 404 to a touchscreen 405. In this example, the mobile phone user does not react to the notification, and not further action is taken. The mobile phone receives a text message 406, which is displayed 408, and the user may use the touchscreen 405 to formulate a reply, which is sent 412 and transmitted (not shown) by mobile phone 401. An incoming phone call 414 is directed to connectivity processor 403, which displays the caller number 416 as a form of notification. The operator may decline the call 418, which is handled by the low power connectivity processor 403, and the declination 420 is handled by the mobile phone 401. A subsequent phone call 422 displays a caller ID 424, and accepted 426, which causes the connectivity processor 403 to apply power to and wake 452 the application processor 407 and send call related context 428 to the application processor 407. This example shows just one aspect of operation, where the notifications and display functions are handled by the low power connectivity processor 403, and tasks requiring greater computational capacity are handled by the application processor 407. In one example of the invention, each process related to a task has a mini-process (such as display tasks 416 and 424) which is operable on the connectivity processor 403 (corresponding to 212 of FIG. 3) and a high computational demand process (such as 428) which is operable on the application processor (corresponding to 340 of FIG. 3) having sufficient computational capability to handle the associated process.

(29) In the present invention, an ‘order of magnitude’ indicates a values which may be 10× larger or 1/10th of the nominal value. ‘Approximately’ or ‘in the range of’ is understood to be +/−50% of the nominal value.