Spacer structure for double-sided-cooled power module and method of manufacturing the same

Abstract

A spacer structure, which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, includes: a conductive material layer which is composed of a composite material; an underlying plating layer disposed on the conductive material layer; and a copper plating layer disposed on the underlying plating layer, in which the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.

Claims

1. A spacer structure which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, the spacer structure comprising: a conductive material layer composed of a composite material; an underlying plating layer disposed on the conductive material layer; and a copper plating layer disposed on the underlying plating layer, wherein the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.

2. The spacer structure of claim 1, wherein the underlying plating layer is composed of one metal selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), and cobalt (Co).

3. The spacer structure of claim 1, wherein the copper plating layer has a thickness of 5 μm or more.

4. The spacer structure of claim 1, further comprising a metal layer disposed on the copper plating layer.

5. The spacer structure of claim 4, wherein the metal layer is composed of one metal selected from a group consisting of gold (Au), silver (Ag), and palladium (Pd).

6. A method of manufacturing a spacer which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, the method comprising: applying an underlying plating layer onto a conductive material layer composed of a composite material; and applying a copper plating layer onto the underlying plating layer, wherein the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.

7. The method of claim 6, wherein the underlying plating layer is composed of one metal selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), and cobalt (Co).

8. The method of claim 6, wherein the copper plating layer has a thickness of 5 μm or more.

9. The method of claim 6, further comprising applying a metal layer onto the copper plating layer.

10. The method of claim 9, wherein the metal layer is composed of one metal selected from a group consisting of gold (Au), silver (Ag), and palladium (Pd).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The following accompanying drawings are provided to help understand the present disclosure, and exemplary embodiments of the present disclosure are provided together with the detailed description. However, technical features of the present disclosure are not limited to the particular drawings, and the features illustrated in the respective drawings may be combined to constitute another exemplary embodiment.

(2) FIG. 1 is a cross-sectional view illustrating a structure of a double-sided-cooled power module in the related art.

(3) FIG. 2A is a view illustrating a spacer structure in the related art which is used for a double-sided-cooled power module.

(4) FIG. 2B is a schematic view illustrating a reaction process between a joining material and a metal layer at a joint portion between a semiconductor chip and a spacer in the related art illustrated in FIG. 2A.

(5) FIG. 3A is a view illustrating a spacer structure according to an exemplary embodiment of the present disclosure which may be used for a double-sided-cooled power module.

(6) FIG. 3B is a schematic view illustrating a reaction process between a joining material and a metal layer at a joint portion between a semiconductor chip and a spacer according to an exemplary embodiment of the present disclosure illustrated in FIG. 3A.

(7) FIG. 4 is a schematic view illustrating a method of joining the double-sided-cooled power module according to an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(8) Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

(9) However, the present disclosure is not restricted or limited by exemplary embodiments. Like reference numerals indicated in the respective drawings refer to members which perform substantially the same functions.

(10) An object and an effect of the present disclosure may be naturally understood or may become clearer from the following description, and the object and the effect of the present disclosure are not restricted only by the following description. In addition, in the description of the present disclosure, the specific descriptions of publicly known technologies related with the present disclosure will be omitted when it is determined that the specific descriptions may unnecessarily obscure the subject matter of the present disclosure.

(11) FIG. 1 is a cross-sectional view illustrating a structure of a double-sided-cooled power module in the related art. As illustrated in FIG. 1, in the double-sided-cooled power module in the related art, upper and lower insulating substrates 130 may be disposed at both sides of a semiconductor chip 160, and a spacer 150 may be installed to connect the upper and lower substrates 130 and define a space in which a wire (not illustrated) is installed. In general, a joining process, using A joining material (solder) 140, is performed to maintain joining forces between the spacer 150, the semiconductor chip 160, and the insulating substrates 130. In addition, thermal grease, that is, a thermal interface material (TIM) 120 is formed outside each of the upper and lower insulating substrates 130 to transfer heat to coolers 110.

(12) FIG. 2A illustrates a spacer structure in the related art which is used for the double-sided-cooled power module. Referring to FIG. 2A, the spacer structure in the related art has a structure in which a nickel plating layer 220 is applied onto a conductive material layer 210 made of a composite material. There may occur the following problem when the spacer structure illustrated in FIG. 2A is used for the double-sided-cooled power module, and the problem will be described below with reference to FIG. 2B.

(13) FIG. 2B is a schematic view illustrating a reaction process between a joining material and a metal layer at a joint portion between the semiconductor chip and the spacer in the related art illustrated in FIG. 2A. As illustrated in FIG. 2B, in a case in which heat is produced from the semiconductor chip as the power module operates in a state in which the joining material is disposed between the spacer in the related art, in which the nickel plating layer 220 is applied onto the composite material layer 210, and the semiconductor chip on which a thin metal layer is applied, that is, in a case in which a high-temperature state (e.g., at a temperature of about 120° C. to 175° C.) is maintained, an intermetallic compound is formed as tin (Sn), which is a main component of the joining material, and the metal layer on the surface of the semiconductor chip react with each other and intermetallic diffusion occurs.

(14) In this regard, because the metal layer applied onto the surface of the semiconductor chip is configured as a thin film, the metal layer may be easily exhausted in the case in which the high-temperature state is maintained as described above. According to an exemplary embodiment of the present disclosure, the thin metal layer on the semiconductor chip may include a nickel layer of several micrometers (μm) and a precious metal layer made of gold (Au) or the like and having a level of nanometer (nm). When the joining material is melted in the high-temperature state, the precious metal layer completely disappears into the joining material, and thereafter, the nickel layer serves as a main reaction layer that reacts with the joining material.

(15) Consequently, the intermetallic compound is formed as the thin metal layer on the surface of the semiconductor chip reacts with the joining material due to the heat produced from the semiconductor chip, and the metal layer on the surface of the semiconductor chip is completely exhausted, which causes a problem of a deterioration in electrical characteristics and durability of the semiconductor chip.

(16) As a solution for this problem, a spacer structure according to an exemplary embodiment of the present disclosure, on which underlying plating is performed and then copper plating is additionally performed, is proposed, as illustrated in FIG. 3A. The underlying plating is performed to ensure a close-contact force between the spacer and the copper plating layer, and the joining material reacts with a copper plating layer instead of an underlying plating layer.

(17) The spacer structure according to an exemplary embodiment of the present disclosure illustrated in FIG. 3A will be more specifically described below.

(18) The spacer according to an exemplary embodiment of the present disclosure is a component configured to connect the insulating substrate and the semiconductor chip of the double-sided-cooled power module. A cross-sectional structure of the spacer will be described with reference to FIG. 3A. The spacer includes a conductive material layer 310 made of a composite material, an underlying plating layer 320 applied onto the conductive material layer 310, and a copper plating layer 330 applied onto the underlying plating layer 320. The copper plating layer 330, which is disposed at an outermost peripheral portion of the cross-sectional structure of the spacer, is in contact with the joining material configured to join the spacer to the semiconductor chip and the insulating substrate.

(19) In particular, the conductive material layer 310 of the spacer may be made of an electrically conductive material that enables an electric current to flow therethrough, that is, a material having excellent thermal conductivity. In addition, according to an exemplary embodiment of the present disclosure, the underlying plating layer 320 may be made of metal to ensure the close-contact force between the conductive material layer 310 and the copper plating layer 330. For example, the underlying plating layer 320 may be made of any one of nickel (Ni), titanium (Ti), chromium (Cr), and cobalt (Co).

(20) In particular, the copper plating layer 330 may have a thickness of 5 μm or more. In addition, according to an exemplary embodiment of the present disclosure, an outer periphery of the copper plating layer 330 may be plated with an additional metal layer to prevent oxidation and improve wettability with the joining material. For example, the outer periphery of the copper plating layer 330 may be additionally plated with a metal layer made of any one of gold (Au), silver (Ag), and palladium (Pd).

(21) According to the spacer structure according to an exemplary embodiment of the present disclosure illustrated in FIG. 3A, it is possible to solve the problem of the deterioration in electrical characteristics and durable life of the semiconductor chip which occurs on the spacer structure in the related art as described above with reference to FIGS. 2A and 2B. This configuration will be described below with reference to FIG. 3B.

(22) FIG. 3B is a schematic view illustrating a reaction process between the joining material and the metal layer at the joint portion between the semiconductor chip and the spacer structure according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 3B, in the case in which heat is produced from the semiconductor chip as the power module operates in the state in which the joining material is disposed between the spacer according to an exemplary embodiment of the present disclosure, in which the underlying plating layer 320 and the copper plating layer 330 are applied onto the conductive material layer 310, and the semiconductor chip on which the thin metal layer is applied, that is, in the case in which a high-temperature state (e.g., at a temperature of about 120° C. to 175° C.) is maintained, tin (Sn), which is a main component of the joining material, reacts not only with the metal layer (e.g., the nickel plating layer) on the surface of the semiconductor chip but also with the copper plating layer 330 of the spacer. Therefore, an intermetallic compound is formed as intermetallic diffusion occurs between the joining material and the semiconductor chip and between the joining material and the spacer.

(23) However, unlike the case in which the metal layer on the semiconductor chip is exhausted as the intermetallic compound is formed between the joining material and the metal layer on the surface of the semiconductor chip as described above with reference to FIG. 2B in which the spacer (illustrated in FIG. 2A) in the related art is used, a reaction speed between the joining material and the copper plating layer of the spacer is significantly higher than a reaction speed between the joining material and the thin metal layer (e.g., the nickel plating layer) of the semiconductor chip in the case of FIG. 3B in which the spacer (illustrated in FIG. 3A) according to an exemplary embodiment of the present disclosure is used, such that the copper plating layer of the spacer preferentially reacts with the joining material, as a result, the reaction between the joining material and the thin metal layer of the semiconductor chip is inhibited. The reaction speed, which is inhibited as described above, also inhibits the exhaustion of the thin metal layer of the semiconductor chip. That is, the thin metal layer of the semiconductor chip is not completely exhausted even though a reaction layer is formed between the joining material and the thin metal layer of the semiconductor chip. Consequently, since the exhaustion of the thin metal layer of the semiconductor chip is inhibited, it is possible to solve the problem of the deterioration in electrical characteristics of the semiconductor chip in the high-temperature environment.

(24) FIG. 4 is a schematic view illustrating a method of joining the double-sided-cooled power module according to an exemplary embodiment of the present disclosure. The joining method will be specifically described below.

(25) Referring to FIG. 4, the joining of the double-sided-cooled power module according to an exemplary embodiment of the present disclosure may be performed through the following processes.

(26) First, a first half-finished product 420 is formed by coupling a lower insulating substrate 421 to a jig, disposing a first joining material 422 and a semiconductor chip 423 on the lower insulating substrate 421, and then performing soldering. Thereafter, a second half-finished product 410 is formed by coupling an upper insulating substrate 411 to a jig, disposing a second joining material 412 and a spacer 413 on the upper insulating substrate 411, additionally disposing a third joining material 414 on the spacer 413, and then performing soldering. In this case, the spacer 413 may be a subsidiary material made by performing the underlying plating and the copper plating on the composite material according to an exemplary embodiment of the present disclosure. Finally, the first half-finished product 420 and the second half-finished product 410 are coupled to the jigs, respectively, and then soldering is performed.

(27) Referring to FIG. 4, the joining of the double-sided-cooled power module according to another exemplary embodiment of the present disclosure may be performed through the following processes.

(28) First, the first half-finished product 420 is formed by coupling the lower insulating substrate 421 to the jig, disposing the first joining material 422 and the semiconductor chip 423 on the lower insulating substrate 421, and then performing soldering. Thereafter, the second half-finished product 410 is formed by coupling the upper insulating substrate 411 to the jig, and disposing the second joining material 412 and the spacer 413 on the upper insulating substrate 411. In this case, the spacer 413 may be a subsidiary material made by performing the underlying plating and the copper plating on the composite material according to an exemplary embodiment of the present disclosure. Finally, the first half-finished product 420 and the second half-finished product 410 are coupled to the jigs, respectively, the third joining material 414 is inserted therebetween, and then soldering is performed.

(29) When comparing several samples made by joining the power modules in accordance with any one of the above-mentioned methods with an ideal state, changes in electrical characteristics are shown in the following Tables 1 and 2.

(30) Table 1 shows changes in electrical characteristics of the respective samples in the case in which the spacer in the related art illustrated in FIG. 4 is joined, and Table 2 shows changes in electrical characteristics of the respective samples in the case in which the spacer according to an exemplary embodiment of the present disclosure illustrated in FIG. 4 is joined.

(31) TABLE-US-00001 TABLE 1 Sample 1 Sample 2 Vce(sat)-H[V] 7.5%↑  13%↓ Vce(sat)-L[V] 25%↑ 15%↓ Vf-H[V] 32%↑ 20%↑ Vf-L[V]  9%↑ 34%↑

(32) TABLE-US-00002 TABLE 2 Sample Sample Sample Sample Sample 1 2 3 4 5 Vce(sat)-H[V] 2.15%↑ 2.46%↑ 2.08%↑ 1.85%↑ 2.15%↑ Vce(sat)-L[V] 1.00%↓ 0.69%↓ 0.92%↓ 1.00%↓ 0.15%↓ Vf-H[V] 2.35%↑ 2.35%↑ 1.35%↑ 1.65%↑ 2.71%↑ Vf-L[V] 1.82%↓ 2.18%↓ 2.65%↓ 2.41%↓ 1.59%↓

(33) When comparing Tables 1 and 2, it can be ascertained that the electrical characteristics are changed between 7.5% and 34% in the case in which the spacer in the related art is used, whereas the electrical characteristics are changed between 0.15% and 2.71% in the case in which the spacer according to an exemplary embodiment of the present disclosure is used. It can be ascertained that a change in electrical characteristics is inhibited in the case in which the spacer structure according to an exemplary embodiment of the present disclosure is used as described above, in comparison with the case in which the spacer structure in the related art is used. In other words, in the case in which the spacer structure according to an exemplary embodiment of the present disclosure is used, it is possible to solve the problem in the related art in that electrical characteristics of the semiconductor chip deteriorate or the semiconductor chip is burnt out.

(34) In addition, Table 3 shows thicknesses of the remaining metal layers on the surfaces of the semiconductor chips which are compared between the case in which the spacer structure according to an exemplary embodiment of the present disclosure is used after soldering the power module in accordance with any one of the methods described with reference to FIG. 4 and the case in which the spacer structure in the related art is used.

(35) TABLE-US-00003 TABLE 3 Related Present Art Disclosure Thickness of remaining 1.1 μm 1.5 μm chip metal layer after soldering

(36) As shown in Table 3, when the power module operates (i.e., the high-temperature state is maintained), the thickness of the remaining metal layer on the surface of the semiconductor chip is greater by approximately 0.4 μm in the case in which the spacer structure according to an exemplary embodiment of the present disclosure is used (about 1.5 μm) than in the case in which the spacer structure in the related art is used (about 1.1 μm). It can be ascertained that a loss of the metal layer on the surface of the semiconductor chip is inhibited in the case in which the spacer structure according to an exemplary embodiment of the present disclosure is used, in comparison with the case in which the spacer structure in the related art is used. In other words, in the case in which the spacer structure according to an exemplary embodiment of the present disclosure is used, the exhaustion of the metal layer on the semiconductor chip is inhibited, and as a result, it is possible to solve the problem of a reduction in durable life of the semiconductor chip in the related art.

(37) While the present disclosure has been described in detail above with reference to the exemplary embodiments, those skilled in the art to which the present disclosure pertains will understand that the exemplary embodiment may be variously modified without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure should not be limited to the described exemplary embodiment, but should be defined not only by the appended claims but also by all changes or modified forms derived from an equivalent concept to the claims.