Nanowire light emitting switch devices and methods thereof

Abstract

A nanowire system includes a substrate and at least one nanowire structure which extends out along an axis from a surface of the substrate. The nanowire structure comprises a light emitting diode and a device driver electrically coupled to control an operational state of the light emitting diode. The light emitting diode and the device driver are integrated to each share at least one doped region.

Claims

1. A nanowire system comprising: a substrate; at least one nanowire structure which extends out along an axis from a surface of the substrate, the nanowire structure comprising: a light emitting diode; and a device driver electrically coupled to the light emitting diode to control an operational state of the light emitting diode; wherein a cathode region of the light emitting diode and a drain region of the device driver are integrated to each share at least one doped region and that comprises an electron rich drain region for the device driver, an anode region of the light emitting diode is electrically coupled to the at least one doped region, and an electron deficient channel region of the device driver is electrically coupled between an electron rich source region and the at least one doped region.

2. The system as set forth in claim 1 wherein the shared at least one doped region comprises a GaN layer.

3. The system as set forth in claim 2 wherein the anode region is electrically coupled to the GaN layer that comprises the cathode region and the channel region is electrically coupled between the source region and the GaN layer that comprises the drain region.

4. The system as set forth in claim 3 wherein the source region and the channel region each comprise another GaN layer.

5. The system as set forth in claim 2 wherein the cathode region of the light emitting diode and the drain region of the device driver share a common external connectivity.

6. The system as set forth in claim 1 wherein a maximum cross sectional dimension of the at least one nanowire structure is less than about 10 microns.

7. The system as set forth in claim 1 wherein a maximum cross sectional dimension of the at least one nanowire structure is less than about 3 microns.

8. The system as set forth in claim 1 further comprising a Ni-based metal drain contact and a Ti-based metal layer adjacent to and electrically connected to the source region.

9. The system as set forth in claim 1 wherein the light emitting diode further comprises one or more layers of material on a light emitting portion of the light emitting diode that alter a spectral emission.

10. The system as set forth in claim 9, wherein the one or more layers comprises a color converter.

11. A nanowire system comprising a substrate; at least one nanowire structure which extends out along an axis from a surface of the substrate, the nanowire structure comprising: a light emitting diode; a device driver electrically coupled to the light emitting diode to control an operational state of the light emitting diode; wherein a cathode region of the light emitting diode and a drain region of the device driver are integrated to each share at least one doped region, an anode region of the light emitting diode is electrically coupled to the at least one doped region, and a channel region of the device driver is electrically coupled between a source region and the at least one doped region; and a gate metal layer electrically coupled to at least a portion of a periphery of the channel region of the device driver.

12. A nanowire system comprising: a substrate; two or more nanowire structures which each extend out along a separate axis from a surface of the substrate, each of the nanowire structures comprising: a light emitting diode; a device driver electrically coupled to the light emitting diode to control an operational state of the light emitting diode, wherein a cathode region of the light emitting diode and a drain region of the device driver are integrated to each share at least one doped region and wherein a source region of the device driver for two or more of the nanostructures is a shared source region; and a gate metal layer electrically coupled with a channel region of two or more nanowire structures.

13. The system as set forth in claim 12 further comprising a transparent conductive film layer that electrically couples together a plurality of adjacent nanowire structures.

14. The system as set forth in claim 13, wherein the plurality of adjacent nanowire structures is electrically coupled by both the transparent conductive film layer and the gate metal layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a cross-sectional view of an example of a nanowire array system with a plurality of nanowire light emitting switch devices;

(2) FIG. 1B is a partially cutaway and partially perspective view of a portion of the nanowire array system shown in FIG. 1A

(3) FIG. 1C is a perspective view of an example of one of the nanowire light emitting switch devices shown in FIGS. 1A-1B;

(4) FIGS. 2A-2F are perspective views of an example of a method of making an example of the nanowire array system;

(5) FIG. 3 is a cross-sectional view of another example of the nanowire array system illustrating another fabrication technique; and

(6) FIG. 4 is a cross-sectional view of yet another example of the nanowire array system illustrating yet another fabrication technique.

DETAILED DESCRIPTION

(7) An example of a nanowire array system 20(1) is illustrated in FIGS. 1A-1C. The nanowire array system 20(1) includes a plurality of spaced apart nanowire light emitting switch devices 11, conductive layers 12, 13, and 14, insulating layers 16, and a substrate 17, although the system may include other types and/or numbers of systems, devices, components, layers, regions or other elements in other configurations. This technology provides a number of advantages including providing one or more energy efficient and reliable nanowire light emitting switch devices whose single axis oriented and integrated shared layer structure enables a high pixel density array to be easily fabricated.

(8) Referring more specifically to FIGS. 1A-1B, in this example of the nanowire array system 20(1) the substrate 17 comprises a layer of Al.sub.2O.sub.3 (sapphire), although other types and/or numbers of substrates may be used, such as SiC (silicon carbide) substrate or silicon (Si) substrate by way of example only.

(9) The conductive layers 12, 13, and 14 each comprise a metal layer, although each of the conductive layers may comprise other types and/or numbers of conductive layers and/or other materials. In this example, the conductive layer 12 forms a drain contact layer located on an end of each of the spaced apart nanowire light emitting switch devices 11, although other types and/or numbers of conductive layers in other configurations may be used. Additionally, in this example, the conductive layer 13 forms a source contact layer located adjacent another end of each of the spaced apart nanowire light emitting switch devices 11, although other types and/or numbers of conductive layers in other configurations may be used. Further, in this example, the conductive layer 14 forms a gate metal contact layer located around at least a portion of channel region 7 of each of the spaced apart nanowire light emitting switch devices 11, although other types and/or numbers of conductive layers in other configurations may be used.

(10) A transparent conductive film (TCF) 15 comprises another conductive layer which may be formed to couple together one or more of the conductive layers 12 for one or more of the spaced apart nanowire light emitting switch devices 11, although other types and/or numbers of conductive layers in other configurations may be used. As illustrated in cross-sectional view in FIG. 1A, the spaced apart nanowire light emitting switch devices 11 may for example with the transparent conductive film (TCF) 15 couple three separate conductive layers 12 for three nanowire light emitting switch devices 11.

(11) The size, density, and brightness of pixels in a pixel array formed in this example by the spacing of the light emitting switch devices 11, also referred to a nanowire structures or nanowires in examples herein, can also be changed by varying the widths of conducting layers 14 and conducting layers 15 to increase or decrease the number of light emitting switch devices 11 functioning as a single display pixel. FIG. 1B illustrates an example of multiple light emitting switch devices 11 that share conducting layers 14 and conducting layers 15.

(12) A transparent insulator 16 is located between the conductive layer 13 and conductive layer 14 and between the conductive layer 13 and at least a portion of the transparent conductive film (TCF) 15 and about a corresponding portion of each of the spaced apart nanowire light emitting switch devices 11, although other types and/or numbers of insulating layers in other configurations may be used.

(13) Referring more specifically to FIGS. 1A-1C, the spaced apart nanowire light emitting switch devices 11 each comprise light emitting diode (LED) layers 8, 9, and 10 and a field effect transistor (FET) or other device driver or switch comprising layers 6, 7, and 8, although each of the devices may comprise other types and/or numbers of other layers, regions, or other elements. In this example, the FET is coupled to control an operational state, i.e. an on state or an off state in this example, of the LED in each nanowire light emitting switch device 11, although other types of drivers or switches may be used. Additionally, in this example, the LED and the FET advantageously share a layer or other doped region 8 to help minimize lost space from prior positioning of the device driver or switch adjacent the LED taking up valuable real estate. Further, in this example the LED and the FET advantageously are each constructed to extend out from the substrate 17 along a single axis to enable a much more compact narrow design enabling closer spacing of the nanowire light emitting switch devices 11 so that much higher resolution can be achieved, although other configurations may be used.

(14) Each pixel made by one or more of the light emitting switch devices 11 also can have the brightness modulated through the inclusion of the device driver which in this example is the FET of the light emitting switch devices 11. Brightness levels can for example be changed through electrical biases to conductive layer 14 and/or conductive layer 15.

(15) The layer 6 of the field effect transistor (FET) or other device driver or switch is an electron rich source region for the FET that is grown or otherwise formed on the substrate 17, although other types of source regions may be used. In this particular example, the layer 6 is an unintentionally doped (u-GaN) buffer layer, although again other types of source regions may be used, such as an n-type GaN layer by way of example only. The u-GaN buffer layer 6 as the electron rich source region for the FET is possible due to the high electron concentration of 10.sup.17 cm.sup.−3-10.sup.20 cm.sup.−3, from O.sub.2 and defect incorporation.

(16) The layer 7 of the field effect transistor (FET) or other device driver or switch is an electron deficient channel region for the FET that is grown or otherwise formed on the layer 6, although other types of channel regions may be used. In this particular example, the layer 7 is a thicker layer of u-GaN than the source region 6, although again other types of channel regions may be used, such as a p-type GaN layer. Use of this thicker u-GaN layer 7 as the electron deficient channel region for the FET is possible due to intrinsic nitrogen vacancies in the material, making the layer slightly n-type.

(17) The layer 8 of the field effect transistor (FET) or other device driver or switch is an electron rich drain region for the FET that is grown or otherwise formed on the layer 7, although other types of source regions may be used. In this particular example, the layer 8 is an n-type GaN layer, although again other types of drain regions may be used. This layer 8 is shared between the FET and LED of the nanowire light emitting switch device 11 and acts as an electron rich layer of the LED. In this particular example, the GaN layer for layer 8 comprises a cathode region of the LED and a drain region of the FET or other device driver.

(18) The layer 9 is a multiple quantum well (MQW) region 9 with for example InGaN or AlGaN quantum wells and GaN or AlGaN barriers for the LED that efficiently generate light, although other types of layers and/or wells and other barriers may be used. More specifically, in this example light emission from the LED makes use of this layer 9 which is a multiple quantum well (MQW) region, where layers of Indium Gallium Nitride (InGaN) or Aluminum Gallium Nitride (AlGaN) are confined between layers of GaN or AlGaN in order to trap electron-hole pairs for the generation of light. In other examples, one or more other layers of material may be on layer 9 that alter a spectral emission. By way of a further example, one or more of the additional layers may comprise a color converter.

(19) The layer 10 is a p-GaN region 10 or anode region for the LED, although again other types of regions and other configurations for the regions of the LED may be used. This layer 10 with layers 8 and 9 complete this example of the LED of each of the nanowire light emitting switch devices 11. Accordingly, in this example, the LED and FET are connected in series with a shared layer 8 and with the FET being able to switch the LED between “on” or “off” operational states.

(20) As illustrated in the example above, each of the layers of the FET and LED may be advantageously formed from the same material, e.g. GaN based material, which reduces the number of materials required for manufacturing providing resulting efficiencies. Additionally, the GaN based material in the LED light emitting region and FET (driver or switch) is intrinsically transparent and, when combined with a select choice of one or more metals, the array system can be made optically transparent. This optical transparency enables examples of this technology to be used in a number of new applications, such as various different types of display technologies including for example augmented reality displays. This optical transparency and single axis oriented structure for the nanowire light emitting switch device 11 enables the generation of flexible display devices for use in wearable and otherwise curved electronics.

(21) Referring to FIGS. 2A-2F, an example of a method of making the example of the nanowire array system is illustrated. As illustrated by way of the example below, fabrication of this integrated LED-FET device may employ fabrication techniques readily available in the semiconductor industry, allowing easy adoption of this technology. More specifically, examples of the claimed technology may make use of conventionally grown LED layers, using a metal organic chemical vapor deposition (MOCVD) tool in wide commercial use.

(22) Referring more specifically to FIG. 2A, first an electron rich source layer or region 6 is grown on the substrate 17, which again could in these examples be either an unintentionally doped (u-GaN) buffer layer or an n-type GaN layer. As discussed earlier, use of a u-GaN buffer layer is possible due to the high Electron concentration of 10.sup.17 cm.sup.−3-10.sup.20 cm.sup.−3, from O.sub.2 and defect incorporation. Additionally, in this example the substrate 17 is Al.sub.2O.sub.3 (sapphire), although in other types of substrates may be used, such as a SiC (silicon carbide) substrate or a silicon (Si) substrate.

(23) Next an electron deficient channel layer or region 7 is grown on layer or region 6 which again can be a thicker layer of u-GaN than used for layer or region 6 or a p-type GaN layer. Use of a thicker u-GaN layer as the electron deficient channel region 7 is possible due to intrinsic nitrogen vacancies in the material, making the layer slightly n-type.

(24) Next, the electron rich layer 8 is grown or otherwise formed on the layer 7. The bottom electron rich source region 6, the electron deficient channel region 7, and the n-GaN drain region 8 create the required structure for this example of a FET for each of the nanowire light emitting switch devices 11. As discussed below, this layer 8 is shared by the FET with the LED of this example of the nanowire light emitting switch devices 11.

(25) Next, to form the LED comprising layers 8, 9, and 10 for this example of each of the nanowire light emitting switch devices 11, a multiple quantum well (MQW) region 9 with InGaN or AlGaN quantum wells and GaN or AlGaN barriers that efficiently generate light is formed on the shared layer or region 8.

(26) Next, a p-GaN region 10 is formed on the multiple quantum well (MQW) region 9 for the LED for 10 for this example of each of the nanowire light emitting switch devices 11. Accordingly, in this example, the LED comprising layers 8, 9, and 10 and the FET comprising layers 6, 7, and 8 are connected in series with a shared layer 8 and with the FET coupled to be able to switch the LED between “on” or “off” operational states. The shared electron rich initial layer again functions both as the cathode for the LED and the drain region for the FET for each of the nanowire light emitting switch devices 11 in this example.

(27) Next, an exposed surface of the p-GaN layer 10 may be patterned through a metal lift-off process to deposit Ni or other conductive material, which both acts as the ohmic p-type GaN contact for layer or region 12 and as the hard mask for the chlorine based dry etch as shown in FIG. 2A-2B. The nanowires 11 can then undergo an optional anneal in O.sub.2 to create NiO for a more ohmic contact to the p-GaN layer or region 12.

(28) Next, the chlorine based dry etch can be used in order to selectively remove material to leave nanowire light emitting switch devices 11 which each extend along a single axis out from the substrate 17 as shown in FIG. 2B.

(29) Next a Ti based or other conductive material metallization is thermally evaporated, coating just the tips of the nanowire light emitting switch devices 11 and base as shown in FIG. 2C. An optional anneal may then be performed to generate TiN from the metal, further increasing the n-type nature of the u-GaN buffer layer or region 6.

(30) After the metal deposition a transparent insulator 16 is then coated and etched back to uncover everything above the upper boundary of the electron rich source region or layer 6 as shown in FIG. 2D. The insulator 16 acts as a spacer to separate the metal or conductive layers 13 and 14 from each other.

(31) Next, lines of metal for the gate layer 14 are then patterned with a lift-off process. Metals, such as Ni are thermally evaporated coating the tops of the nanowire light emitting switch devices 11 with the conductive layer or wire 12 and the insulator 16, forming the layer 14 comprising a gate-all-around coupling to the u-GaN region as shown in FIG. 2D. Accordingly, examples of the claimed technology may wrap the gate around at least a portion of the channel region or layer 7 of each of the nanowire light emitting switch devices 11 which provides fast switching and lowers power consumption when in an “off” operational state.

(32) Next, more optically transparent insulation 16 may then be coated and etched back to reveal just the tips of the wires 12. Lift-off may again be used to pattern lines of a transparent conductive film (TCF) 15 to form the top interconnects 15 as shown in FIG. 2E.

(33) As a final step, the insulator 16 may be selectively etched away to expose the buried metal or conductive layers 13 and 14 for external connection as shown in FIG. 2F.

(34) A variety of alternative choices may be used with each of these steps, such as using choices for the gate metal or conductive layer 14 besides Ni by way of example only. In other examples, a gate insulator along the nanowire sides may be alternatively integrated. One of the advantages of this method is that this layer by layer fabrication enables precise control over and customization of the final design and layout. Another advantage as noted earlier is this technology is able to utilize existing fabrication methodologies.

(35) The device layout illustrated in this particular layout creates a cross design in order to selectively address individual nanowires 11 for display purposes. In this example, the source metal or conductive layer 13 is common to all nanowires, acting as a common ground connection, while the gate metal or conductive layer 14 and drain metal or conductive layer 15 are alternatively addressed in rows and columns.

(36) An example of a method for operating one of the nanowire light emitting switch devices 11 in a nanowire array system will now be described with reference to FIGS. 1A-1C. When the gate layer 14 of the FET the nanowire light emitting switch devices 11 is energized, then electrons flow from the source region 6 through the channel region 7 into the shared drain region 8 to turn the FET and LED to an “on” operational state. From the shared drain region 8, the electrons flow through the LED to recombine with holes in the MQW region 9 to produce light. The drain contact layer 8 forward biases the LED 8-10 that is in series with the FET 6-8 allowing for a positive source to drain bias for FET operation.

(37) Referring to FIG. 3, an alternative method of fabricating nanowire light emitting switch devices 11 in a nanowire array system 20(2) is shown. This method is the same as illustrated and described with reference to FIGS. 2A-2F except as otherwise illustrated or described by way of the examples herein. In this example, this method of fabrication utilizes a bottom-up growth technique through use of an insulating layer 16 for selective area growth. Selective area growth of the nanowire light emitting switch devices 11 can allow for separate growths to occur to create nanowire light emitting switch devices 11 that each emit distinct colors. Variations in the opening size of the insulating layer 16 can be used with a single growth process in order to create as-grown nanowire light emitting switch devices 11 which emit distinct colors.

(38) Referring to FIG. 4, an alternative method of fabricating nanowire light emitting switch devices 11 in a nanowire array system 20(3) is shown. This method is the same as illustrated and described with reference to FIGS. 2A-2F except as otherwise illustrated or described by way of the examples herein. In this example, this method of fabrication, the MQW region 9 and p-type region 10 of the grown LED can wrap around a portion of shared n-GaN region 8.

(39) As illustrated and described by way of the examples herein, examples of the claimed technology may be utilized for a variety of different types of application. For example, the claimed technology can be used for a variety of different types of display technologies from smart watches, to TVs, to phones. The nanowire light emitting switch devices 11, each being the individual pixels, can be advantageously spaced to provide much higher resolution.

(40) In other examples, the claimed technology can be used to replace typical display technology, due to the transparent nature discussed earlier. As a result, examples of the claimed technology work exceedingly well in creating heads-up display technology. Additionally, by way of another example, current heads-up displays rely on a bulky projector, where examples of this claimed technology would eliminate this need. The display made from examples of this claimed technology would be the transparent eyepiece itself without the need for any projectors.

(41) In yet other examples, the nanowire nature of the nanowire light emitting switch devices 11 allows for flexibility which opens up other opportunities relating to flexible displays. In particular, the wire structure of the nanowire light emitting switch devices 11 allows them to tolerate the stress of flexing and mechanical motion.

(42) Having thus described the basic concept of the invention, it will be rather apparent to those skilled in the art that the foregoing detailed disclosure is intended to be presented by way of example only, and is not limiting. Various alterations, improvements, and modifications will occur and are intended to those skilled in the art, though not expressly stated herein. These alterations, improvements, and modifications are intended to be suggested hereby, and are within the spirit and scope of the invention. Additionally, the recited order of processing elements or sequences, or the use of numbers, letters, or other designations therefore, is not intended to limit the claimed processes to any order except as may be specified in the claims. Accordingly, the invention is limited only by the following claims and equivalents thereto.