METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE

Abstract

A method of manufacturing a thin film transistor (TFT) substrate and a TFT substrate. The method of manufacturing the TFT substrate adopts a first gate and a second gate to form a double gate structure, and uses a silicon nitride layer to form a etch stop layer. When depositing the silicon nitride layer of the etch stop layer, hydrogen atoms in the silicon nitride layer diffuse into the active layer to form a doping in the active layer. The hydrogen atoms provide a large amount of electrons as a donor, which increases an electron mobility of a channel region with low impedance and further reduces the impedance. Thus, a TFT channel series structure is formed in the channel region. A double TFT structure is realized by an ion diffusion doping, which saves costs and effectively saves space and optimizes a spatial layout in practical use.

Claims

1. A method of manufacturing a thin film transistor (TFT) substrate, comprising: a step S1 of providing a substrate, forming a first gate and a second gate spaced apart from each other on the substrate, depositing a gate insulating layer on the first gate, the second gate, and the substrate, and depositing and patterning to form an active layer on the gate insulating layer and corresponding to the first gate and the second gate; a step S2 of depositing an etch stop layer on the active layer and the gate insulating layer, the etch stop layer comprising a silicon nitride layer, when depositing the silicon nitride layer of the etch stop layer, hydrogen atoms in the silicon nitride layer diffuse into the active layer, so as to reduce impedance of the active layer; and a step S3 of depositing and patterning to form a source and a drain on the etch stop layer.

2. The method according to claim 1, wherein in the step S2, the silicon nitride layer of the etch stop layer is deposited by a plasma chemical vapor deposition.

3. The method according to claim 1, wherein in the step S1, the active layer is deposited by electroplating and splashing, and a material of the active layer comprises a metal oxide semiconductor.

4. The method according to claim 1, wherein the step S1 further comprises performing a plasma doping treatment on both sides of the active layer, such that a conductivity on the both sides of the active layer is enhanced to form a source contact region and a drain contact region at both ends of the active layer, and a region between the source contact region and the drain contact region is formed as a channel region; the step S2 further comprises patterning the etch stop layer, and the etch stop layer forms a first via and a second via respectively over the source contact region and the drain contact region of the active layer; and in the step S3, the source and the drain contact the source contact region and the drain contact region through the first via and the second via respectively.

5. The method according to claim 1, wherein the etch stop layer further comprises a silicon oxide layer between the silicon nitride layer and the active layer.

6. The method according to claim 1, wherein when the TFT substrate is in use, voltages on the first gate and the second gate are independently controlled.

7. A thin film transistor (TFT) substrate, comprising: a substrate, a first gate, and a second gate spaced apart from each other on the substrate, a gate insulating layer on the first gate, the second gate, and the substrate, an active layer disposed on the gate insulating layer and corresponding to the first gate and the second gate, an etch stop layer disposed on the active layer, and a source and a drain disposed on the etch stop layer; wherein the etch stop layer comprises a silicon nitride layer, and hydrogen atoms in the silicon nitride layer diffuse into the active layer, so as to reduce impedance of the active layer.

8. The TFT substrate according to claim 7, wherein a material of the active layer comprises a metal oxide semiconductor; both sides of the active layer are respectively a source contact region and a drain contact region which are enhanced in a conductivity by a plasma doping treatment, and a region between the source contact region and the drain contact region is formed as a channel region; and the etch stop layer is respectively provided with a first via and a second via respectively over the source contact region and the drain contact region of the active layer, and the source and the drain contact the source contact region and the drain contact region through the first via and the second via respectively.

9. The TFT substrate according to claim 7, wherein the etch stop layer further comprises a silicon oxide layer between the silicon nitride layer and the active layer.

10. The TFT substrate according to claim 7, wherein when the TFT substrate is in use, voltages on the first gate and the second gate are independently controlled.

Description

DESCRIPTION OF DRAWINGS

[0026] For a better understanding of the features and technical contents of the present disclosure, please refer to the following detailed description and figures of the present disclosure. However, the figures are only for reference and illustration, and are not intended to limit the present disclosure.

[0027] Combined with the following attached figures, by detailed description of the specific embodiments of the present disclosure, the technical solution and other beneficial performances of the present disclosure will be obvious.

[0028] FIG. 1 is a schematic structural diagram of a current ESL type thin film transistor (TFT) substrate.

[0029] FIG. 2 is a flowchart of a method of manufacturing a TFT substrate according to an embodiment of the present disclosure.

[0030] FIG. 3 is a schematic diagram of step S1 of a method of manufacturing a TFT substrate according to an embodiment of the present disclosure.

[0031] FIG. 4 is a schematic diagram of a step S2 of a method of manufacturing a TFT substrate according to an embodiment of the present disclosure.

[0032] FIG. 5 is a schematic diagram of step S3 of a method of manufacturing a TFT substrate and a schematic structural diagram of a TFT substrate according to an embodiment of the present disclosure.

[0033] FIG. 6 is a schematic overhead diagram of a TFT substrate according to an embodiment of the present disclosure.

[0034] FIG. 7 is a circuit diagram of a TFT substrate according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0035] In order to further clarity the technical means and performances of the present disclosure, the following is described in detail in connection with the embodiments of the present disclosure and the accompanying figures.

[0036] Referring to FIG. 1, an embodiment of the present disclosure provides a method of manufacturing a thin film transistor (TFT) substrate. The method includes the following steps:

[0037] Referring to FIG. 2, in a step S1, provide a substrate 10 and form a first gate 21 and a second gate 22 spaced apart from each other on the substrate 10. Deposit a gate insulating layer 30 on the first gate 21, the second gate 22, and the substrate 10. Deposit and pattern to form an active layer 40 on the gate insulating layer 30 corresponding to the first gate 21 and the second gate 22. Perform a plasma doping treatment on both sides of the active layer 40, such that a conductivity on the both sides of the active layer 40 is enhanced to form a source contact region 41 and a drain contact region 42 at both ends of the active layer 40, and a region between the source contact region 41 and the drain contact region 42 is formed as a channel region 43.

[0038] In details, materials of the first gate 21 and the second gate 22 include metal materials, such as one or more alloys of molybdenum, aluminum, copper and titanium.

[0039] In details, in the step S1, patterning to form the first gate 21, the second gate 22, and the active layer 40 includes photoresist coating, exposure, development, etching, and photoresist removal. The etching of the first gate 21 and the second gate 22 is wet etching, and the etching of the active layer 40 is dry etching.

[0040] In details, the material of the active layer 40 formed in the step S1 includes an indium gallium zinc oxide, and can also be a metal oxide semiconductor material such as an indium gallium selenium oxide.

[0041] In details, materials of the gate insulating layer 30 include one or a combination of silicon oxide (SiOx) and silicon nitride (SiNx). Preferably, the materials of the gate insulating layer 30 include a silicon oxide.

[0042] In details, in the step S1, the gate insulating layer 30 is deposited by a chemical vapor deposition (CVD).

[0043] In details, the active layer 40 is deposited by electroplating and splashing.

[0044] In details, perform a N-type plasma doping treatment on the both sides of the active layer 40, that is, the source contact region 41 and the drain contact region 42 are both n+IGZO regions which are conductive by the N-type plasma doping treatment.

[0045] Referring to FIG. 3, in a step S2, deposit the etch stop layer 50 on the active layer 40 and the gate insulating layer 30. The etch stop layer 50 includes a silicon nitride layer 51. When depositing the silicon nitride layer 51 of the etch stop layer 50, hydrogen atoms in the silicon nitride layer 51 diffuse into the active layer 40 so as to reduce impedance of the active layer 40.

[0046] In details, the silicon nitride layer 51 of the etch stop layer 50 is deposited by a plasma chemical vapor deposition (PECVD). In this process, the hydrogen atoms in the silicon nitride layer 51 diffuse into the active layer 40. The hydrogen atoms provide a large amount of electrons as a donor, which increases an electron mobility of the channel region 43 with low impedance and further reduces the impedance. Thus, a TFT channel series structure is formed in the channel region 43, which reduces a channel impedance of the first gate 21 and the second gate 22 on the both sides, and shortens a channel length.

[0047] In details, the step S2 further includes patterning the etch stop layer 50, and the etch stop layer 50 forms a first via 501 and a second via 502 respectively over the source contact region 41 and the drain contact region 42 of the active layer 40.

[0048] In details, the etch stop layer 50 further includes a silicon oxide layer 52 between the silicon nitride layer 51 and the active layer 40.

[0049] Referring to FIG. 4, in a step S3, deposit and pattern a source 61 and a drain 62 on the etch stop layer 50. The source 61 and the drain 62 contact the source contact region 41 and the drain contact region 42 through the first via 501 and the second via 502 respectively.

[0050] In the method of manufacturing a TFT substrate of the embodiment present disclosure, firstly the first gate 21 and the second gate 22 are formed on the substrate 10 and are spaced apart from each other, and the first gate 21 and the second gate 22 form a double gate structure. Then the gate insulating layer 30, the active layer 40, the etch stop layer 50, the source 61 and the drain 62 are sequentially formed. The etch stop layer 50 includes the silicon nitride layer 51. When depositing the silicon nitride layer 51 of the etch stop layer 50, the hydrogen atoms in the silicon nitride layer 51 diffuse into the active layer 40 and form a doping in the active layer 40. The hydrogen atoms provide a large amount of electrons as a donor, which increases the electron mobility of the channel region 43 with low impedance and further reduces the impedance. Thus, a TFT channel series structure is formed in the channel region 43, which reduces the impedance of the both sides of the channel. Referring to FIG. 6, the channel length is shortened, the electron mobility is improved, and the power consumption is reduced. L is an original channel length, D is an equivalent channel length after adding a double TFT structure. Referring to FIG. 7, without changing a yellow light processing equipment, the double TFT structure is realized by an ion diffusion doping, which saves costs. In addition, a first voltage Vg1 and a second voltage Vg2 are independently controlled, this is, the double TFT structure is independently controlled, which saves costs and effectively save spaces and optimizes a spatial layout in practical use.

[0051] Referring to FIG. 5, on the basis of the method of manufacturing a TFT substrate above, the embodiment of the present disclosure further provides a TFT substrate including a substrate 10, a first gate 21 and a second gate 22 spaced apart from each other on the substrate 10, a gate insulating layer 30 on the first gate 21, the second gate 22, and the substrate 10, an active layer 40 disposed on the gate insulating layer 30 and corresponding to the first gate 21 and the second gate 22, an etch stop layer 50 on the active layer 40, and a source 61 and a drain 62 on the etch stop layer 50.

[0052] A material of the active layer 40 is a metal oxide semiconductor. Both sides of the active layer 40 are respectively a source contact region 41 and a drain contact region 42 which are enhanced in a conductivity by a plasma doping treatment, and a region between the source contact region 41 and the drain contact region 42 is formed as a channel region 43.

[0053] The etch stop layer 50 is respectively provided with a first via 501 and a second via 502 respectively over the source contact region 41 and the drain contact region 42 of the active layer 40, and the source 61 and the drain 62 contact the source contact region 41 and the drain contact region 42 through the first via 501 and the second via 502 respectively.

[0054] The etch stop layer 50 includes a silicon nitride layer 51. Hydrogen atoms in the silicon nitride layer 51 diffuse into the active layer 40 to form a doping in the active layer 40. The hydrogen atoms provide a large amount of electrons as a donor, which increases an electron mobility of the channel region 43 with low impedance and further reduces the impedance. Referring to FIG. 6, a TFT channel series structure is formed in the channel region 43, which reduces the channel impedance corresponding to the first gate 21 and the second gate 22, and shortens a channel length. L is the original channel length, D is the equivalent channel length after adding a double TFT structure.

[0055] In details, a material of the active layer 40 is the metal oxide semiconductor, preferably IGZO.

[0056] The etch stop layer 50 further includes a silicon oxide layer 52 between the silicon nitride layer 51 and the active layer 52.

[0057] In details, a N-type plasma doping treatment is performed to both side of the active layer 40, that is, the source contact region 41 and the drain contact region 42 are both n+IGZO regions which are conductive by a N-type plasma doping.

[0058] In details, materials of the first gate 21 and the second gate 22 are metal materials, such as one or more alloys of molybdenum, aluminum, copper and titanium.

[0059] The TFT substrate of the embodiment of the present disclosure adopts the first gate 21 and the second gate 22 to form a double gate structure, and the silicon nitride layer 51 is disposed on the etch stop layer 50. When depositing the silicon nitride layer 51 of the etch stop layer 50, the hydrogen atoms in the silicon nitride layer 51 diffuse into the active layer 40 and form a doping in the active layer 40. The hydrogen atoms provide a large amount of electrons as a donor, which increases the electron mobility of the channel region 43 with low impedance, and further reduces the impedance. Thus, the TFT channel series structure is formed in the channel region 43, which reduces the impedance of both sides of the channel, shortens the channel length, improves the electron mobility, and reduces the power consumption. D is the equivalent channel length after adding the double TFT structure. Without changing a yellow light processing equipment, the double TFT structure is realized by an ion diffusion doping, which saves costs. In addition, the first voltage Vg1 and the second voltage Vg2 are independently controlled, this is, the double TFT structure is independently controlled, which saves costs and effectively saves space and optimizes a spatial layout in practical use. Table 1 below is a control logic table for controlling on/off a double channel of the TFT substrate of the present disclosure.

TABLE-US-00001 TABLE 1 Input Output Vg1 Vg2 Vout H H H H L L L H L L L L

[0060] In summary , in the method of manufacturing the TFT substrate of the embodiment of the present disclosure, the first gate and the second gate are formed on the substrate and are spaced apart from each other, and the first gate and the second gate form the double gate structure. Then the gate insulating layer, the active layer, the etch stop layer, the source, and the drain are sequentially formed. The etch stop layer includes the silicon nitride layer. When depositing the silicon nitride layer of the etch stop layer, the hydrogen atoms in the silicon nitride layer diffuse into the active layer, so as to form a doping in the active layer. The hydrogen atoms provide a large amount of electrons as a donor, which increases the electron mobility of the channel region with low impedance and further reduces the impedance. Thus, the TFT channel series structure is formed in the channel region, which reduces the impedance of both sides of the channel, shortens the channel length, improves the electron mobility, and reduces the power consumption. Without changing the yellow light processing equipment, the double TFT structure is realized by an ion diffusion doping, which saves costs and effectively saves space and optimizes a spatial layout in practical use. The TFT substrate of the embodiment of the present disclosure adopts the double gate structure and forms the TFT channel series structure in the channel region by diffusing and doping the hydrogen atoms in the silicon nitride layer to reduce the impedance of both sides of the channel, short the channel length, improve the electron mobility, and reduce the power consumption. Without changing the yellow light processing equipment, the double TFT structure is realized by the ion diffusion doping, which saves costs and effectively saves space and optimizes a spatial layout in practical use.

[0061] As mentioned above, for those of ordinary skill in the art, various corresponding changes and variations may be made according to the technical solution and technical conception of the present disclosure, and all these changes and variations are within the scope of the claims of the present disclosure.