Abstract
A high electron mobility transistor includes a set of electrodes, such as a source, a drain, a top gate, and a side gate, and includes a semiconductor structure having a fin extending between the source and the drain. The top gate is arranged on top of the fin, and the side gate is arranged on a sidewall of the fin at a distance from the top gate. The semiconductor structure includes a cap layer positioned beneath the top gate and a channel layer arranged beneath the cap layer for providing electrical conduction. The cap layer includes nitride-based semiconductor material to enable a heterojunction forming a carrier channel between the source and the drain.
Claims
1. A high electron mobility transistor, comprising: a set of electrodes including a source, a drain, a top gate, and a side gate; and a semiconductor structure having a fin extending between the source and the drain, wherein the top gate is arranged on top of the fin, wherein the side gate is arranged on a sidewall of the fin at a distance from the top gate making the top gate nonintegral with the side gate to prevent physical and electrical contacts between the side gate and the top gate, such that the top gate is configured to accept a first voltage independently from a second voltage applied to the side gate, and the side gate is configured to accept the second voltage independently from the first voltage applied to the side gate, wherein the semiconductor structure includes a cap layer positioned beneath the top gate and a channel layer arranged beneath the cap layer for providing electrical conduction, wherein the cap layer includes nitride-based semiconductor material configured to enable a heterostructure forming a carrier channel between the source and the drain, wherein the side gate has an L-shape, wherein a first leg of the L-shape is arranged on the sidewall of the fin, and wherein a second leg of the L-shape is substantially perpendicular to the first leg.
2. The transistor of claim 1, wherein the transistor includes two gates arranged on the opposite sidewalls of the fin.
3. The transistor of claim 2, wherein the side gate is made of semiconductor material.
4. The transistor of claim 3, wherein the semiconductor material of the side gate is p-doped semiconductor.
5. The transistor of claim 1, further comprising: a dielectric layer arranged between the top gate and the top surface of the fin, or between the side gate and the sidewall of the fin, or combination thereof.
6. The transistor of claim 1, wherein the semiconductor structure includes AlInGaN.
7. The transistor of claim 1, wherein a voltage applied to the top gate with respect to the source modulates the conductivity of a carrier channel between the source and the drain, and wherein a voltage applied to the side gate with respect to the source modulates a threshold voltage of the transistor.
8. The transistor of claim 7, wherein the voltage applied to the side gate is negative to move the threshold voltage towards a positive domain with respect to the source.
9. The transistor of claim 8, wherein an absolute value of the negative voltage applied to the side gate is proportional to a linearity of the transistor.
10. The transistor of claim 7, wherein the voltage applied to the side gate is positive to move the threshold voltage towards a negative domain with respect to the source.
11. The transistor of claim 1, wherein the width of the fin is less than 400 nm.
12. The transistor of claim 1, further comprising a ferroelectric oxide (FE) layer arranged between the side gate and the sidewall of the fin.
13. The transistor of claim 12, wherein the width of the fin is greater than 400 nm.
14. A method for controlling the transistor of claim 1, the method comprising: applying a voltage to the top gate with respect to the source to modulate the conductivity of a carrier channel between the source and the drain; and applying a voltage to the side gate with respect to the source to modulate a threshold voltage of the transistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 shows the 3-D schematic of a high electron mobility transistor (HEMT) according to some embodiments.
(2) FIG. 2 shows the cross section in the middle of the channel of the transistor according to one embodiment.
(3) FIG. 3 shows the energy band diagram 310 along the cross-section AA of the transistor of FIG. 2.
(4) FIG. 4A and FIG. 4B show the electron density cross section profile of transistors of o different embodiments.
(5) FIG. 5 shows the simulated I.sub.DS-V.sub.GS characteristics for different side gate voltages.
(6) FIG. 6 shows the variation of the threshold voltage with the side gate voltage for different fin thickness used by some embodiments.
(7) FIG. 7 shows the I.sub.DS-V.sub.DS characteristics for different side gate voltage (V.sub.SG) for 100 nm fin width transistor according to one embodiment.
(8) FIG. 8 shows a 2-D cross section is the middle of the channel of the transistor according to one embodiment.
(9) FIG. 9 shows a 2-D cross section in the middle of the channel of the transistor according to one embodiment.
(10) FIG. 10 shows a 2-D cross section in the middle of the channel of the transistor according to one embodiment.
(11) FIG. 11 shows a flow chart of a method for controlling the threshold voltage of the transistor according to various embodiments.
(12) FIG. 12 shows a block diagram of a method for fabricating a semiconductor device according to some embodiments.
DETAILED DESCRIPTION
(13) FIG. 1 shows the 3-D schematic of a high electron mobility transistor (HEMT) according to some embodiments. The transistor includes a semiconductor structure having a compound semiconductor heterostructure formed between a cap layer 101 and a channel layer 102 such that a two dimensional electron gas (2-DEG) 103 is formed at the interface of cap layer and channel layer. A source electrode 110 and a drain electrode 120 are put to make electrical connection with the said 2-DEG. The semiconductor structure has a fin 199 extending between the source and the drain to facilitate the placement of side wall gates labeled 140 and/or 150 on one or the two opposite sides of the fin in order to modulate the carrier density in the channel thus the threshold voltage. A top gate labeled 130 is placed on top of the cap layer to control the conductivity of the channel. On embodiments controls the threshold voltage by having only one side wall gate, however, alternative embodiments include two side gates to provide better controllability.
(14) FIG. 2 shows the cross section in the middle of the channel of the transistor according to one embodiment. In this embodiment, the side wall gates are L-shaped wherein the vertical leg of L-shaped side are placed in proximity to the fin side wall and the horizontal leg is just to facilitate the application of voltage to that gate.
(15) FIG. 3 shows the energy band diagram 310 along the cross-section AA of the transistor of FIG. 2. From this energy band diagram, some embodiments derive the equation for threshold voltage of a HEMT labeled 333. One thing to be noted from this equation is that threshold voltage has a linear relationship with the 2-DEG concentration. Therefore, it can be inferred that one can modulate the threshold voltage of a HEMT by modulating the 2-DEG density. Generally, because of high 2-DEG density the threshold voltage of a HEMT is negative making it a normally ON device. However, by depleting the 2-DEG it is possible to make the threshold voltage positive thereby making the device normally off. To modulate the 2-DEG density side wall gates are placed.
(16) FIG. 4A shows the electron density cross section profile for side gate voltage of 0 V used by some embodiments. Here the scale 410 is in log(Electron-Concentration). We can observe that the electron concentration is very high at the interface of 101 and 102 layer, and it decreases monotonically as me move away from the interface in both directions.
(17) FIG. 4B shows the electron density cross section profile for side gate voltage of 4 V. Compared to FIG. 4B the electron density has been reduced significantly at least by 3 orders of magnitude. This is because as we apply negative bias to the side gate we move the fermi level in the channel higher and electron density has an exponential dependence on the fermi level (exp(FermiEnergy/(k.sub.BT))). Since the threshold voltage depends on the electron density, through the modulation of the electron density by the side gate we can modulate the threshold voltage.
(18) FIG. 5 shows the simulated I.sub.DS-V.sub.GS characteristics for different side gate voltages. The threshold voltage of a transistor can be measured from a I.sub.DS-V.sub.GS characteristics. The gate voltage at which the drain current starts to increase rapidly is called the threshold voltage, which can be found by extrapolating the linear region of I.sub.DS curve and finding the point at which it crosses the gate voltage axis. As demonstrated here, the threshold voltage of the transistor is increasing as we apply more and more negative bias to the side gate. This is because applying negative bias at the side gate depletes the channel Here, 510 is the I.sub.DS-V.sub.GS curve for the side gate voltage, V.sub.SG=0 V, 520 is for V.sub.SG=2 V and 530 is for V.sub.SG=4 V.
(19) FIG. 6 shows the variation of the threshold voltage with the side gate voltage for different fin thickness used by some embodiments. Here the simulated curves are presented for fin widths 100 nm, 200 nm, 300 nm and 400 nm labeled 610, 620, 630 and 640 respectively. If we can define a controllability parameter , defined as =V.sub.TH/V.sub.SG which is given by the slope of the curves. Ideally we want the magnitude of to be as high as possible, however due to physical reasons it cannot be made more than 1. As shown in this figure the value of decreases as we increase the fin thickness this is because as the fin thickness is increased the side wall loses the controllability of the channel due to reduced capacitance. If the fin thickness is more than 400 nm the controllability parameter is very close to zero-which gives us the upper limit of fin thickness.
(20) FIG. 7 shows the I.sub.DS-V.sub.DS characteristics for different side gate voltage (V.sub.SG) for 100 nm fin width transistor according to one embodiment. The curve 710 shows an example wherein V.sub.SG=0V and the curve 720 shows an example when V.sub.SG=3V. When a negative tuner voltage is applied, drain current drops sharply due to the increment of in the threshold voltage, which in turn reduces the overdrive voltage (V.sub.DS-V.sub.TH).
(21) FIG. 8 shows a 2-D cross section is the middle of the channel of the transistor according to one embodiment. In this embodiment, the transistor includes a dielectric layer 103 sandwiched between the top gate electrode and the cap layer. This structure allows to decrease the gate leakage current and improves the efficiency by reducing the power loss.
(22) FIG. 9 shows a 2-D cross section in the middle of the channel of the transistor according to one embodiment. In this embodiment, the transistor includes a dielectric layer 104 and 105 sandwiched between the side gate electrode and the fin side wall. This dielectric layer helps to reduce the gate leakage from the side wall.
(23) FIG. 10 shows a 2-D cross section in the middle of the channel of the transistor according to one embodiment. In this embodiment, the semiconductor structure includes a back barrier layer 107. The purpose of a back barrier layer is to provide quantum confinement to the 2-DEG formed at the interface of channel and cap layer. According to one embodiment the back barrier is doped with p-type dopants.
(24) FIG. 11 shows a flow chart of a method for controlling the threshold voltage of the transistor according to various embodiments. The method measures 1110 the threshold voltage without applying any side gate voltage. The method checks 1130 the desired threshold voltage to detect a request to change a sign of the threshold voltage with respect to the source. For example, if a higher threshold voltage is needed, the method applies 1120 negative bias to the side gate. For example, the method applies a negative voltage to the side gate when the threshold voltage is negative and the positive threshold voltage is required. On the other hand, if a lower threshold voltage is needed, then the method applies 1140 positive bias to the side gate. For example, the method applies a positive voltage to the side gate when the threshold voltage is positive and the negative threshold voltage is required.
(25) Additionally, or alternatively, if enhancement mode operation is required then the method keeps increasing the negative bias at the side gate until the threshold voltage becomes greater than zero. Generally, for driver circuits and most power electronic applications enhancement mode operation is preferred.
(26) FIG. 12 shows a block diagram of a method for fabricating a semiconductor device according to some embodiments. The method includes providing a substrate 1210, making 1220 a semiconductor structure comprising at least a III-N channel layer forming a carrier channel in the semiconductor structure. The material of cap-layer has a higher bandgap than the bandgap of material in the III-N channel layer. According to some embodiments, various methods can be adopted for the growth and formation of the cap-layer or channel layer, including but not limited to a Chemical Vapor Deposition (CVD), a Metal-Organic-Chemical-Vapor-Deposition (MOCVD), a Molecular Beam Epitaxy (MBE), a Metal-Organic Vapor Phase Epitaxy (MOVPE) and a Plasma Enhanced Chemical Vapor Deposition (PECVD) and a microwave plasma deposition system.
(27) The method defines 1230 the active region of the transistor by wet etching or dry etching and forms 1240 the source and the drain electrode to electrically connect to the carrier channel using one or combination of an ebeam deposition, a joule evaporation, a chemical vapor deposition and a sputtering process. Then the sample is annealed >800 C. in vacuum or N2 environment to form the ohmic contact. The method forms 1250 the fin structure, e.g., by depositing hard mask and dry etching, and forming 1260 the side wall gate, e.g., by depositing metal and then blank etching.
(28) The method also includes deposition 1270 of a spacer dielectric layer, e.g., using one or combination of an atomic layer deposition (ALD), a chemical vapor deposition (CVD), Metal-Organic Chemical Vapor Deposition (MOCVD), a Molecular Beam Epitaxy (MBE), a Metal Organic Vapor Phase Epitaxy (MOVPE), a Plasma Enhanced Chemical Vapor Deposition (PECVD), and a microwave plasma deposition. Then the method planarizes the spacer layer by blank etching.
(29) Further method also includes the formation 1280 of the metal layer for the gate electrode. The formation of this metal layer can be done using one or combination of Lithography.fwdarw.Metal Deposition.fwdarw.Lift-off, and Metal deposition.fwdarw.Lithography.fwdarw.Etching. Here the lithography could be performed using, including but not limited to photo-lithography, electron-beam lithography. Metal deposition can be done using one or combination of an ebeam deposition, a joule evaporation, a chemical vapor deposition and a sputtering process.
(30) Although the invention has been described by way of examples of preferred embodiments, it is to be understood that various other adaptations and modifications can be made within the spirit and scope of the invention. Therefore, it is the objective of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.
