Stacked III-V semiconductor component

Abstract

A stacked III-V semiconductor component having a p.sup.+ region with a top side, a bottom side, and a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3, a first n.sup. layer with a top side and a bottom side, a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3, and a layer thickness of 10-300 m, an n.sup.+ region with a top side, a bottom side, and a dopant concentration of at least 10.sup.18 N/cm.sup.3, wherein the p.sup.+ regions, the n.sup. layer, and the n.sup.+ region follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the n.sup.+ region or the p.sup.+ region is formed as the substrate layer, and the n.sup. layer comprises chromium with a concentration of at least 10.sup.14 N/cm.sup.3 or at least 10.sup.15 N/cm.sup.3.

Claims

1. A stacked group III-V semiconductor component comprising: a p.sup.+ region with a top side, a bottom side, and an electrically active dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3; a first n.sup. layer with a top side and a bottom side, a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3, cm, and a layer thickness of 10-300 m; an n.sup.+ region with a top side, a bottom side, and a dopant concentration of at least 10.sup.18 N/cm.sup.3; wherein the p.sup.+ regions, the n.sup. layer, and the n.sup.+ region follow one another and are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, wherein the n.sup.+ region or the p.sup.+ region is formed as a substrate layer, and wherein the n.sup. layer comprises defects with a concentration of at least 10.sup.14 N/cm.sup.3 or at least 10.sup.15 N/cm.sup.3.

2. The stacked group III-V semiconductor component according to claim 1, wherein the p.sup.+ region and the n.sup.+ region are formed layered, wherein the layered n.sup.+ region and the layered p.sup.+ region are each integrally connected to the n.sup. layer, wherein the layered n.sup.+ region has a layer thickness of 50-675 m, wherein the layered p.sup.+ region has a layer thickness greater than 2 m, wherein the stacked III-V semiconductor component has a defect layer with a layer thickness between 0.5 m and 50 m, and wherein the defect layer is disposed within the n.sup. layer and has a defect concentration in a range between 1.Math.10.sup.13 N/cm.sup.3 and 5.Math.10.sup.16 N/cm.sup.3.

3. The stacked group III-V semiconductor component according to claim 2, wherein the defect layer has a layer thickness between 0.5 m and 50 m and a distance of the defect layer to an interface between the n.sup. layer and the p.sup.+ region is at most half the layer thickness of the n.sup. layer.

4. The stacked group III-V semiconductor component according to claim 1, wherein the p.sup.+ region and the n.sup.+ region are formed layered, wherein the layered n.sup.+ region is integrally connected to the n.sup. layer, wherein a doped interlayer with a layer thickness of 1-50 m and a dopant concentration of 10.sup.12-10.sup.17 cm.sup.3 is disposed between the n.sup. layer and the p.sup.+ layer, and wherein the interlayer is integrally connected to the n.sup. layer and to the p.sup.+ layer.

5. The stacked group III-V semiconductor component according to claim 1, wherein the p.sup.+ region and the n.sup.+ region are formed layered, wherein a p-doped interlayer with a layer thickness of 1-50 m and a dopant concentration of 10.sup.12-10.sup.17 cm.sup.3 is disposed between the n.sup. layer and the p.sup.+ region, wherein the layered n.sup.+ region and the interlayer are each integrally connected to the n.sup. layer and the layered p.sup.+ region is integrally connected to the interlayer, wherein the stacked III-V semiconductor component has a first defect layer with a layer thickness between 0.5 m and 40 m, and wherein the defect layer is disposed within the p-doped interlayer and has a defect concentration in a range between 1.Math.10.sup.13 N/cm.sup.3 and 5.Math.10.sup.16 N/cm.sup.3.

6. The stacked group III-V semiconductor component according to claim 1, wherein the p.sup.+ region and the n.sup.+ region are formed layered, wherein the layered n.sup.+ region and the layered p.sup.+ region are integrally connected to the p.sup. layer, and wherein the dopant concentration within the n.sup. layer of the surface, adjacent to the p.sup.+ region, of the n.sup. layer, to the surface, adjacent to the n.sup.+ region, of the n.sup. layer increases by a factor between 1.5 and 2.5.

7. The stacked group III-V semiconductor component according to claim 1, wherein the layered p.sup.+ region is formed as the substrate with a layer thickness of 50-500 m and the layered n.sup.+ region has a layer thickness less than 30 m.

8. The stacked group III-V semiconductor component according to claim 1, wherein the layered n.sup.+ region is formed as a substrate with a layer thickness of 50-400 m and the layered p.sup.+ region has a layer thickness greater than 2 m.

9. The stacked group III-V semiconductor component according to claim 1, wherein the stacked semiconductor component has a first connection contact layer, a second connection contact layer, and a p.sup. layer, wherein the p.sup. layer has a dopant concentration between 10.sup.12 and 10.sup.16 N/cm.sup.3 and a layer thickness between 10 nm and 10 m and comprises a GaAs compound or consists of GaAs compounds or comprises further III-V compounds or consists of further III-V compounds, wherein the n.sup.+ region is formed layered with a layer thickness between 50 m and 400 m, wherein the bottom side of the n.sup. layer is integrally connected to the top side of the layered n.sup.+ region, wherein the p.sup. layer is integrally connected to the top side of the n.sup. layer, wherein the p.sup.+ region is formed of at least two subregions spaced from to one another, wherein each subregion of the p.sup.+ region has a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3, is formed as ribs running parallel to a top side of the p.sup. layer and extends from a top side of the p.sup. layer into the n.sup. layer, wherein the first connection contact layer is integrally connected to the bottom side of the n.sup.+ region, wherein the second connection contact layer is integrally and electrically conductively connected to part of the top side of the p.sup. layer, wherein the second connection contact layer is connected integrally and electrically conductively to the entire top side or to part of the top side of each subregion of the p.sup.+ region, and wherein the second connection contact layer comprises a metal or a metallic compound or consists of a metal or a metallic compound and forms a Schottky contact.

10. The stacked group III-V semiconductor component according to claim 1, wherein the III-V semiconductor component has at least one p region, a dielectric layer, and at least three connection contact layers, wherein the p.sup.+ region is formed as a layered substrate with a layer thickness of 50-500 m, wherein the p region is adjacent to the n.sup. layer, has a dopant concentration of 10.sup.14 N/cm.sup.3-10.sup.18 N/cm.sup.3, and comprises a GaAs compound or consists of a GaAs compound, wherein the at least one p region forms a first pn junction with the n.sup. layer, wherein the n.sup.+ region forms a second pn junction with the at least one p region, wherein the dielectric layer covers at least the first pn junction and the second pn junction and is integrally connected to the n.sup. layer, the p region, and the n.sup.+ region, wherein a doped interlayer with a layer thickness from 1 m to 50 m and a dopant concentration of 10.sup.12-10.sup.17 cm.sup.3 is disposed between the layered p.sup.+ region and the n.sup. layer, wherein the interlayer is integrally connected at least to the layered p.sup.+ region, wherein the first connection contact layer is connected electrically conductively to the bottom side of the layered p.sup.+ region, wherein the second connection contact layer is formed as a field plate on the dielectric layer, and wherein the third connection contact layer is connected electrically conductively to the at least one p region and the at least one n.sup.+ region.

11. The stacked group III-V semiconductor component according to claim 1, wherein the p.sup.+ region comprises zinc.

12. The stacked group III-V semiconductor component according to claim 1, wherein the n.sup.+ region comprises chromium and/or silicon and/or palladium and/or tin.

13. The stacked group III-V semiconductor component according to claim 1, wherein the n.sup. layer comprises silicon and/or palladium and/or tin.

14. The stacked group III-V semiconductor component according to claim 1, wherein the n.sup. layer comprises chromium with a concentration in a range between 1.Math.10.sup.13 N/cm.sup.3 and 5.Math.10.sup.16 N/cm.sup.3.

15. The stacked group III-V semiconductor component according to claim 1, wherein the semiconductor component is formed monolithically or comprises a semiconductor bond.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a schematic view of an embodiment of the invention of a stacked III-V semiconductor component;

(3) FIG. 2 shows a top plan view of the stacked III-V semiconductor element of FIG. 1;

(4) FIG. 3 shows a schematic view of an embodiment of the invention of a stacked III-V semiconductor diode;

(5) FIG. 4 shows a schematic view of an embodiment of the invention of a stacked III-V semiconductor diode;

(6) FIG. 5 shows a schematic view of an embodiment of the invention of a stacked III-V semiconductor diode;

(7) FIG. 6 shows a schematic view of an embodiment of the invention of a stacked III-V semiconductor diode;

(8) FIG. 7 shows a schematic view of an embodiment of the invention of a Schottky diode;

(9) FIG. 8 shows a schematic view of an embodiment of the invention of a Schottky diode;

(10) FIG. 9 shows a schematic view of an embodiment of the invention of an IGBT semiconductor structure;

(11) FIG. 10 shows a top plan view of the IGBT semiconductor structure of FIG. 9; and

(12) FIG. 11 shows a schematic view of a further embodiment of the invention of an IGBT semiconductor structure.

DETAILED DESCRIPTION

(13) The diagram in FIG. 1 shows a side view of an embodiment of a stacked III-V semiconductor component 10. The diagram in FIG. 2 shows a top plan view of III-V semiconductor component 10. Component 10 is formed as a diode with a stack of three semiconductor layers and two contact layers, wherein each semiconductor layer comprises a GaAs compound or consists of a GaAs compound.

(14) The first semiconductor layer is p.sup.+ region 12, formed as substrate, with a layer thickness D1 and is highly p-doped with a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3. The second semiconductor layer is a first n.sup. layer 14 with a layer thickness D2. The third semiconductor layer is a highly n-doped, layered n.sup.+ region 16 with a dopant concentration of at least 10.sup.18 N/cm.sup.3. The three semiconductor layers are grown monolithically on one another in the stated order, so that a bottom side of p.sup. layer 14 is integrally connected to a top side of the p.sup.+ substrate and a bottom side of the n.sup.+ layer is integrally connected to n.sup. layer 14.

(15) The n.sup. layer 14 is lightly n-doped with a dopant concentration between 10.sup.12 N/cm.sup.3 and 10.sup.17 N/cm.sup.3, wherein the dopant concentration increases by a factor of 1.5 to 2.5 in a direction from the bottom side of n.sup. layer 14 to the top side of n.sup. layer 14. In addition, n.sup. layer 14 comprises chromium Cr with a concentration of at least 10.sup.14 N/cm.sup.3 or at least 10.sup.15 N/cm.sup.3.

(16) A first contact layer 40 is integrally and electrically conductively connected to the bottom side of p.sup.+ substrate 12, therefore the bottom side of the stack, and a second contact layer 42 is integrally and electrically conductively connected to the top side of the n.sup.+ layer, therefore the top side of the stack, wherein the two contact layers 40 and 42 according to the illustrated exemplary embodiment only partially cover the respective surface of the semiconductor layer.

(17) Alternatively, the n.sup.+ layer is formed as a substrate, on which n.sup. layer 14 and a layered p.sup.+ region are created epitaxially, so that the bottom side of the n.sup.+ layer forms the bottom side of the stack and the top side of the stack is the top side of the p.sup.+ layer.

(18) In the diagram in FIG. 3, a further embodiment of a III-V semiconductor component of the invention is shown as a diode. Only the differences from the diagram in FIG. 1 will be explained below.

(19) The n.sup.+ region 14 is formed as a substrate on which n.sup. layer 14 and a layered p.sup.+ region are grown.

(20) The n.sup. layer 14 is lightly n-doped and has a dopant concentration that is constant over the entire layer. A defect layer 22 with a defect concentration in a range between 1.Math.10.sup.13 N/cm.sup.3 and 5.Math.10.sup.16 N/cm.sup.3 and with a layer thickness D4 0.5 m and 50 m is disposed within n.sup. layer 14, wherein defect layer 22 has a first distance A1 to an interface between n.sup. layer 14 and p.sup.+ region 12, therefore to the top side of n.sup. layer 14.

(21) An embodiment that is an alternative to the diagram in FIG. 3 is shown in the diagram in FIG. 4, wherein the order of the semiconductor layers is inverted, so that p.sup.+ region 12 is formed as a layered substrate, followed by n.sup. layer 14, containing defect layer 22, and n.sup.+ layer 16. The first distance A1 accordingly provides the distance of defect layer 22 to the bottom side of n.sup. layer 14.

(22) A further embodiment of a III-V semiconductor component of the invention as a diode is shown in the diagram in FIG. 5. Only the differences from the diagram in FIG. 1 will be explained below.

(23) The III-V semiconductor component 10 has n.sup.+ region 16 as the substrate, followed by n.sup. layer 14 with a dopant concentration that is constant over the entire layer, an interlayer 24 with a layer thickness D5, and p.sup.+ layer 12. Interlayer 24 is p-doped or n-doped with a dopant concentration of 10.sup.12-10.sup.17 cm.sup.3.

(24) An embodiment that is an alternative to the diagram in FIG. 5 is shown in the diagram in FIG. 6, wherein the order of the semiconductor layers is inverted, so that p.sup.+ region 12 is formed as the substrate and is followed in the indicated order by interlayer 24, n.sup. layer 14, and the n.sup.+ layer.

(25) A further alternative embodiment of a III-V semiconductor component 10 of the invention is shown in the diagram in FIG. 7. Only the differences to the preceding figures will be described below.

(26) III-V semiconductor component 10 is formed as a Schottky diode, having the n.sup.+ region, formed as the substrate, and followed by layered n.sup. region 14, grown monolithically on the substrate, and a p.sup. layer 26, grown on n.sup. region 14 and having a layer thickness D6. The p.sup.+ region 12 has two subregions spaced from one another, wherein the subregions extend from a top side of p.sup. layer 26 up to a depth D1 through the entire p.sup. layer 26 into n.sup. layer 14.

(27) First connection contact layer 40 in the illustrated exemplary embodiment covers the entire bottom side of the n.sup.+ substrate, whereas second connection contact layer 42 covers only part of the top side of p.sup. layer 26 and in each case part of a top side of each p.sup.+ subregion, so that in each case an edge of second connection contact layer 42 is located within the top side of a p.sup.+ subregion.

(28) An embodiment of a Schottky diode of the invention that is an alternative to the diagram in FIG. 7 is shown in the diagram in FIG. 8, wherein the p.sup.+ region is formed of six subregions, spaced from one another, and second contact layer 42 partially covers a top side of the first subregion and a top side of the sixth subregion and completely covers the top sides of the subregions lying therebetween.

(29) The diagrams of FIGS. 9 and 10 show a further alternative embodiment of a III-V semiconductor component 10 of the invention in a side view and a top view. Only the differences to the preceding figures will be described below.

(30) III-V semiconductor component 10 is formed as a stacked IGBT semiconductor structure with a so-called non-punch-through design, wherein the p.sup.+ region is formed as the substrate, followed by a lightly n-doped or p-doped interlayer 24 and an n.sup. layer 14. The n.sup. layer 14 forms part of a top side of the stack. Another part of the top side of the stack is formed by a p region 28, wherein p region 28 extends from the top side of the stack up to a depth D7 into n.sup. layer 14. A further part of the top side of the stack is formed by n.sup.+ region 16, wherein the n.sup.+ region extends from the top side of the stack up to a depth D8 into p region 28 and the depth D7 of p region 28 is greater than depth D8 of n.sup.+ region 16.

(31) Thus, two pn junctions form, adjacent to the top side of the stack of the semiconductor structure, namely a first pn junction 32 between p region 28 and p.sup. layer 14 and a second pn junction 34 between n.sup.+ region 16 and p region 28. A dielectric layer 30 with a layer thickness D9 covers at least first pn junction 32 and second pn junction 34 and is integrally connected to the top side of the stack of the semiconductor structure, in particular to n.sup.+ region 16, p region 28, and n.sup. layer 14.

(32) First connection contact layer 40 is formed as a metal layer, wherein the metal layer is integrally and electrically conductively connected to a bottom side of the stack, therefore to the bottom side of the p.sup.+ region. Second connection contact 42 is formed as a field plate on a surface of dielectric layer 30, said surface facing away from the semiconductor structure. A third connection contact 44 is likewise formed as a metal layer, wherein the metal layer is integrally and electrically conductively connected to a part of the stack top side, said part being formed by p region 28 and n.sup.+ region 16.

(33) The top side of the semiconductor structure without contact layers as shown in the diagram of FIG. 10 has a rectangular contour, wherein p region 28 and n.sup.+ region 16 are formed circular.

(34) The diagram in FIG. 11 shows a further alternative embodiment of an IGBT semiconductor structure of the invention. Only the differences from the diagram in FIG. 9 will be explained below. Semiconductor structure 10 is formed as a so-called trench IGBT.

(35) The p region 28 and n.sup.+ region 16 are each formed as layers on n.sup. layer 14 or p region 28, respectively, wherein the semiconductor structure has a trench 46 extending from the top side through layered n.sup.+ region 16 and layered p region 28 into n.sup. layer 14.

(36) First pn junction 32 and second pn junction 34 run perpendicular to a side surface 48 of trench 46. Side surface 48 and a bottom 50 of trench 46 are covered by dielectric layer 30. Second connection contact 42, formed as a field plate, extends correspondingly on dielectric layer 30. Third connection contact layer 44 is located on a side surface 52 of the semiconductor structure, said surface lying opposite to side surface 48 of trench 46, and is connected electrically conductively to layered n.sup.+ region 16 and to layered p region 28. Preferably, the side surfaces extend along crystallographic directions of the III-V semiconductor material.

(37) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims: