TFT SUBSTRATE, ESD PROTECTION CIRCUIT AND MANUFACTURING METHOD OF TFT SUBSTRATE

Abstract

A TFT substrate, an ESD protection circuit, and a method for manufacturing the TFT substrate. The TFT substrate comprises: a base substrate; a first gate provided on the base substrate; a first insulating layer provided on the first gate; a drain, a source, and an active layer provided on the first insulating layer; a second insulating layer provided on the drain, the source, and the active layer; and a second gate provided on the second insulating layer. In this way, display abnormality of a liquid crystal panel screen can be avoided.

Claims

1. A TFT substrate, comprising: a base substrate; a first gate provided on the base substrate; a first insulating layer provided on the first gate; a drain, a source and an active layer provided on the first insulating layer and at least a portion of the drain and at least a portion of the source being provided and spaced apart at the outer end of the active layer and connected through the active layer; and a second insulating layer provided on the drain, the source, and the active layer; a second gate provided on the second insulating layer, and the second gate is connected to a negative voltage.

2. The TFT substrate according to claim 1, wherein the distances from the first gate and the second gate to the active layer are the same.

3. The TFT substrate according to claim 1, wherein the second gate is U-shaped.

4. The TFT substrate according to claim 1, wherein an orthographic projection of the active layer on the base substrate at least partially covers an orthographic projection of the first gate on the base substrate.

5. The TFT substrate according to claim 1, wherein the drain and the source are stepped and symmetrically provided at the outer end of the active layer.

6. The TFT substrate according to claim 1, wherein the first gate and the second gate have the same shape and size.

7. An ESD protection circuit, comprising the TFT substrate according to claim 1, and the TFT substrate comprises a first TFT transistor and a second TFT transistor, wherein a drain of the first TFT transistor is connected to a positive voltage signal, and a source of the second TFT transistor is connected to a negative voltage signal; a source of the first TFT transistor, a first gate of the first TFT transistor and a drain of the second TFT transistor are connected to data signal altogether, and a first gate of the second TFT transistor is connected to the source.

8. The ESD protection circuit according to claim 7, wherein the second gate of the first TFT transistor and the second gate of the second TFT transistor are respectively connected to the source of the second TFT transistor.

9. A method for manufacturing a TFT substrate, comprising the following steps: S11. providing a base substrate, and forming a first gate on the base substrate; S12. forming a first insulating layer on the first gate and the substrate, and the first insulating layer completely covering the first gate; S13. forming a drain, a source and an active layer on the first insulating layer, and at least a portion of the drain and at least a portion of the source being provided and spaced apart at the outer end of the active layer and connected through the active layer; S14. forming a second insulating layer on the drain, the source and the active layer, and the second insulating layer completely covering the drain, the source and the active layer; and S15. forming a second gate connected to a negative voltage on the second insulating layer.

10. The method for manufacturing a TFT substrate according to claim 9, wherein in the step S11, forming the first gate on the base substrate, comprising: depositing a first metal layer is deposited on the base substrate, and patterning the first metal layer by a photolithography process to obtain the first gate; or, forming a first polysilicon layer ion the base substrate, after performing N-type doping for the first polysilicon layer, patterning the N-type doped polysilicon layer by a photolithography process to obtain the first gate.

11. The method for manufacturing a TFT substrate according to claim 9, wherein the step S13 comprises: depositing a semiconductor layer on the first insulating layer by a chemical or physical vapor deposition method, and patterning the semiconductor layer by a photolithography process to obtain the active layer; depositing a second metal layer on the active layer and the first insulating layer, and patterning the second metal layer by a photolithography process to obtain the drain and the source; or, forming a second polysilicon layer on the active layer and the first insulating layer, after performing N-type doping for the second polysilicon layer, patterning the N-type doped polysilicon layer by a photolithography process to obtain the drain and the source.

12. The method for manufacturing a TFT substrate according to claim 9, wherein the step S15 comprises: depositing a third metal layer on the second insulating layer, and patterning the third metal layer by a photolithography process to obtain the second gate; or, forming a third polysilicon layer on the second insulating layer, after performing N-type doping for the third polysilicon layer, patterning the N-type doped polysilicon layer by a photolithography process to obtain the second gate.

13. The method for manufacturing a TFT substrate according to claim 10, wherein the photolithography process comprises photoresist, exposure, development and etching processes.

14. The method for manufacturing a TFT substrate according to claim 11, wherein the photolithography process comprises photoresist, exposure, development and etching processes.

15. The method for manufacturing a TFT substrate according to claim 12, wherein the photolithography process comprises photoresist, exposure, development and etching processes.

16. An ESD protection circuit, comprising the TFT substrate according to claim 2, and the TFT substrate comprises a first TFT transistor and a second TFT transistor, wherein a drain of the first TFT transistor is connected to a positive voltage signal, and a source of the second TFT transistor is connected to a negative voltage signal; a source of the first TFT transistor, a first gate of the first TFT transistor and a drain of the second TFT transistor are connected to data signal altogether, and a first gate of the second TFT transistor is connected to the source.

17. An ESD protection circuit, comprising the TFT substrate according to claim 3, and the TFT substrate comprises a first TFT transistor and a second TFT transistor, wherein a drain of the first TFT transistor is connected to a positive voltage signal, and a source of the second TFT transistor is connected to a negative voltage signal; a source of the first TFT transistor, a first gate of the first TFT transistor and a drain of the second TFT transistor are connected to data signal altogether, and a first gate of the second TFT transistor is connected to the source.

18. An ESD protection circuit, comprising the TFT substrate according to claim 4, and the TFT substrate comprises a first TFT transistor and a second TFT transistor, wherein a drain of the first TFT transistor is connected to a positive voltage signal, and a source of the second TFT transistor is connected to a negative voltage signal; a source of the first TFT transistor, a first gate of the first TFT transistor and a drain of the second TFT transistor are connected to data signal altogether, and a first gate of the second TFT transistor is connected to the source.

19. An ESD protection circuit, comprising the TFT substrate according to claim 5, and the TFT substrate comprises a first TFT transistor and a second TFT transistor, wherein a drain of the first TFT transistor is connected to a positive voltage signal, and a source of the second TFT transistor is connected to a negative voltage signal; a source of the first TFT transistor, a first gate of the first TFT transistor and a drain of the second TFT transistor are connected to data signal altogether, and a first gate of the second TFT transistor is connected to the source.

20. An ESD protection circuit, comprising the TFT substrate according to claim 6, and the TFT substrate comprises a first TFT transistor and a second TFT transistor, wherein a drain of the first TFT transistor is connected to a positive voltage signal, and a source of the second TFT transistor is connected to a negative voltage signal; a source of the first TFT transistor, a first gate of the first TFT transistor and a drain of the second TFT transistor are connected to data signal altogether, and a first gate of the second TFT transistor is connected to the source.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly explain the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments drawing may be obtained based on these drawings without any creative efforts. In the drawings:

[0042] FIG. 1 is a circuit structure diagram of an ESD protection circuit in the prior art;

[0043] FIG. 2 is a schematic diagram of the ESD protection circuit in FIG. 1 when static electricity occurs;

[0044] FIG. 3 is a waveform diagram of the input data signal and the output data signal when static electricity occurs;

[0045] FIG. 4 is a schematic structural view of embodiment 1 of the TFT substrate of the present invention;

[0046] FIG. 5 is a schematic diagram of the simulation of the turn-on voltage of the TFT transistor of the prior art and the TFT transistor of the present invention;

[0047] FIG. 6 is a circuit structure diagram of the ESD protection circuit of the present invention;

[0048] FIG. 7 is a flowchart of embodiment 1 of a method for manufacturing a TFT substrate of the present invention.

DETAILED DESCRIPTION

[0049] In the following, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by an ordinary person of skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0050] FIG. 4 is a schematic structural view of the embodiment 1 of the TFT substrate of the present invention. The TFT substrate of this embodiment comprises a stacked arrangement of a base substrate 11, a first gate 12, a first insulating layer 13, a drain 14, a source 15, an active layer 16, a second insulating layer 17, a the second gate 18. Wherein, the first gate 12 is provided on the base substrate 11 and has an area smaller than that of the base substrate 11, and is preferably provided in the middle portion of the base substrate 11. The first insulating layer 13 is provided on the first gate 12, the drain 14, the source 15 and the active layer 16 are provided on the first insulating layer 13, and at least a portion of the drain 14 and at least a portion of the source 15 are provided and spaced apart at the outer end of the active layer 16 and connected through the active layer 16. In addition, the second insulating layer 17 is provided on the drain 14, the source 15 and the active layer 16, covering the drain 14, the source 15 and the active layer 16, and the second gate 18 is provided on the second insulating layer 17, and the second gate 18 is connected to a negative voltage.

[0051] Moreover, in this embodiment, an orthographic projection of the active layer 16 on the base substrate 11 partially covers an orthographic projection of the first gate 12 on the base substrate 11. Of course, in other embodiments, the orthographic projection of the first gate 12 on the base substrate 11 may also be completely covered.

[0052] Further, the drain electrode 14 and the source electrode 15 are stepped, and are symmetrically provided at both ends and top of the active layer 16. Of course, in other embodiments, the drain 14 and the source 15 may have other shapes, and may also be provided at the left and right ends, the bottom, or the top of the active layer.

[0053] Further, the shape of the second gate 18 is U-shaped. Of course, in other embodiments, the shape, size of the first gate 12 and the second gate may be the same, and the distances from both of them to the active layer 16 are the same respectively. Of course, in other embodiments, the shape, size, and distances to the active layer 16 of both of them may are vary.

[0054] The TFT substrate of this embodiment adopts a double gate structure, and the first gate 12 and the second gate 18 are distributed on both sides of the active layer. When a voltage is applied to the first gate, an on-current of the conducting channel is generated, and because the second gate 18 is applied a negative voltage, the amount of current in the conducting channel is suppressed, thereby preventing the sectional area of the conductive channel from increasing, which is equivalent to increasing the turn-on voltage of the TFT transistor. With reference to FIG. 5, when the second gate 18 is not added, the turn-on voltage of the TFT transistor is 5V, and when the second gate 18 is added, the turn-on voltage of the TFT transistor shifts to the positive direction and becomes 0V.

[0055] FIG. 6 is a circuit structure diagram of the ESD protection circuit of the present invention. The ESD protection circuit of this embodiment comprises the TFT substrate shown in the above-mentioned embodiment, and the TFT substrate comprises a first TFT transistor M1 and a second TFT transistor M2, wherein the drain of the first TFT transistor M1 is connected to a positive voltage signal (VGH), the source of the second TFT transistor M2 is connected to a negative voltage signal (VGL), the source of the first TFT transistor M1, the first gate of the first TFT transistor M1 and the drain of the second TFT transistor M2 are connected to data signal (Data) altogether, and the first gate of the second TFT transistor M2 is connected to the source.

[0056] Preferably, the second gate of the first TFT transistor M1 and the second gate of the second TFT transistor M2 are respectively connected to the source of the second TFT transistor M2, so that without adding a voltage source, the existing negative voltage signal (VGL) is utilized to connect the second gate of the first TFT transistor M1 and the second gate of the second TFT transistor M2.

[0057] In this embodiment, after the driver IC outputs the data signal (Data), it is output to the pixel electrode through the ESD protection circuit, when static electricity occurs, since the turn-on voltages of the two TFTs M1 and M2 are greater than 0, the leakage current is very small and can be ignored, as thus the data signal (Data) will not be doped with undesired positive voltage signal (VGH), so that the data signal (Data) output to the pixel electrode is more accurate, and the brightness of pixel electrode will not occur abnormal conditions.

[0058] FIG. 7 is a flowchart of embodiment 1 of a method for manufacturing a TFT substrate of the present invention, and the method for manufacturing a TFT substrate in this embodiment comprises the following steps:

[0059] S11. providing a base substrate is provided, and forming a first gate on the base substrate;

[0060] Specifically, in one example, the method for manufacturing the first gate may be: depositing a first metal layer on the base substrate, and patterning the first metal layer using a photolithography process to obtain the first gate. The material of the first metal layer may be aluminum, molybdenum, copper, or silver. Of course, in another example, the manufacturing method of the first gate may be: forming a first polysilicon layer on the base substrate, and performing N-type doping on the first polysilicon layer, and patterning the N-type doped polysilicon layer by a photolithography process to obtain the first gate.

[0061] S12. forming first insulating layer on the first gate and the substrate, and the first insulating layer completely covering the first gate;

[0062] S13. providing a drain, a source and an active layer on the first insulating layer and at least a portion of the drain and at least a portion of the source are provided and spaced apart at the outer end of the active layer and connected through the active layer;

[0063] Specifically, the manufacturing method of the active layer may be: depositing a semiconductor layer on the first insulating layer by a chemical or physical vapor deposition method, and patterning the semiconductor layer by a photolithography process to obtain the active layer.

[0064] Specifically, the manufacturing method of the drain and the source may be: depositing a second metal layer on the active layer and the first insulating layer, and patterning the second metal layer by a photolithography process to obtain the drain and the source; or forming a polysilicon layer on the active layer and the first insulating layer, performing N-type doping on the second polysilicon layer, and patterning the N-type doped polysilicon layer by a photolithography process to obtain the drain and the source.

[0065] S14. forming a second insulating layer on the drain, the source and the active layer, and the second insulating layer completely covering the drain, the source and the active layer;

[0066] S15. forming second gate connected to a negative voltage on the second insulating layer.

[0067] Specifically, the manufacturing method of the second gate may be: depositing a third metal layer on the second insulating layer, and patterning the third metal layer by a photolithography process to obtain the second gate; or forming a third polysilicon layer on the second insulating layer, and performing N-type doping on the third polysilicon layer, and patterning the N-type doped polysilicon layer by a photolithography process to obtain the second gate.

[0068] Further, the photolithography process in the above-mentioned embodiments includes photoresist, exposure, development and etching processes.

[0069] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present invention shall be included in the scope of the claims of the present invention.