Dual-gate transistors and their integrated circuits and preparation method thereof

Abstract

A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption. Moreover, no additional power sources are added to the circuit, which makes it suitable for ultra-large-scale integrated circuits.

Claims

1. A dual-gate transistor, comprising: an insulating substrate; a semiconductor layer on the insulating substrate; and at least one P-type transistor or at least one N-type transistor, wherein the semiconductor layer includes a plurality of channel regions separated from each other, wherein each of the plurality of channel regions is provided with a P-type transistor or an N-type transistor, wherein the P-type transistor includes: a pair of contact electrodes on the channel region, wherein one of the electrodes is a source electrode connected to VDD and the other one of the electrodes is a drain electrode, a gate dielectric layer between the pair of contact electrodes; a main gate electrode on the gate dielectric layer near the source electrode; and an auxiliary gate electrode near the drain electrode connected to GND, wherein the N-type transistor includes: a pair of contact electrodes on the channel region, wherein one of the electrodes is a source electrode connected to GND and the other one of the electrodes is a drain electrode, a gate dielectric layer between the pair of electrodes; a main gate electrode on the gate dielectric layer near the source electrode; and an auxiliary gate electrode near the drain electrode connected to VDD, wherein the auxiliary gate electrodes of P-type transistor and N-type transistor are respectively connected with GND and VDD.

2. The dual-gate transistor of claim 1, wherein the insulating substrate comprises silicon/silicon dioxide, quartz, glass, Al.sub.2O.sub.3, PET, PEN, or PI.

3. The dual-gate transistor of claim 1, wherein the semiconductor layer includes one or more materials comprising semiconducting-type carbon nanotubes, graphene nano ribbons, MoS.sub.2, WS.sub.2, black phosphorus, Si, Ge, InAs, InSb, PbS, PbSe, or PbTe, wherein the semiconductor layer is formed by a single layer composed of one of the materials or a composite layer composed of two or more of the materials.

4. The dual-gate transistor of claim 1, wherein the semiconductor layer has a bandgap smaller than 1 eV.

5. The dual-gate transistor of claim 1, wherein the pair of contact electrodes, the main gate electrode and auxiliary gate electrodes in the P-type transistor or the N-type transistor includes one or more materials comprising Pd, Pt, Ta, Ti, Cr, Ca, Cu, Al, Au, W, Y, Sc, conductive metal silicide, and doped polysilicon.

6. The dual-gate transistor of claim 1, wherein the gate dielectric layer material in the P-type transistor or the N-type transistor includes a high- oxide insulating material, wherein the high- oxide insulating material includes Al.sub.2O.sub.3, HfO.sub.2, Y.sub.2O.sub.3, Zr.sub.2O.sub.3, wherein interlayer interconnections are formed by a low- insulating material comprising SiO.sub.2, SiC, or PMMA, wherein the high- insulating material has a value greater than 3.9, and the low- insulating material has a value less to 3.9.

7. The dual-gate transistor of claim 1, wherein the auxiliary gate electrode in the P-type transistor is made of a high work-function metal including Pd or Ta, wherein the auxiliary gate electrode in the N-type transistor is made of a low work-function metal including Sc or Ti.

8. An integrated circuit, comprising a dual-gate transistor of claim 1.

9. A method for preparing a dual-gate transistor, comprising: 1) forming a semiconductor layer on an insulating substrate; 2) patterning the semiconductor layer into channel regions separated from each other; 3) forming contact regions on the semiconductor layer respectively for source electrodes and drain electrodes of a P-type transistor and an N-type transistor; 4) depositing a gate dielectric layer on the channel between the contact regions; 5) forming a main gate electrode on the gate dielectric layer near the source electrodes; 6) forming an auxiliary gate electrode separate from the main gate electrode on the gate dielectric layer near the drain electrodes; 7) forming an electric connection between the auxiliary gate electrode of the P-type transistor and GND, forming an electric connection between the auxiliary gate electrode of the N-type transistor and VDD; and 8) forming an insulation layer to separate multiple layers of wiring in the circuit.

10. The method of claim 9, wherein forming a semiconductor layer comprises a dry transfer, coating, nano ink jet printing, or spin coating, wherein steps 2)-8) use a patterning process, wherein the source electrodes, the drain electrodes, the main gate electrode, the auxiliary gate electrode, and the gate dielectric layer are formed by a process comprising: photolithography or electron beam lithography, electron beam evaporation, sputtering, spin coating and cured, sol-gel, coating by atomic layer deposition, and peeling or plasma etching.

11. The method of claim 9, wherein the insulating spacer layer material in step 8) is an organic insulating material or an inorganic insulating material, wherein the organic insulating material comprises PMMA, wherein the inorganic insulating material comprises silicon dioxide or silicon nitride.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG. 1A is a schematic diagram of a conventional self-aligned carbon nanotube transistor.

[0034] FIG. 1B is a schematic diagram of a conventional dual-gate transistor.

[0035] FIG. 1C is a schematic diagram of a dual-gate semiconductor N-type transistor in accordance with the present invention.

[0036] FIG. 1D is a schematic diagram of a dual-gate semiconductor P-type transistor in accordance with the present invention.

[0037] FIG. 2A is a circuit diagram of a conventional CMOS inverter based on conventional self-aligned structure transistors.

[0038] FIG. 2B is a circuit diagram of a conventional CMOS inverter based on conventional feedback gate structure transistors.

[0039] FIG. 2C is a circuit diagram of a dual-gate CMOS inverter in accordance with some embodiments of the present invention.

[0040] FIG. 3A is a schematic diagram of a conventional CMOS inverter based on conventional self-aligned structure transistors.

[0041] FIG. 3B is a schematic diagram of a conventional CMOS inverter based on conventional feedback-gate structure transistors.

[0042] FIG. 3C is a schematic diagram of a strengthened CMOS inverter in accordance with some embodiments of the present invention.

[0043] FIG. 4A-4B show transfer characteristic curves of the transistors prepared using a conventional self-aligned structure.

[0044] FIG. 4C-4E show transfer characteristic curves of the transistors prepared using a conventional feedback gate structure.

[0045] FIGS. 5A-5E show electrical characteristic curves of the transistors prepared using the presently disclosed methods.

[0046] FIG. 5A shows transfer characteristic curves of a dual-gate semiconductor P-type transistor (PMOS) in accordance with some embodiments of the present invention.

[0047] FIG. 5B shows transfer characteristic curves of a dual-gate semiconductor N-type transistor (NMOS) in accordance with some embodiments of the present invention.

[0048] FIG. 5C shows output characteristic curves of a dual-gate semiconductor P-type transistor (PMOS) in accordance with some embodiments of the present invention.

[0049] FIG. 5D is a voltage graph of a CMOS inverter in a dual-gate transistor circuit in accordance with some embodiments of the present invention.

[0050] FIG. 5E is an operation current diagram of a CMOS inverter in a dual-gate transistor circuit in accordance with some embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0051] In order to make the above features and advantages of the present invention more comprehensible, embodiments are described below in detail with reference to the accompanying drawings.

[0052] In some embodiments, as shown in FIGS. 1C/1D, a dual-gate transistor includes an insulating substrate 000, a semiconductor layer 015/016 on the insulating substrate 000, and at least one P-type transistor or at least one N-type transistor. The semiconductor layer 015/016 includes a plurality of mutually separated channel regions, as shown in the two channel regions 015 and 016 respectively in FIGS. 1C/1D. FIG. 1D shows a P-type transistor. The P-type transistor includes a pair of contact electrodes 001/005 made of Pd on the semiconductor layer 015, one of which is a source electrode 001 connected to VDD and another is a drain electrode 005. A gate dielectric layer 002 is formed between the pair of electrodes 001/005. A main gate electrode 003 is formed on the gate dielectric layer 002 near the source electrode 001. An auxiliary gate electrode 004 is formed near the drain electrode 005.

[0053] FIG. 1C includes an N-type transistor. The N-type transistor includes a pair of contact electrodes 006/010 made of Sc on the semiconductor layer 016, one of which is a drain electrode 006 and the other is a source electrode 010 connected to GND. A gate dielectric layer 007 is formed between the pair of electrodes 006/010. On the gate dielectric layer 007, a main gate electrode 008 is formed at a position near the source electrode 010, and a gate electrode auxiliary 009 is formed near the drain electrode 006. The auxiliary gate electrode 004 of the P-type transistor is connected to the grounded source electrode 010 via line 001. The auxiliary gate electrode 009 in the N-type transistor is connected via connection line 012 to the source electrode 001 that supplies operating voltage.

[0054] Comparing FIGS. 1C/1D to the conventional transistors shown in FIGS. 1A-1B, the present transistors can suppress ambipolar behavior, improve current on/off ratio at large drain-source voltage while ensuring high on-state current at small drain-source voltage of the transistors. The two unchanged power supplies GND and VDD in the circuit are respectively connected to two auxiliary gates of P-type and N-type transistors. A thick and high potential barrier of minority carriers is formed near the drain electrode, which inhibits reverse minority carrier tunneling from the drain electrode at large drain-source voltage. While the thick and high potential barrier near drain electrode is transparent for majority carriers from source electrode, so even at a small drain-source voltage, the transistor can be easily turned on and on-state current won't decrease a lot. The circuit diagram of a strengthened CMOS inverter is shown in FIG. 2C, which is distinctly different from conventional CMOS inverters shown in FIGS. 2A-2B. The strengthened CMOS inverter in this embodiment is shown in FIG. 3C. Conventional CMOS inverters with self-aligned gate structure and feedback gate structure are respectively shown in FIGS. 3A-3B.

[0055] In the following, semiconducting-type carbon nanotube thin film is used as an example for a semiconductor layer. Based on dual-gate transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption. Here we take most fundamental circuit-inverter as an example to decrease how to show advantages in circuit level, but it won't be just limit to this. A CMOS inverter based on a carbon nanotube film can be prepared using a method to be described specifically as follows:

[0056] 1. In this example, a semiconducting-type carbon nanotube film can be obtained by solution deposition, or by self-assembly, alignment, spin coating, growth, and transfer, etc.

[0057] 2. In this example, the insulating substrate 000 may be made of a silicon/silicon dioxide, quartz, glass, aluminum, or other hard materials, or PET, PEN, PI, or other high temperature flexible insulating materials;

[0058] 3. A semiconducting-type carbon nanotube film is deposited on the silicon/silicon dioxide and is patterned according to a desired shape. The excess portion is etched away with O.sub.2 plasma or other methods;

[0059] 4. On the patterned carbon nanotube film, a pair of Pd electrodes 001/005 is formed by electron beam lithography and electron beam evaporation. The electrodes have a thickness of 60 nm and a width of 300 nm, with spacing of 500 nm in between;

[0060] 5. On the Pd electrodes 001/005, a gate dielectric material HfO.sub.2 is grown by electron beam lithography and atomic layer deposition (ALD) on the electrodes and on the carbon nanotube film in the channels between the electrodes, which forms the gate dielectric layer 002 having a thickness of 8 nm;

[0061] 6. Near the source electrode, Pd is evaporated as the main gate electrode 003 by electron beam lithography and electron beam evaporation. The main gate electrode 003 has a thickness of 15 nm. Near the drain electrode, Pd is evaporated as the auxiliary gate electrode 004 by electron beam lithography and electron beam evaporation. The auxiliary gate electrode has a thickness of 15 nm. The two electrodes are spaced apart by a distance about 50-100 nm;

[0062] 7. Next to these electrodes, Sc electrodes 006/010 are formed, by electron beam lithography and electron beam evaporation. The Sc electrodes have a thickness of 60 nm, a width of 300 nm, and a spacing 500 nm in between;

[0063] 8. On the pair of Sc electrodes 006/010, a gate dielectric material HfO.sub.2 is grown by electron beam lithography and atomic layer deposition (ALD) on the electrodes and on the carbon nanotube film in the channels between the electrodes, which forms the gate dielectric layer 007 having a thickness of 8 nm;

[0064] 9. Near the source electrode, Pd is evaporated as the main gate electrode 008 by electron beam lithography and electron beam evaporation. The main gate electrode 008 has a thickness of 15 nm. Near the drain electrode, Sc is evaporated as the auxiliary gate electrode 009 by electron beam lithography and electron beam evaporation. The auxiliary gate electrode has a thickness of 15 nm. The distance between the two electrodes is about 50-100 nm;

[0065] 10. An Au electrode is made using electron beam lithography and electron beam evaporation, to form the wiring 011 and the wiring 012. The Au electrode thickness is about 40 nm. In the P-type transistor, the auxiliary gate electrode 004 near the drain electrode is connected to the grounded source electrode 010 by of by a wiring 011 connected to the GND. In the N-type transistor, the auxiliary gate electrode 009 near the drain electrode is connected to the source electrode 001 at VDD through a connection line 012;

[0066] 11. An Au electrode is made using electron beam lithography and electron beam evaporation, to form the wiring 013 and the wiring 014. The Au electrode thickness is about 150 nm. As shown in FIG. 3C, the main gate electrode 003 near the source electrode and the main gate electrode 008 are connected by a wiring 013. The Pd drain electrode 005 and the Sc drain electrode 006 are connected via wires 014. If any two of the intermediate wire electrodes have overlap, an insulating spacer layer 017 in the dashed box is sued for isolation. The insulating spacer layer 17 in this embodiment is formed by a crosslinked PMMA that has been bombarded by an electron beam at a high dose, and has a thickness of approximately 60-100 nm; and

[0067] 12. The method and approach described in this invention can be applied to any transistor and all of their related circuits with semiconductors in general, not just for the small band-gap materials nor just for inverters.

[0068] The above embodiments are only used to illustrate the technical solution of the present invention but not to limit it. Those skilled in the art can modify or equivalently replace the technical solution of the present invention without departing from the spirit and scope of the present invention. The scope of protection shall be subject to the claims.