Semiconductor device with high voltage field effect transistor and junction field effect transistor

Abstract

Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.

Claims

1. A semiconductor device comprising: a first junction field effect transistor (JFET) comprising: a first N-type well region disposed in a substrate; a second N-type well region abutting the first N-type well region; a first JFET source region disposed in the first N-type well region; a common drain region disposed in the second N-type well region; and a first high voltage field effect transistor (HVFET) comprising: a first P-type well region formed in the substrate; a first HVFET source region disposed in the first P-type well region; the common drain region disposed in the second N-type well region and shared by the first JFET and the first HVFET; and a first gate electrode formed on the first P-type well region and disposed between the first HVFET source and the common drain region.

2. The semiconductor device of claim 1, wherein a maximum vertical length of the first JFET source region is greater than a maximum vertical length of the common drain region.

3. The semiconductor device of claim 1, wherein the first JFET has a rectangular shape in a plan view.

4. The semiconductor device of claim 3, wherein the rectangular shape has a vertical length greater than a horizontal length.

5. The semiconductor device of claim 1, wherein the first N-type well region has a cross-sectional area smaller than a cross-sectional area of the second N-type well region.

6. The semiconductor device of claim 1, wherein the first N-type well region has a maximum depth smaller than or equal to a maximum depth of the second N-type well region with respect to a top surface of the substrate respectively.

7. The semiconductor device of claim 1, further comprising a P-type gate region disposed between the first N-type well region and the second N-type well region.

8. The semiconductor device of claim 1, further comprising a second HVFET comprising: a second P-type well region formed in the substrate; a second HVFET source region disposed in the second P-type well region; the common drain region disposed in the second N-type well region; and a second gate electrode disposed between the second HVFET source region and the common drain region, wherein the common drain region is shared by the first HVFET and the second HVFET.

9. The semiconductor device of claim 1, further comprising a second JFET comprising: a third N-type well region spaced apart from the first N-type well region; a fourth N-type well region spaced apart from the second N-type well region; a second JFET source region disposed in the third N-type well region; and a second common drain region disposed in the fourth N-type well region.

10. The semiconductor device of claim 8, wherein the first JFET source region does not protrude outwardly from a virtual line connected between an end of the first gate electrode and an end of the second gate electrode.

11. The semiconductor device of claim 1, wherein the first JFET source region has a length in a vertical direction perpendicular to the first gate electrode having a length in a horizontal direction in a plan view.

12. A semiconductor device comprising: a junction field effect transistor (JFET) comprising: an N-type well region disposed in a substrate; a first JFET source region disposed in the N-type well region; and a common drain region disposed in the N-type well region; and a first high voltage field effect transistor (HVFET) comprising: a first P-type well region spaced apart from the N-type well region; a first field oxide film formed over the first P-type well region; a first gate electrode formed over the first field oxide film; and a first field plate formed over the first field oxide film to overlap the first gate electrode, wherein the common drain region is shared by the JFET and the first HVFET.

13. The semiconductor device of claim 12, wherein the N-type well region comprises: a first well region; and a second well region abutting the first well region, and wherein the first JFET source region and the common drain region are formed in the first well region and the second well region, respectively.

14. The semiconductor device of claim 12, wherein the N-type well region has a maximum depth larger than that of the first P-type well region with respect to a top surface of the substrate.

15. The semiconductor device of claim 14, further comprising a P-type buried layer spaced apart from a bottom surface of the first field oxide film.

16. The semiconductor device of claim 12, further comprising a second HVFET comprising: a second P-type well region spaced apart from the N-type well region; a second field oxide film formed over the second P-type well region; a second gate electrode formed over the second field oxide film; and a second field plate formed over the second field oxide film to overlap the second gate electrode, wherein the common drain region is shared by the first HVFET and the second HVFET.

17. The semiconductor device of claim 16, wherein the first and second HVFETs further comprise a first HVFET source region and a second HVFET source region, respectively.

18. The semiconductor device of claim 16, wherein the first JFET source region does not protrude outwardly from a virtual line connected between an end of the first gate electrode and an end of the second gate electrode.

19. The semiconductor device of claim 12, wherein the first JFET source region has a length in a vertical direction perpendicular to the first gate electrode having a length in a horizontal direction in a plan view.

20. The semiconductor device of claim 12, wherein the JFET further comprises a P-type gate region formed in the N-type well region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram illustrating a semiconductor device according to embodiments.

(2) FIG. 2 is a top-view of a semiconductor device according to a comparative example.

(3) FIG. 3 is a top-view of an embodiment of a semiconductor device.

(4) FIG. 4 is a diagram in which a portion of the semiconductor device of FIG. 3 is enlarged.

(5) FIG. 5 is a cross-sectional view taken along the line A-A of the semiconductor device 1 of FIG. 3.

(6) FIG. 6 are cross-sectional views of embodiments of the semiconductor device 1 of FIG. 3 along line B-B.

(7) FIG. 7 is a top-view of another embodiment of a semiconductor device.

(8) FIG. 8 are cross-sectional views of embodiments of the semiconductor device 1 of FIG. 7 along line C-C.

(9) FIG. 9 are cross-sectional views of embodiments of the semiconductor device 1 of FIG. 7 along line D-D.

(10) FIG. 10 is a top-view of another embodiment of a semiconductor device.

(11) FIG. 11 is a top-view of an embodiment of a semiconductor device.

(12) FIG. 12 is a V-I graph according to an operation of a semiconductor device according to an embodiment and a comparative example.

(13) FIG. 13 are contour map of equipotential electric field line of a semiconductor device of a comparative example and an embodiment.

(14) Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

(15) The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.

(16) The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

(17) Throughout the specification, when an element, such as a layer, region, or substrate, is described as being on, connected to, or coupled to another element, it may be directly on, connected to, or coupled to the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being directly on, directly connected to, or directly coupled to another element, there can be no other elements intervening therebetween.

(18) Spatially relative terms such as above, upper, below, and lower may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being above or upper relative to another element will then be below or lower relative to the other element. Thus, the term above encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

(19) The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms comprises, includes, and has specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

(20) For convenience of explanation, in a top-view of a semiconductor device, a part in which an external electrode D is disposed is referred to as a head, and a part in which a common drain region connected to an external electrode D is divided into two parts and is arranged long is referred to as a tail. However, it will be clearly understood that embodiments of the following disclosure are not limited to the above-mentioned names, but may be variously named, which will be apparent to those skilled in the art.

(21) In addition, in the following description, if a substrate of a semiconductor device is P-type, a well region may be N-type in an embodiment. If a substrate of a semiconductor is N-type, a well region may be P-type in another embodiment.

(22) The following description is provided to suggest a semiconductor device having the structure of a Junction Field Effect Transistor (JFET) and a High Voltage Field Effect Transistor (HVFET) that minimize an area, thereby improving integration degree.

(23) The following description is also provided to suggest a semiconductor device having a JFET that may control pinch-off feature of a JFET while maintaining on-resistance feature of a HVFET.

(24) The following description is also provided to suggest a semiconductor device having a JFET that may control a current amount while maintaining on-resistance feature of the JFET.

(25) The following description is also provided to suggest a semiconductor device that allows electric field of a HVFET to be distributed uniformly without being affected by addition of a JFET.

(26) The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.

(27) FIG. 1 is a block diagram illustrating a semiconductor device according to embodiments.

(28) According to FIG. 1, in order to implement a Junction Field Effect Transistor (JFET) 10 and a High Voltage Field Effect Transistor (HVFET) 20. Here, the JFET 10 is also referred to as Tap-JFET. The semiconductor device 1 converts an alternating current (AC) input 3 into a direct current (DC) voltage signal in a high voltage at a rectifier 2 and receives it. In the HVFET 20, an application device 6 is connected to an end of a source S, and a control IC 5 is connected to an end of a gate G. The application device 6 to which the semiconductor device 1 is connected may be a USB type C in an embodiment and may be a LED lighting driver in another embodiment, but embodiments of the present description are not limited thereto and include various devices using a HVFET and a JFET together. JFET 10 and HV NMOS 20 are integrated as one chip 1. The one chip (semiconductor device) 1 may use one common drain to integrate the JFET 10 and HV NMOS 20. The entire chip area is reducing by embedding the JFET 10 in a certain region of the HVFET 20.

(29) FIG. 2 is a plan view of a semiconductor device according to a comparative example.

(30) Referring to FIG. 2, a semiconductor device 1 includes a HVFET 20 and a JFET 10.

(31) The JFET 10 includes an N-type source region (first N+ doped region) 110-S, an N-type drain region 140-D (second N+ doped region), and a P-type gate region 170, and the JFET 10 includes the first N-type well region 310.

(32) The HVFET 20 includes an N-type drain region (second N+ doped region) 140-D formed in a substrate 201, an N-type HVFET source regions 210-S, 211-S (third N+ doped regions), a second N-type well region 320 and a P-type well region 112-1, 112-2. The HVFET 20 shares a drain region 140-D with the JFET 10. Thus, the drain region 140-D becomes a common drain region for JFET 10 and HVFET 20.

(33) In the semiconductor device 1 of the comparative example, the source region 110-S and the first N-type well region 310 of the JFET 10 are extended outwardly to the boundary of the area of the HVFET 20, such that T-shaped JFET 10 is formed in the semiconductor device 1 in a plan view. T-shaped JFET 10 has an extra area of the first N-type well region 310. Due to the extra area of the first N-type well region 310. The amount of the N-type impurities (dopants) in the semiconductor device 1 may increase. N-type impurities (dopants) and P-type impurities (dopants) in the semiconductor device 1 are unbalanced. That is, an electrical field in the semiconductor device 1 of the comparative example is not uniformly distributed. The electric field may be locally concentrated on a certain portion of the semiconductor device 1, due to the increased amount of the N-type impurities. As a result, a breakdown voltage may be decreased in the semiconductor device 1 (see Old in FIG. 12).

(34) FIG. 3 is a plan view of an embodiment of a semiconductor device. An N-type well region 300 includes the N-type well region 310 and the N-type well region 320. For convenience of the description, hereinafter the N-type well region 310 of the JFET 10 is referred to as a first N-type well region 310, and the N-type well region 320 of the HVFET 20 is referred to as a second N-type well region 320. The area of the first N-type well region 310 is remarkably smaller than an area of the second N-type well region 320. The small area of the first N-type well region 310 is intended to minimize the increase of total N-type dopants.

(35) Referring to FIG. 3, in a plan view (top view), the first N-type well region 310 of the JFET 10 of the semiconductor device 1 has a rectangular shape. Thus, an area of the first N-type well region 310 of the JFET 10 in FIG. 3 is smaller than an area of the first N-type well region 310 of the JFET 10 in FIG. 2. The JFET 10 is embedded in the HVFET 20. That is, the JFET 10 is not formed to be protrusive outwardly from a border of the HVFET 20. Thus, an overall shape of the HVFET 20 combined with the JFET 10 is a rectangle.

(36) Due to the small area of the first N-type well region 310, the amount of the N-type impurities is not increased much, compared to the comparative example illustrated in FIG. 2. N-type impurities and P-type impurities in the semiconductor device 1 are balanced. Therefore, the semiconductor device 1 according to the embodiment may allow a breakdown voltage in a predetermined range (see New in FIG. 12) and also minimize the chip size.

(37) The semiconductor device 1 includes a JFET 10 in the first area 400 and a HVFET 20 in the second area 500. All of the N-type well regions 310 and 320 are formed in a substrate 201. The source region 110-S of the JFET 10 is an N+ doped region formed in the first N-type well region 310. A vertical length of the source region 110-S of the JFET 10 is greater than a vertical length of the drain region 140-D of HVFET 20 in a Y-direction in a plan view. A P-type gate region 170 of the JFET 10 is formed between the first N-type well region 310 and the second N-type well region 320. The P-type gate region 170 is formed in the substrate 201.

(38) The HVFET 20 includes a common drain region 140-D (a second N+ doped region), a HVFET source region 210-S, 211-S, and a gate electrode 221-G, as illustrated in the second area 500. A maximum vertical length of the source region 110-S of the JFET 10 is greater than a maximum vertical length of the drain region 140-D of HVFET 20 in a Y-direction in a plan view.

(39) In addition, the HVFET 20 includes a P-type well region 112. The channel region and HVFET source region 210-S of the HVFET 20 are formed in the P-type well region 112.

(40) The HVFET 20 may further include a field plate 160. The field plate 160 may comprise metal or polycrystalline silicon to reduce the electric field on the semiconductor device 1, thereby increasing a breakdown voltage of the semiconductor device 1.

(41) FIG. 4 is a diagram in which the region 400 of FIG. 3 illustrating an embodiment of the present description is enlarged. Referring to FIG. 4, the N-type well region 300 includes, in a direction parallel to a surface of a substrate 201, the first N-type well region 310 having a first width w1 and a second N-type well region 320 having a second width w2. The first N-type well region 310 includes a source region 110-S (a first N+ doped region) of a JFET 10 so that the source region of JFET 10 and the first N-type well region 310 can be formed to shape a rectangular. The source region 110-S of the JFET 10 has a vertical length SL1 greater than a horizontal length (width) SW1 in a plan view. The current of the JFET depends on the vertical length SL1 of the source region 110-S as well as the width SW1 of the source region 110-S. If the vertical length SL1 of the source region 110-S increases, the current of the JFET 10 increases. The first N-type well region 310 of the JFET 10 also has a vertical length L1 greater than a horizontal length (width, W1) in a plan view.

(42) FIG. 5 is a cross-sectional view of an embodiment of a semiconductor, which is the cross-sectional view taken along line A-A of the semiconductor device 1 of FIG. 3.

(43) Referring to FIG. 5, in the semiconductor device 1, a well region 300 is formed in a substrate 201. In an embodiment, if the substrate has a P-type conductivity, the well region may have an N-type conductivity. In another embodiment, if the substrate has an N-type conductivity, the well region may have a P-type conductivity. The first N-type well region 310 of a JFET 10 is disposed in the substrate 201 and has a first depth d1. A first N+ doped region 110-S is disposed in the first N-type well region 310.

(44) The semiconductor device 1 further includes a second N+ doped region 140-D in an N-type well region 300. The first N+ doped region 110-S and the second N+ doped region 140-D are disposed spaced apart from each other on a top surface of the substrate. The first N+ doped region is a source region of the JFET, and the second N+ doped region is a drain region of the JFET.

(45) The N-type well region 300 includes the first N-type well region 310 having a first depth d1 from a top surface of the substrate 201 and a second N-type well region 320 having a second depth d2 from the top surface of the substrate 201. According to various embodiments, the first depth d1 and the second depth d2 may be equal (that is, d1=d2), or the first depth d1 may be smaller than the second depth d2 as illustrated in FIG. 5 (that is, d1<d2).

(46) The semiconductor device 1 includes a P-type gate region 170 that is disposed in the N-type well region 300 and has a third depth smaller than the respective first and second depths. The P-type gate region 170 is disposed closer to the source region 110-S than the drain region 140-D. The P-type gate region 170 may be maintained at a ground voltage in an embodiment, but may be maintained at a different voltage in another embodiment.

(47) The semiconductor device 1 may further include a P+ doped region (not illustrated) in the P-type gate region 170 in an embodiment. To the P+ doped region, a ground voltage may be applied via a terminal (not illustrated) according to an embodiment, and a different voltage may be applied according to another embodiment.

(48) A drain region of a HVFET 20 and a JFET 10, that is, the second N+ doped region 140-D is formed in the second N-type well region 320, and the drain region 140-D is formed as N-type and is connected to the common drain terminal 150-D. The common drain terminal 150-D is made of a metal wire.

(49) The semiconductor device 1 may further include a field plate 160 on a surface of a field oxide film 120 disposed closer to the drain region 140-D than the source region 110-S. The field plate 160 is connected to a common drain region.

(50) The source region 110-S of the JFET 10 is formed in the first N-type well region 310, and the source region 110-S is formed as N-type and is connected to the source terminal 250-S of the JFET 10. The source terminal 250-S is made of a metal wire.

(51) The JFET source region and the first N-type well region 310 are formed in a boundary of the HVFET 20, but is not extended into outside the HVFET 20, as illustrated in FIG. 3. The first N-type well region 310 and the second N-type well region 320 each are initially formed spaced apart by a certain distance, and subsequently, they meet at a certain point H after going through a heat treatment at a high temperature. The second N-type well region 320 and the first N-type well region 310 are formed by ion implantation at an equal impurity concentration, and a diffusion region 330 is formed by diffusion of ion-implanted N-type dopants.

(52) The diffusion region 330 includes a concave groove H. An N-type impurity concentration of the diffusion region 330 may be lower than that of the first N-type well region 310 or the second N-type well region 320. A depth of a bottom surface of the diffusion region 330 may be lower than or equal to that of the first N-type well region 310 or the second N-type well region 320.

(53) According to embodiments, a maximum depth d1 of the first N-type well region 310 may be equal to or different from a maximum depth d2 of the second N-type well region 320.

(54) In an embodiment, depending on an area of the source region 110-S of the JFET, the maximum depth d1 of the first N-type well region 310 may be smaller than the maximum depth d2 of the second N-type well region 320 (d1<d2), but in another embodiment, the respective depths may be equal to each other (d1=d2) by adjusting the implanted N-type impurity ions. However, a cross-section area of the first N-type well region 310 is quite less than a cross-section area of the second N-type well region 320, which is the same when viewed in a plan view as well.

(55) Since the entire N-type dopant concentration 300 increases as the cross-section area of the first N-type well region 310 becomes larger, the entire N-type dopant concentration may be adjusted by the cross-section area of the first N-type well region 310. However, an issue occurs in a breakdown voltage if the dopant concentration of the first N-type well region 310 exceeds a certain level; thus, a degree of dopant implantation of the first N-type well region 310 is properly adjusted to such a concentration that the reduced surface electric field (RESURF) will not collapse.

(56) A field oxide film 120 may be formed on a surface of the substrate between a drain region 140-D and the source region 110-S. The field oxide film 120 is formed by Local Oxidation of Silicon (LOCOS) process or Shallow Trench Isolation (STI) process.

(57) The semiconductor device 1 may further include a buried impurity layer 130, and the buried impurity layer 130 may be electrically connected to the substrate 201 (see FIG. 6). For example, the buried impurity layer 130 may be formed in the N-type well region 300 in parallel with a top surface of the substrate 201. The buried impurity layer 130 may be doped with P-type impurity ions and may be formed to cross the second N-type well region 320, the first N-type well region 310, and the diffusion region 330. The buried impurity layer 130 is spaced apart by a certain distance from and under the field oxide film 120. The buried impurity layer 130 may be formed in a horizontal direction of a bottom surface of the field oxide film 120. In another example, the buried impurity layer 130 may be formed directly below the field oxide layer without spaces. In the present description, one buried impurity layer is suggested, but in another embodiment, at least two buried impurity layers may be formed spaced apart from each other in a vertical direction with respect to a top surface of the substrate 201. Also, the breakdown voltage and the on-resistance feature of the JFET 10 may vary depending on the number of the buried impurity layers 130.

(58) The substrate 201 is connected to a ground reference voltage. An output voltage of a source terminal 250-S of the JFET 10 is determined according to the voltage difference between the substrate 201 and the drain region 140-D.

(59) A P-type gate region 170 of the JFET 10 is formed by implanting P-type impurity ions into the N-type well region 300. The P-type gate region 170 is formed through the P-type buried impurity layer 130 in contact with the bottom surface of the field oxide film 120. The P-type gate region 170 of the JFET 10 is electrically connected to the substrate 201 and is grounded.

(60) A pinch-off may occur due to a potential difference between the substrate 201 and the source region 110-S. Thus, a pinch-off voltage V.sub.pinch-off can be adjusted by applying a certain voltage to the source region 110-S of the JFET and setting the P-type gate region 170 to a ground voltage. Because the common drain region 140-D is remote from the P-type gate region 170, the electric potential of the drain at the P-type gate region 170 becomes small. The depletion is generally caused by the source region 110-S near the P-type gate region 170, not by the potential different between the drain and the P-type gate region, thereby causing a pinch-off.

(61) When the pinch-off occurs in the diffusion region 330, the resistance of the N-type well region 300 between the common drain terminal 150-D and the source terminal 250-S of the JFET rapidly increases. Even if the input voltage of the common drain terminal 150-D is kept increased, the output voltage of the source terminal 250-S is maintained at a certain pinch-off voltage. However, if the input voltage is below or equal to the pinch-off voltage, the output voltage of the source terminal 250-S of the JFET increases in proportion to the input voltage of the common drain terminal 150-D. That is, even when a high input voltage is input to the drain region, the JFET 10 controls the amount of voltage so that it does not exceed a specific voltage, thereby protecting an internal circuit (e.g., the control Integrated Circuit of FIG. 1) connected to the source terminal 250-S.

(62) FIGS. 6(a) and 6(b) are cross-sectional views of an embodiment of the semiconductor device, which is a cross-sectional view taken along the line B-B of the semiconductor device 1 of FIG. 3.

(63) Referring to FIG. 6(a), in a semiconductor device 1 according to an embodiment, a second N-type well region 320 is disposed in a substrate 201, and a common drain region 140-D is disposed in one upper side of the well region 300. The common drain region 140-D is electrically connected to a common drain terminal 150-D, and a field oxide film 120 is formed on remaining top surface of the substrate 201 or the second N-type well region 320 except for the common drain region 140-D.

(64) The buried impurity layer 130 may be formed in the second N-type well region 320 and P-type substrate 210, being spaced apart from a bottom surface of the field oxide film 120 by a certain distance under the field oxide film 120. In another embodiment, a buried impurity layer 130 may be formed in the second N-type well region 320, being in contact with the bottom surface of the field oxide film 120 rather than being spaced apart therefrom. In another embodiment, the buried impurity layer 130 may be a plurality of layers.

(65) Referring to FIG. 6(b), the semiconductor device 1 according to another embodiment may further include a bulk contact region 161.

(66) The bulk contact region 161 may be formed on a top surface of the substrate 201 in which the second N-type well region 320 is not formed. The bulk contact region 161 is electrically connected to a pick-up terminal 165. The bias to be applied to the substrate 201 varies depending on the bias applied to the pick-up terminal 165, so that the pinch-off voltage of the JFET varies depending on the voltage difference between the common drain terminal 150-D and the pick-up terminal 165.

(67) The field oxide film 120 is formed between the drain region 140-D and the bulk contact region 161 and formed on the upper surface of the substrate 201 or the second N-type well region 320.

(68) In addition, according to various embodiments, the semiconductor device of the present description 1 may include a P-type gate region 170 and may apply a certain voltage to an electrode (not illustrated) connected to the P-type gate region 170.

(69) In addition, according to various embodiments, the semiconductor device 1 may include a bulk contact region 161 on the upper surface of the substrate 201 and may apply a bias to a pick-up electrode 165.

(70) FIG. 7 is a top-view of an embodiment of a semiconductor device.

(71) Referring to FIG. 7, it is similar to FIG. 3 but further includes gate electrodes 221-G1, 221-G2. The gate electrodes 221-G1, 221-G2 are used as a gate electrode of a HVFET 20. Each of the gate electrodes 221-G1, 221-G2 is disposed in a region in which a source region 110-S of a JFET is not disposed. Each of the gate electrodes 221-G1, 221-G2 is symmetrically disposed on both side surfaces of the substrate 201. In one example, an end of the gate electrode 221-G1, or 221-G2 may be formed extending horizontally from the first N-type well region 310. The HVFET source region 210-S, 211-S of the HVFET 20 is formed at a side surface of each gate electrode. The common drain region 140-D is disposed between the first gate electrode 221-G1 and the second gate electrode 221-G2. The source region 110-S and the first N-type well region 310 are disposed between the first gate electrode 221-G1 and the second gate electrode 221-G2. The source region 110-S of the JFET and the HVFET source region 210-S, 211-S of the HVFET 20 are formed spaced apart from each other. Each of the P-type well regions 112-1, 112-2 is formed adjacent to each of the gate electrodes 221-G1, 221-G2 of the HVFET.

(72) FIG. 8 is a cross-sectional view of the semiconductor device illustrated in FIG. 7, which is a cross-sectional view of the semiconductor device 1 taken along the line C-C of FIG. 7.

(73) In the semiconductor device 1 according to an embodiment, a field oxide film 120 is disposed on a substrate 201.

(74) Each of the gate electrodes 221-G1, 221-G2 of HVFET 20 is disposed on a top surface of the field oxide film 120. The semiconductor device 1 further includes a P-type buried impurity layer 130 disposed spaced apart from a bottom surface of the field film and having a third depth d3.

(75) The semiconductor device 1 further includes first and second P-type well regions 112-1, 112-2. As an embodiment, referring to FIG. 8(a), each of the first and second P-type well regions 112-1, 112-2 is disposed apart from the P-type buried impurity layer 130 and has a fourth depth d4, which is a greater than the third depth d3 (d3<d4). The semiconductor device 1 further includes first and second P+ doped regions 301-1, 301-2 respectively disposed in the first and second P-type well regions.

(76) The semiconductor 1 further includes a plurality of field plates 222 formed on the field oxide film 120. The pluralities of field plates 222 are formed spaced apart from each other, so that at least each portion of them are overlapped.

(77) Referring to FIG. 8(b) as another embodiment, first and second P-type well regions 112-1, 112-2 may be merged as one well region, different from the embodiment of FIG. 8(a). That is, the first and second P-type well regions 112-1, 112-2 and a third P-type well region 112-3 may be formed as one P-type well region 112.

(78) FIG. 9 is another cross-sectional view of the semiconductor device 1 illustrated in FIG. 7, taken along the line D-D.

(79) Referring to FIG. 9, the semiconductor device 1 includes at least a P-type well region 112-1, 112-2, the first N-type well region 310, and a field oxide film 120.

(80) The first and second field oxide films 120 are disposed on a top surface of the substrate 201, and the first N-type well region 310 having a fifth depth d5 is disposed on the top surface of the substrate 201.

(81) The semiconductor device 1 further includes at least one first N+ doped region 110-S (a source region of the JFET) disposed in the first N-type well region 310.

(82) The first and second P-type well regions 112-1, 112-2 are disposed symmetrically on both sides of the first N-type well region 310 and spaced apart from the first N-type well region 310, and they have a sixth depth d6 less than the fifth depth d5.

(83) The semiconductor device 1 further includes first and second P+ doped regions 301-1, 301-2 respectively disposed in the first and second P-type well regions 112-1, 112-2.

(84) The semiconductor device 1 further includes first and second gate electrodes 221-G1 and 221-G2. The first and second gate electrodes 221-G1 and 221-G2 are spaced apart in a vertical direction of a plane of the substrate 201 and overlapped with the first and second P-type well regions 112-1, 112-2. The first and second gate electrodes 221-G1 and 221-G2 are disposed on the field oxide film 120.

(85) In addition, the semiconductor device 1 further includes first and second field plates 222 formed on the first and second field oxide film 120. The first and second field plates 222 are respectively spaced apart in a vertical direction from and overlapped with the first and second gate electrodes 221-G1 and 221-G2 and the plane of the substrate.

(86) The semiconductor device of the present description may vary the width of the first and second P-type well regions according to various embodiments. As illustrated in FIG. 9(b), the width of the first and second P-type well regions may be set as wider compared to FIG. 9(a), and thus, a breakdown voltage may be adjusted to be larger. That is, if the first and second P-type well regions 112-1, 112-2 are disposed near the first N-type well region 310, the area of a depletion region is increased much, and thus, a breakdown voltage may be increased.

(87) FIG. 10 is a top-view of another embodiment of a semiconductor device. For convenience of description, differences from FIG. 3 will be mainly described.

(88) Referring to FIG. 10, a source region 110-S of the JFET may be formed in the N-type well region 310 and it is extended vertically longer on a side surface of the HVFET 20 different from FIG. 3. The first source region 110-S1 extends from the second gate electrode 221-G2 toward the first gate electrode 221-G2 in a Y-direction, such that the first source region 110-S has a length greater than a width. The vertical length of source region 110-S as well as N-type well region 310 is increased together. If the vertical length SL1 of the source region 110-S increases, the current of the JFET increases. The source region 110-S is formed longer than that of the embodiment of FIG. 3, so the current of the JFET in FIG. 10 is higher than a JFET current in FIG. 3. The vertical length of the source region 110-S of JFET 10 is greater than a vertical length of the common drain region 140-D. The vertical length of the N-type well region 310 of JFET 10 is also greater than a vertical length of the common drain region 140-D. The length of the source region is controllable or adjustable than the drain region. The JFET current can be increased by increasing length of the source region. If the length of the source region 110-S of JFET 10 becomes longer without change in the HVFET 20, only the amount of current may be increased while a pinch-off voltage remains the same.

(89) As shown in FIG. 10, an area of the first N-type well region 310 is increased, thus the total N-type dopants are increased. It is required to balance between the N-type dopants and P-type dopants to increase breakdown voltage of HVFET 20. Thus, the P-type well extension region 112E is extended toward to the source region of JFET 10.

(90) FIG. 11 is a top-view of another embodiment of a semiconductor device.

(91) Referring to FIG. 11 as an embodiment, a first source region 110-S1, a first drain region 140-D1, a first gate electrode 221-G1, a second gate electrode 221-G2, a first buried impurity layer 130-1, a first N-type well region 310 and a second N-type well region 320 are formed in the semiconductor device 1. The first source region 110-S1 is disposed at a corner of the semiconductor device 1. The first source region 110-S1 is adjacent to the first gate electrode 221-G1 rather than the second gate electrode 221-G2.

(92) The semiconductor device 1 further comprises a second source region 110-S2, a second drain region 140-D2, a third gate electrode 221-G3, a second buried impurity layer 130-2, a third N-type well region 350 and a fourth N-type well region 360. The second source region 110-S2 is disposed between the second gate electrode 221-G2 and the third gate electrode 221-G3. Second source region 110-S2 of JFETs 10b is formed near the second gate electrode 221-G2. Two JFETs 10a, 10b are formed in the semiconductor device 1. It helps that more JFET current flows in the semiconductor device 1.

(93) FIG. 12 is a V-I curve according to the operation of a semiconductor device.

(94) When measuring voltages and currents in the semiconductor device 1 of the comparative example (that is, Old) illustrated in FIG. 2, a well region 310 for inserting a JFET is further implanted into an outer of a HVFET. The well region 310 is extended to outside the HVFET 20, resulting in decreasing a breakdown voltage at or below 200 V.

(95) However, in the case of the semiconductor device (that is, New) of the present description, a breakdown voltage is near 1000 V, which is because a charge or dopant amount between an N-type impurity and a P-type impurity is balanced. In contrast, in the case of the semiconductor device (Old), a breakdown voltage is at or below 200 V. This indicates that it is important to design the JFET to be placed inside the HVFET 20.

(96) FIG. 13(a) is a graph of an electric field distribution according to the operation of the semiconductor device of the comparative example, and FIG. 13(b) is a graph of an electric field distribution according to the operation of the semiconductor device of the present description.

(97) FIG. 13(a) depicts a contour map of the equipotential electric field line in the case of the comparative example. The electric field lines of the comparative example are locally concentrated at a specific point. This result is caused by the imbalance of the total N-type charge amount and the total P-type charge amount in the HVFET 20. When the N-type well region 310 including the source region of the JFET is formed outside the HVFET 20, the RESURF of the HVFET collapses. Thus, the breakdown voltage is lowered to 200 V or less as illustrated in FIG. 12.

(98) However, in the case of the semiconductor device of the present description (that is, New), the electric field is uniformly distributed as illustrated in FIG. 13(b); as a result, the breakdown voltage is near 1000 V. This shows that it is important to design the source region 110-S and the first N-type well region 310 of JFET 10 to be arranged within an area or boundary of the HVFET 20.

(99) A semiconductor device according to the present description allows the JFET and the HVFET to share a drain, thereby improving the integration degree.

(100) In addition, a semiconductor device according to the present description allows the JFET to be fully inserted into the HVFET, thereby having advantages in design.

(101) In addition, a semiconductor device according to the present description forms a P-type well region of the JFET in an N-type well region in a channel region of the HVFET in a direction toward the channel width, thereby individually controlling the pinch-off feature of the JFET while maintaining an electric feature of the HVFET.

(102) In addition, a semiconductor device according to the present description reduces the area of a well region for a source region of the JFET, thereby having an effect that RESURF does not collapse.

(103) In addition, a semiconductor device according to the present description reduces the area of a well region of the JFET, and thus, the electric field is uniformly distributed, thereby having a higher breakdown voltage.

(104) In addition, a semiconductor device according to the present description operates at a relatively high voltage, thereby having an effect that the JFET may be used at the same voltage region together with the HVFET.

(105) In addition, a semiconductor device according to the present description individually controls the area of a source region of the JFET, thereby individually controlling the current amount without any change in pinch-off.

(106) While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.