Electronic package

Abstract

An electronic package is provided, which includes: an insulating layer; an electronic element embedded in the insulating layer and having a sensing area exposed from the insulating layer; and a circuit layer formed on the insulating layer and electrically connected to the electronic element, thereby reducing the thickness of the overall package structure.

Claims

1. An electronic package, comprising: a first insulating layer having opposite first and second surfaces; an electronic element embedded in the first insulating layer and having an active surface with at least a sensing area and a plurality of electrode pads exposed from the first surface of the first insulating layer and an inactive surface opposing the active surface; a first circuit layer formed on the first surface of the first insulating layer, wherein the first circuit layer is in contact with the electrode pads and in electrical connection with the electronic element, and the sensing area is exposed from the first circuit layer; a second circuit layer embedded in the second surface of the first insulating layer and electrically connected to the first circuit layer, wherein the second circuit layer is in contact with a part of the inactive surface of the electronic element and free from being in contact with corner portions of the inactive surface of the electronic element; and a plurality of solid conductive posts embedded in the first insulating layer and electrically connected to the first circuit layer and the second circuit layer, wherein the solid conductive posts are in direct contact with the first circuit layer and the second circuit layer.

2. The electronic package of claim 1, further comprising a second insulating layer formed on the first surface of the first insulating layer and the first circuit layer, wherein the sensing area is exposed from the second insulating layer.

3. The electronic package of claim 2, wherein portions of the first circuit layer are exposed from the second insulating layer.

4. The electronic package of claim 1, further comprising a third insulating layer formed on the second surface of the first insulating layer and the second circuit layer.

5. The electronic package of claim 4, wherein portions of the second circuit layer are exposed from the third insulating layer.

6. The electronic package of claim 1, further comprising a plurality of conductive elements formed on the second surface of the first insulating layer.

7. The electronic package of claim 1, further comprising a redistribution layer (RDL) structure disposed on the second surface of the first insulating layer and electrically connected to the first circuit layer.

8. The electronic package of claim 1, further comprising a transparent element covering the sensing area of the electronic element.

9. An electronic package, comprising: a first insulating layer having opposite first and second surfaces; an electronic element embedded in the first insulating layer and having an active surface with at least a sensing area and a plurality of electrode pads exposed from the first surface of the first insulating layer and an inactive surface opposing the active surface; a first circuit layer formed on the first surface of the first insulating layer, wherein the first circuit layer is in contact with the electrode pads and in electrical connection with the electronic element, and the sensing area is exposed from the first circuit layer; a second circuit layer embedded in the second surface of the first insulating layer and electrically connected to the first circuit layer, wherein the second circuit layer is in contact with a part of the inactive surface of the electronic element and free from being in contact with corner portions of the inactive surface of the electronic element; a plurality of solid conductive posts embedded in the first insulating layer and electrically connected to the first circuit layer and the second circuit layer, wherein the solid conductive posts are in direct contact with the first circuit layer and the second circuit layer; and a second insulating layer covering the sensing area of the electronic element.

10. The electronic package of claim 9, further comprising a third insulating layer formed on the second surface of the first insulating layer and the second circuit layer.

11. The electronic package of claim 10, wherein portions of the second circuit layer are exposed from the third insulating layer.

12. The electronic package of claim 9, further comprising a plurality of conductive elements formed on the second surface of the first insulating layer.

13. The electronic package of claim 9, wherein the second insulating layer is further formed on the first surface of the first insulating layer and the first circuit layer.

14. The electronic package of claim 13, wherein portions of the first circuit layer are exposed from the second insulating layer.

15. The electronic package of claim 9, further comprising a redistribution layer (RDL) structure formed on the second surface of the first insulating layer and electrically connected to the first circuit layer.

16. The electronic package of claim 9, further comprising a transparent element covering the sensing area of the electronic element.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1A is a schematic cross-sectional view of a conventional wire-bonding type package structure;

(2) FIG. 1B is a schematic cross-sectional view of a conventional COB type package structure;

(3) FIG. 1C is a schematic cross-sectional view of a conventional light-sensing package structure;

(4) FIGS. 2A to 2E are schematic cross-sectional views of electronic packages according to a first embodiment of the present disclosure, wherein FIGS. 2A and 2B show other embodiments of FIGS. 2A and 2B, respectively;

(5) FIGS. 3A to 3C are schematic cross-sectional views of electronic packages according to a second embodiment of the present disclosure, wherein FIGS. 3A and 3B show other embodiments of FIGS. 3A and 3B, respectively; and

(6) FIGS. 4A and 4B are schematic cross-sectional views of electronic packages according to a third embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(7) The following illustrative embodiments are provided to illustrate the disclosure of the present disclosure, these and other advantages and effects can be apparent to those in the art after reading this specification.

(8) It should be noted that all the drawings are not intended to limit the present disclosure. Various modifications and variations can be made without departing from the spirit of the present disclosure. Further, terms such as on, first, second, a, etc. are merely for illustrative purposes and should not be construed to limit the scope of the present disclosure.

(9) FIGS. 2A to 2E are schematic cross-sectional views of electronic packages 2a to 2e according to a first embodiment of the present disclosure. The electronic packages 2a to 2e are applicable in, for example, fingerprint identifiers and image sensors.

(10) Referring to FIG. 2A, the electronic package 2a has: a first insulating layer 20 having opposite first and second surfaces 20a, 20b; an electronic element 23 embedded in the first insulating layer 20; a plurality of conductive posts 24 formed in the first insulating layer 20; and a first circuit layer 21 and a second circuit layer 22 formed on the first and second surfaces 20a, 20b of the first insulating layer 20, respectively.

(11) In the present embodiment, the first insulating layer 20 is made of a molding compound, or a dielectric material such as an epoxy resin, polyimide or other photosensitive or non-photosensitive organic resin. According to the practical need, another insulating layer 200 can be formed on the first surface 20a of the first insulating layer 20 and made of a material that is the same as or different from that of the first insulating layer 20. Further, the insulating layer 200 and the first insulating layer 20 can be formed at the same time.

(12) In the present embodiment, the electronic element 23 is a sensor element, which has an active surface 23a with a sensing area 231 and a plurality of electrode pads 230 and an inactive surface 23b opposite to the active surface 23a. The sensing area 231 is a light sensing area or a fingerprint sensing area. The sensing area 231 and the electrode pads 230 of the electronic element 23 are exposed from the first surface 20a of the first insulating layer 20.

(13) Since the electronic element 23 is embedded in the first insulating layer 20, the present disclosure dispenses with the conventional encapsulant, thus reducing the thickness of the overall structure.

(14) The first circuit layer 21 is formed on the first surface 20a of the first insulating layer 20 and in contact with the electrode pads 230 and thus in electrical connection with the electronic element 23. The sensing area 231 of the electronic element 23 is exposed from the first circuit layer 21. In the present embodiment, the first circuit layer 21 is made of such as copper and formed by patterned electroplating, deposition or etching.

(15) The second circuit layer 22 is formed on the second surface 20b of the first insulating layer 20. In the present embodiment, the second circuit layer 22 is embedded in and exposed from the second surface 20b of the first insulating layer 20. The surface of the second circuit layer 22 is flush with or slightly lower than the second surface 20b of the first insulating layer 20.

(16) The second circuit layer 22 is made of such as copper and formed by patterned electroplating, deposition or etching.

(17) Further, a portion of the second circuit layer 22 is in contact with the inactive surface 23b of the electronic element 23 for heat dissipation.

(18) The conductive posts 24 are embedded in the first insulating layer 20 and electrically connecting the first circuit layer 21 and the second circuit layer 22. But the first circuit layer 21 is not electrically connected to the inactive surface 23b of the electronic element 23.

(19) In another embodiment, referring to FIG. 2A, the second circuit layer 22 is not in contact with the inactive surface 23b of the electronic element 23. That is, a portion of the first insulating layer 20 is sandwiched between the second circuit layer 22 and the inactive surface 23b of the electronic element 23. The conductive path constituted by the first circuit layer 21, the conductive posts 24 and the second circuit layer 22 extends below the inactive surface 23b of the electronic element 23.

(20) Since the first circuit layer 21 is in direct electrical connection with the electronic element 23, the present disclosure dispenses with the conventional bonding wires, thus reducing the thickness of the overall structure.

(21) Referring to FIG. 2B, as compared to FIG. 2A, the electronic package 2b further has a plurality of conductive elements 25 formed on the second surface 20b of the first insulating layer 20. In particular, the conductive elements 25 are formed on and electrically connected to the second circuit layer 22.

(22) In the present embodiment, the conductive elements 25 are, for example, solder balls, solder bumps or copper bumps.

(23) In another embodiment, referring to FIG. 2B, similar to FIG. 2A, the second circuit layer 22 is not in contact with the inactive surface 23b of the electronic element 23. That is, a portion of the first insulating layer 20 is sandwiched between the second circuit layer 22 and the inactive surface 23b of the electronic element 23.

(24) Referring to FIG. 2C, as compared to FIG. 2B, the electronic package 2c further has a second insulating layer 26 formed on the first surface 20a of the first insulating layer 20 and the first circuit layer 21, and the sensing area 231 of the electronic element 23 is exposed from the second insulating layer 26. The second insulating layer 26 is made of, for example, a dielectric material.

(25) In addition, the second circuit layer 22 can be omitted, and the conductive elements 25 can be in direct contact with the conductive posts 24.

(26) Referring to FIG. 2D, as compared to FIGS. 2B and 2C, the second insulating layer 26 is a dielectric layer or a solder mask layer, and portions of the first circuit layer 21 are exposed from the second insulating layer 26. For example, the second insulating layer 26 has a plurality of first openings 260 exposing portions of the first circuit layer 21. Alternatively, the surface of the second insulating layer 26 is flush with the surface of the first circuit layer 21 so as to expose the first circuit layer 21.

(27) The electronic package 2d further has a third insulating layer 27 formed on the second surface 20b of the first insulating layer 20 and the second circuit layer 22. The third insulating layer 27 is, for example, a dielectric layer or a solder mask layer.

(28) Portions of the second circuit layer 22 are exposed from the third insulating layer 27 and the conductive elements 25 are formed on the exposed portions of the second circuit layer 22. For example, the third insulating layer 27 has a plurality of second openings 270 exposing portions of the second circuit layer 22. Alternatively, the surface of the third insulating layer 27 is flush with the surface of the second circuit layer 22. As such, the surface of the second circuit layer 22 is exposed from the third insulating layer 27 for mounting the conductive elements 25.

(29) Referring to FIG. 2E, as compared to FIGS. 2C and 2D, the second insulating layer 26 covers and hence seals the sensing area 231 of the electronic element 23.

(30) FIGS. 3A to 3C are schematic cross-sectional views of electronic packages 3a to 3c according to a second embodiment of the present disclosure. The present embodiment differs from the first embodiment in the circuit layer structure.

(31) Referring to FIGS. 3A and 3A, as compared to FIGS. 2A and 2A, the electronic package 3a further has an RDL (Redistribution Layer) structure 30 formed on the second surface 20b of the first insulating layer 20 and electrically connected to the first circuit layer 21 through the second circuit layer 22 and the conductive posts 24.

(32) In the present embodiment, the RDL structure 30 has at least a dielectric layer 300 and a circuit layer 301 formed on the dielectric layer 300 and electrically connected to the second circuit layer 22 through conductive posts 302 formed in the dielectric layer 300.

(33) The circuit layer 301 is exposed from the dielectric layer 300 for mounting the conductive elements 25.

(34) Referring to FIGS. 3B and 3B, the electronic package 3b can further have a characteristic of FIG. 2C or 2D. For example, similar to FIG. 2C, a second insulating layer 26 such as a dielectric layer or a solder mask layer is formed on the first surface 20a of the first insulating layer 20 and the first circuit layer 21, and the sensing area 231 of the electronic element 23 is exposed from the second insulating layer 26.

(35) Referring to FIG. 3C, similar to FIG. 2E, the sensing area 231 of the electronic package 3c is covered by the second insulating layer 26 made of such as a dielectric material.

(36) FIGS. 4A and 4B are schematic cross-sectional views of electronic packages 4a, 4b according to a third embodiment of the present disclosure. The present embodiment differs from the above-described embodiments in that the electronic packages 4a, 4b are applicable in camera lenses. In particular, a transparent element 40 is added.

(37) Referring to FIGS. 4A and 4B, as compared to FIGS. 2D and 3B, the electronic packages 4a, 4b further has a transparent element 40 such as a lens or glass that covers the sensing area 231 of the electronic element 23. For example, the transparent element 40 is attached to the second insulating layer 26. As such, the present disclosure dispenses with the conventional support members so as to reduce the thickness of the overall structure.

(38) In the electronic package 4a of FIG. 4A, the surface of the second insulating layer 26 is flush with the surface of the first circuit layer 21.

(39) On the other hand, in the electronic package 4b of FIG. 4B, the first insulating layer 26 encapsulates the first circuit layer 21.

(40) In the above-described electronic packages 2a to 2e, 3a to 3c and 4a to 4b, the electronic element 23 is embedded in the first insulating layer 20 and the first circuit layer 21 is electrically connected to the electronic element 23. As such, the present disclosure does not need to consider the wire loop of bonding wires or the thickness of an encapsulant as in the prior art. Therefore, the thickness of the first insulating layer 20 is easy to control, thus achieving a better uniformity and a greatly reduced thickness

(41) Further, since the present disclosure uses a non-semiconductor process, the fabrication cost is reduced.

(42) Furthermore, the electronic packages 2a to 2e, 3a to 3c and 4a to 4b can be easily adjusted according to the practical need, thereby improving the design flexibility.

(43) In addition, the above-described embodiments are applicable to LGA (Land Grid Array) or BGA (Ball Grid Array) packages.

(44) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present disclosure, and it is not to limit the scope of the present disclosure. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present disclosure defined by the appended claims.