Electronic Chip Reliably Mounted with Compressive Strain

Abstract

An electronic component includes a carrier and an electronic chip mounted with compressive strain on the carrier. At least a part of a material of the carrier fulfils at least two of the following three criteria: an offset yield point in a range between 100 C. and 300 C. is at least 300 N/mm.sup.2; a yield strength in a range between 100 C. and 300 C. is at least 250 N/mm.sup.2; an electrical conductivity at 20 C. is at least 65% of the International Annealed Copper Standard (IACS).

Claims

1. An electronic component, comprising: a carrier; and an electronic chip mounted with compressive strain on the carrier, wherein at least a part of a material of the carrier fulfils at least two of the following three criteria: an offset yield point in a range between 100 C. and 300 C. is at least 300 N/mm.sup.2; a yield strength in a range between 100 C. and 300 C. is at least 250 N/mm.sup.2; and an electrical conductivity at 20 C. is at least 65% of the International Annealed Copper Standard (IACS).

2. The electronic component of claim 1, wherein the offset yield point in a range between 100 C. and 300 C. is at least 500 N/mm.sup.2.

3. The electronic component of claim 1, wherein the yield strength in a range between 100 C. and 300 C. is at least 500 N/mm.sup.2.

4. The electronic component of claim 1, wherein the electrical conductivity at 20 C. is at least 75% of the IACS.

5. The electronic component of claim 1, wherein a ratio between the offset yield point at 350 C. and the offset yield point at 100 C. is at least 0.75.

6. The electronic component of claim 1, wherein a ratio between the offset yield point at 300 C. and the offset yield point at 100 C. is at least 0.75.

7. The electronic component of claim 1, wherein the material of the carrier comprises a metal and/or an alloy.

8. The electronic component of claim 1, wherein the material of the carrier comprises an alloy of copper with not more than one weight percent of at least one other metal in relation to the copper and the at least one other metal.

9. The electronic component of claim 8, wherein the at least one other metal comprises at least one of zirconium, chromium, silver and zinc.

10. The electronic component of claim 1, wherein the material of the carrier comprises a copper-X alloy comprising primarily copper and up to 1 weight percent of X, X being a sum of zirconium, chromium, silver and zinc.

11. The electronic component of claim 1, wherein the material of the carrier has an overall coefficient of thermal expansion of larger than 10 ppm/K.

12. The electronic component of claim 1, wherein the carrier is a bare metal body.

13. The electronic component of claim 1, wherein the carrier is a leadframe.

14. The electronic component of claim 1, wherein the carrier comprises an electrically insulating structure and an electrically conductive structure.

15. The electronic component of claim 14, wherein the electrically conductive structure fulfils at least two of the three criteria and/or the electrically conductive structure is arranged between the electronic chip and the electrically insulating structure.

16. The electronic component of claim 14, wherein the carrier comprises a thermally conductive structure, wherein the electrically insulating structure is arranged between the thermally conductive structure and the electrically conductive structure, and wherein the thermally conductive structure fulfils at least two of the three criteria.

17. The electronic component of claim 1, wherein a ratio between an area of a main surface of the electronic chip or a sum of areas of a main surface of a plurality of electronic chips mounted on the carrier, and a mounting area of the carrier is at least 50%.

18. A method of manufacturing an electronic component, the method comprising: mounting an electronic chip with compressive strain on a carrier; and providing at least a part of a material of the carrier so as to fulfil at least two of the following three criteria: an offset yield point in a range between 100 C. and 300 C. is at least 300 N/mm.sup.2; a yield strength in a range between 100 C. and 300 C. is at least 250 N/mm.sup.2; and an electrical conductivity at 20 C. is at least 65% of the International Annealed Copper Standard (IACS).

19. The method of claim 18, further comprising: mounting the electronic chip on the carrier at a temperature above 300 C.; and/or mounting the electronic chip on the carrier by diffusion soldering or sintering using a copper sinter paste and/or a silver sinter paste.

20. The method of claim 18, further comprising: cold metal forming or hot metal forming the material of the carrier to adjust hardness and tensile strength.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of the specification, illustrate exemplary embodiments. The illustrations in the drawings are schematically and not to scale.

[0051] In the drawings:

[0052] FIG. 1 illustrates a cross-sectional view of an electronic component according to an exemplary embodiment during mounting an electronic chip on a carrier at elevated temperature;

[0053] FIG. 2 illustrates the electronic component according to FIG. 1 after completion of the mounting procedure and after cooling the electronic component to an operation temperature at which the mounted electronic chip maintains compressive strain; and

[0054] FIG. 3 illustrates a cross-sectional view of an electronic component according to another exemplary embodiment to be mounted on a mounting structure.

DETAILED DESCRIPTION

[0055] Before exemplary embodiments will be described in more detail referring to the figures, some general considerations will be summarized based on which exemplary embodiments have been developed.

[0056] According to an exemplary embodiment, a carrier (in particular formed on the basis of copper) for a strained silicon device (as an example for an electronic chip) is provided. Stiffly mounting such a strained chip on such a carrier may allow obtaining a highly reliable electronic component, package or module. In this context, usage of the strained silicon effect may be advantageous. When the die attach is performed at a high temperature for instance with diffusion soldering, and through a mismatch between the coefficients of thermal expansion (CTE mismatch) of the involved materials as well as through a high temperature difference between mounting temperature and operating temperature, the stiffly mounted die may remain under compressive strain over a wide range of temperatures and operating conditions. This causes an electrically beneficial bandgap narrowing of the material of the electronic chip. According to exemplary embodiments, a particularly appropriate material for the carrier is provided which is appropriate for obtaining the strained silicon effect over a long term by fulfilling a specific combination of design rules, as described below in further detail.

[0057] A conventionally mounting MOSFET on a leadframe (which may be denoted as discrete) may have a low ratio of semiconductor to copper area. As such the compressive strain is high for the silicon and overall low for the bulk of copper. As such, relaxation of the copper/semiconductor stack over the operating time can usually be neglected.

[0058] However, this may be no longer the case if the ratio of semiconductor to copper area becomes higher. In such cases, the larger surface area and bulk of the semiconductor(s) may exhibit a larger stress on the (in particular isolated) copper or IMS (Insulated Metal Substrate) and may lead to significant undesired relaxation of the metal. This may have the impact that the semiconductors may lose their compressive strain over the lifetime of the module. Especially problematic is that widely used carrier material is pronouncedly pliable in the range between operating temperature and die attach, which leads to losing compressive stress when cooling down from die attach.

[0059] In order to at least partly overcome such and/or other shortcomings of conventional approaches, an exemplary embodiment provides an electronic chip (such as a semiconductor die) with compressive strain on the semiconductor using high-performance alloys as metallization part of a chip carrier. Such a chip carrier may be for instance an IMS or a leadframe with however modified material. For instance, such a carrier may be stiffly connected to the electronic chip using diffusion solder, etc.

[0060] Advantageously, this may increase the compressive stress, in particular by avoiding or at least suppressing relaxation while cooling down from die attach. Moreover, such an embodiment may allow maintaining compressive strain over the life-time of the electronic component, which may be denoted as low creep behavior. At the same time, it may be possible to realize a high electric conductivity.

[0061] A highly appropriate metallization material of the carrier may fulfil at least two of three criteria, and preferably all three of the following criteria: [0062] High R.sub.p02: at least 300 N/mm.sup.2 (in particular in the range between 100 C. and 300 C.), preferably at least 500 N/mm.sup.2 [0063] High yield strength in the range between 100 C. and 300 C.: at least 250 N/mm.sup.2, preferably more than 500 N/mm.sup.2 [0064] High electric conductivity: at least 65% IACS, preferably at least 75% IACS.

[0065] Particularly appropriate materials meeting these conditions are for example CuZr0.1 or CuCr0.1Zr, but other metals and/or alloys can also be used. In particular CuZrCr and CuZr alloys may have an excellent yield strength in the temperature range from 100 C. to 300 C.

[0066] Exemplary forms and stackings for providing a carrier of an electronic component according to exemplary embodiments include: [0067] Bare metal leadframe, in particular made from the above materials, having a coefficient of thermal expansion (CTE) above 10 ppm/K, preferably above 14 ppm/K. [0068] Sandwich of metal plus an electric isolation layer, with the compound having a CTE value above 10 ppm/K, preferably above 14 ppm/K. [0069] Sandwich of metal (on the chip side, i.e. facing the electronic chip when mounted) plus an isolation layer plus another metal layer (on a heatsink side, i.e. opposing the electronic chip when mounted), with the compound preferably having a CTE value above 10 ppm/K, preferably above 14 ppm/K (in particular, one or both of the metal components may be made from a high performance alloys as described above, but not necessarily both).

[0070] The electronic component may be assembled using a connection structure providing a stiff die attach (for instance diffusion solder, copper sinter paste, silver sinter paste) at a mounting temperature of preferably above 320 C. Then, the electronic component may be cooled down to room temperature. Later, the electronic component may be used at operating temperature, for instance in the range between 50 C. and 280 C.

[0071] In the assembled device or electronic component, both at room temperature and operating temperature, the semiconductor may be reliably maintained under compressive strain at all times, even for long lifetimes and mission profiles.

[0072] In another exemplary embodiment, the electronic component may be treated with other high temperature die attach procedures, preferably with a stiff and non-relaxing interface.

[0073] FIG. 1 illustrates a cross-sectional view of an electronic component 100 according to an exemplary embodiment during mounting an electronic chip 104 on a carrier 102 at elevated temperature. FIG. 2 illustrates the electronic component 100 according to FIG. 1 after completion of the mounting and after cooling the electronic component 100 to an operation temperature at which the mounted electronic chip 104 maintains compressive strain.

[0074] The shown electronic component 100, package or module comprises carrier 102 and electronic chip 104 mounted with compressive strain on the carrier 102. A stiff connection structure 136 is formed at an interface between carrier 102 and electronic chip 104 and may be for example a solder structure (such as a diffusion solder structure) or a sinter structure (such as a sinter structure formed on the basis of copper sinter paste and/or silver sinter paste).

[0075] The electronic chip 104 may be a semiconductor die, for instance made of silicon.

[0076] In the shown embodiment, the carrier 102 is a layer stack which comprises a central electrically insulating structure 101 and an electrically conductive structure 103 facing the electronic component 104. As shown, the electrically conductive structure 103 is arranged between the electronic chip 104 and the electrically insulating structure 101. Furthermore, the carrier 102 comprises a thermally conductive structure 105. The electrically insulating structure 101 is arranged between the thermally conductive structure 105 and the electrically conductive structure 103.

[0077] The electrically insulating structure 101 may be optionally elastic and may preferably have a non-brittle material property. The thermally conductive structure 105 is an optional heat sink metal.

[0078] The electrically conductive structure 103 being closest to the electronic chip 104 may be a high performance metal, such as CuZr0.1. Highly advantageously, the material of the electrically conductive structure 103 of the carrier 102 fulfils the following three criteria: [0079] an offset yield point R.sub.p02 at 250 C. is at least 500 N/mm.sup.2; [0080] a yield strength at 250 C. is at least 500 N/mm.sup.2; [0081] an electrical conductivity at 20 C. is at least 75% of the International Annealed Copper Standard IACS.

[0082] It is also highly desired that a ratio between the offset yield point R.sub.p02 at 350 C. and the offset yield point R.sub.p02 at 100 C. (i.e. a possible operating temperature of the device) is at least 0.75. When such a low creep behavior is present, there is no risk of a significant loss of the compressive strength of the mounted silicon based electronic chip 104 when cooling down from solder temperature to room temperature.

[0083] Preferably but not necessarily, also the thermally conductive structure 105 fulfils the mentioned three criteria. For example, the thermally conductive structure 105 may be made of the same material as the electrically conductive structure 103.

[0084] Said material meeting the three criteria may be a copper-zirconium alloy, for instance CuZr0.1. Said material may advantageously have an overall coefficient of thermal expansion of larger 14 ppm/K (for instance about 15 ppm/K) at 20 C.

[0085] As shown in FIG. 1, mounting the electronic chip 104 on the carrier 102 may be done at an elevated temperature preferably above 350 C. Mounting the electronic chip 104 on the carrier 102 may be accomplished by soldering such as diffusion soldering, during which connection structure 136 is formed as a solder structure stiffly connecting carrier 102 with electronic chip 104. It is also possible to perform the mounting by sintering, for instance using a copper sinter paste or a silver sinter paste. As a result of this mounting procedure, the connection structure 136 is formed at an interface between carrier 102 and electronic chip 104.

[0086] FIG. 1 shows the electronic component 100 in a configuration where die attach is carried out at a temperature above 350 C. In view of the above-described material selection, a stiff and non-relaxing die attach may be carried out, for instance by diffusion soldering.

[0087] Now referring to FIG. 2, the electronic component 100 is then cooled down, thereby establishing permanent compression strain of the electronic chip 104. This improves the bandwidth properties of the silicon material of the electronic chip 104. Still referring to FIG. 2, the obtained electronic component 100 is shown at an operating temperature being significantly below die attach temperature. For instance, operation temperature may be room temperature. In view of the thermal compression of the materials of the electronic chip 104 and the carrier 102, the silicon material of the electronic chip 104 is compressed, as indicated schematically by reference numeral 200. In contrast to this, another compression occurs with the carrier 102, which may preferably have a higher coefficient of thermal expansion. This is indicated schematically by reference numeral 202. Since the silicon material of the electronic chip 104 may have a significantly smaller CTE value (for example about 3 ppm/K compared to about 15 ppm/K of the electrically conductive structure 103), the higher thermal compression forces acting on the carrier 102 will also result in a strong compression of the material of the electronic chip 104. Since the electronic chip 104 is stiffly connected to the carrier 102 due to the stiff connection structure 136, the electronic chip 104 of the electronic component 100 may therefore remain under permanent compressive stress after cooling down to room temperature or operation temperature of the electronic component 100. As a result of the cooling of the electronic component 100 and in view of the different material properties of the electronic chip 104 on the one hand and the carrier 102 on the other hand, the semiconductor material of the electronic chip 104 remains under compressive stress preferably over the entire lifetime of the electronic component 100.

[0088] In view of the described material selection, a high electric reliability, mechanical reliability, thermal performance and proper maintenance of the compressive strain of the mounted electronic chip 104 may be synergistically combined. The latter may result, in turn, in low switching losses during operation of the electronic component 100.

[0089] Although not shown in FIG. 1 and FIG. 2, the electronic component 100 may be subsequently encapsulated by an encapsulant (see FIG. 3).

[0090] FIG. 3 illustrates a cross-sectional view of an electronic component 100, which is embodied as a Transistor Outline (TO) package, according to an exemplary embodiment. The electronic component 100 can be mounted on a mounting structure 132, here embodied as printed circuit board, for establishing an arrangement 130.

[0091] The mounting structure 132 comprises an electric contact 134 embodied as a plating in a through hole of the mounting structure 132. When the electronic component 100 is mounted on the mounting structure 132, electronic chip 104 of the electronic component 100 is electrically connected to the electric contact 134 via electrically conductive carrier 102, here embodied as a leadframe made of a material meeting the three above-mentioned criteria, of the electronic component 100.

[0092] The electronic component 100 thus comprises the electrically conductive carrier 102, the electronic chip 104 (which is here embodied as a power semiconductor chip) stiffly mounted on the carrier 102 by solder or sinter contact structure 136, and an encapsulant in form of a mold compound 106 encapsulating part of the carrier 102 and part of the electronic chip 104. As can be taken from FIG. 3, a pad on an upper main surface of the electronic chip 104 is electrically coupled to the carrier 102 via a bond wire as electrically conductive contact element 110.

[0093] During operation of the power package or electronic component 100, the power semiconductor chip in form of the electronic chip 104 generates a considerable amount of heat. At the same time, it shall be ensured that any undesired current flow between a bottom surface of the electronic component 100 and an environment is reliably avoided.

[0094] For ensuring electrical insulation of the electronic chip 104 and removing heat from an interior of the electronic chip 104 towards an environment, an electrically insulating and thermally conductive interface structure 108 may be provided which covers an exposed surface portion of the carrier 102 and a connected surface portion of the mold compound 106 at the bottom of the electronic component 100. The electrically insulating property of the interface structure 108 prevents undesired current flow even in the presence of high voltages between an interior and an exterior of the electronic component 100. The thermally conductive property of the interface structure 108 promotes a removal of heat from the electronic chip 104, via the electrically conductive carrier 102, through the interface structure 108 and towards a heat dissipation body 112. The heat dissipation body 112, which may be made of a highly thermally conductive material such as copper or aluminum, has a base body 114 directly connected to the interface structure 108 and has a plurality of cooling fins 116 extending from the base body 114 and in parallel to one another so as to remove the heat towards the environment.

[0095] As used herein, the terms having, containing, including, comprising and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles a, an and the are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0096] It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0097] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.