Metal core solder ball interconnector fan-out wafer level package

Abstract

A fan-out wafer level package is disclosed, which includes: a redistribution layer; a semiconductor chip electrically connected with the redistribution layer through a bump; a protective member protecting the semiconductor chip, wherein a part of the protective member is removed such that the upper surface of the semiconductor chip is exposed in order to dissipate heat and prevent warpage; and an interconnector disposed outside the semiconductor chip at substantially the same level and having a lower part electrically connected with the redistribution layer and an upper part not being covered with the protective member, wherein the interconnector includes a metal core solder ball, the metal core solder ball includes a metal core and a solder buffer between the metal core and the protective member, and the metal core is formed of a combination of copper (Cu), nickel (Ni), and silver (Ag).

Claims

1. A fan-out wafer-level package comprising: a redistribution layer; a semiconductor chip electrically connected to the redistribution layer through a bump; a protective member configured to protect the semiconductor chip; and an interconnector disposed outside the semiconductor chip at substantially the same level as the semiconductor chip, wherein a lower portion of the interconnector is electrically connected to the redistribution layer and a top surface of the interconnector, a top surface of the protective member, and a top surface of the semiconductor chip are positioned to form a substantially uniform planar surface, wherein the interconnector comprises a metal-core solder ball, the metal-core solder ball comprises a metal core and a solder buffer interposed between the metal core and the protective member, an upper portion of the metal-core solder ball comprises a surface of the metal core not covered by the solder buffer, and the metal core comprises a combination of copper (Cu), nickel (Ni), or silver (Ag).

2. The fan-out wafer-level package of claim 1, wherein the interconnector has one of a globular shape or an egg shape.

3. The fan-out wafer-level package of claim 2, wherein the solder buffer is formed of a material having a higher ductility than a metal material of the metal core and includes tin (Sn) solder.

4. The fan-out wafer-level package of claim 2, wherein the solder buffer includes a multilayered structure of solder and nickel (Ni) (or nickel alloy) layers.

5. The fan-out wafer-level package of claim 1, wherein the solder buffer includes a multilayered structure of a conductive layer which is disposed inside thereof and formed of solder or nickel and a nonconductive layer which is disposed outside the conductive layer and formed of a material having a higher ductility than the conductive layer.

6. The fan-out wafer-level package of claim 1, wherein the bump is a stud bump having a pointed end portion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of a semiconductor structure in which a buffer member is interposed between a molding compound and a conductive via plug, according to the related art.

(2) FIG. 2 is a cross-sectional view of a package-on-package (PoP) device in which upper and lower packaging dies are adhered to each other using a plurality of metal plugs, according to the related art.

(3) FIG. 3 is a cross-sectional view of a bottom packaging die further including a protective layer provided on a sidewall of a metal plug according to the related art.

(4) FIG. 4 is a cross-sectional view of a configuration of a fan-out wafer-level package including a metal core according to the present invention.

(5) FIG. 5 is a cross-sectional view of a configuration of a fan-out wafer-level package further including a solder buffer according to the present invention.

(6) FIG. 6 is a cross-sectional view of a configuration of a fan-out wafer-level package further including a sacrificial pad according to the present invention.

(7) FIG. 7 is a cross-sectional view of a configuration of a fan-out wafer-level package further including a heat dissipation pad according to the present invention.

(8) FIG. 8 is a cross-sectional view of a configuration of a fan-out wafer-level package including both a sacrificial pad and a heat dissipation pad according to the present invention.

(9) FIG. 9 is a cross-sectional view of a configuration of a fan-out PoP in which upper and lower packages are connected to each other by interconnectors, according to the present invention.

(10) FIGS. 10A to 10D are cross-sectional views illustrating a process of manufacturing a semiconductor chip according to the present invention.

(11) FIGS. 11A to 11G are cross-sectional views of a process of manufacturing a fan-out package according to the present invention.

(12) FIG. 12 is a flowchart of a process of manufacturing a fan-out package according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(13) Advantages and features of the present invention and methods of achieving the same will be clearly understood with reference to the following detailed embodiments. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The scope of the present invention is defined by the appended claims. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout the specification.

(14) Furthermore, the embodiments of the present invention are described herein with reference to plan and/or cross-section illustrations that are schematic illustrations of the idealized embodiments of the present invention. Accordingly, for example, shapes of illustrated components may be modified as a result of manufacturing techniques and/or tolerances. Thus, the embodiments of the present invention are not to be construed as limited to the particular shapes of regions illustrated herein, but are to be understood as including deviations in shapes that result from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.

(15) Hereinafter, a fan-out wafer-level package (C2FO-WLP) having the above-described configuration according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

(16) Referring to FIG. 4, a C2FO-WLP 100 of the present invention includes a redistribution layer RDL, a semiconductor chip 110 electrically connected to the redistribution layer RDL through stud contacts or bumps 102, interconnectors 120 disposed outside the semiconductor chip 110 to be substantially coplanar with the semiconductor chip 110 and having one side electrically connected to the outside through the redistribution layer RDL, a protective member 130 formed on the redistribution layer RDL, configured to protect the semiconductor chip 110 and the interconnector 120, and configured to expose the other side of the interconnector 120, and a connection member 140 of the redistribution layer RDL.

(17) Here, the interconnector 120 may be formed using a ball mount process prior to an epoxy molding compound (EMC) process of the protective member 130. The conductive ball mount process includes forming a seed layer on a sacrificial substrate (refer to M in FIG. 11A), forming a sacrificial pad (refer to Mp in FIG. 11A) using an RDL process, and dropping a conductive ball on the sacrificial pad Mp.

(18) Referring to FIG. 5, the interconnector 120 of the present invention is formed using the conductive ball. The conductive ball may include a metal-core solder ball.

(19) The metal-core solder ball includes a metal core 120a located at the center thereof and a solder buffer 120b surrounding the metal core 120a.

(20) The metal core 120a may solely include copper (Cu). Alternatively, the metal core 120a may include a combination of a central copper (Cu) portion and a silver (Ag) portion surrounding the central copper (Cu) portion. Alternatively, the metal core 120a may include a triple combination which further includes another metal portion outside the silver portion.

(21) The solder buffer 120b may include lead (Pb) or tin (Sn), which has a relatively low melting point. The solder buffer 120b may include a nickel (Ni) alloy or a silver (Ag) alloy in addition to solder.

(22) In particular, the metal-core solder ball is characterized by being formed by dropping a conductive ball according to a predetermined manual. The formation of the metal-core solder ball includes shaping a ball and dropping the ball on the sacrificial pad Mp.

(23) When the metal-core solder ball has a double structure of the metal core 120a and the solder buffer 120b, the metal-core solder ball may improve conductive characteristics for interconnecting fan-out upper and lower packages and function as a buffer despite a difference in coefficient of thermal expansion (CTE) between the protective member 130 and the metal core 120a.

(24) In addition, oxidation of the interconnector 120 may be suppressed due to the solder buffer 120b. Above all, the interconnector 120 may be protected from external impact.

(25) The metal-core solder ball may have a globular shape, an egg shape, or a cubic shape. When the interconnector 120 is formed in a ball type, the interconnector 120 may be generally freely controlled, and adhesion of the redistribution layer RDL with the interconnector 120 may be increased during an RDL process. Particularly, since the redistribution layer RDL is formed using surface mount technology (SMT), processing costs are greatly reduced, and yield greatly increases.

(26) The solder buffer 120b may include a multilayered structure of a conductive layer which is disposed inside thereof and formed of solder or nickel and a nonconductive layer which is disposed outside the conductive layer and formed of a material having a higher ductility than the conductive layer.

(27) Referring to FIG. 6, according to another aspect of the present invention, when the interconnector 120 is formed using the conductive ball, a size of the conductive ball may be easily changed according to conditions of each package because the conductive ball may be manufactured in various sizes by adjusting a diameter of the conductive ball.

(28) For example, widths of packages tend to be gradually reduced due to a reduction in the design rule of semiconductor devices. When the overall width of a package is reduced, upper and lower sizes of an interconnector configured to connect upper and lower packages are meant to be reduced. The conductive ball of the present invention may actively adjust to size changes.

(29) Although the size of the conductive ball may be freely changed, it is difficult to change a shape of the conductive ball. When the conductive ball is designed to have a small size corresponding to a fine pitch, the upper and lower packages may not wholly be connected to each other due to a limitation in shape change. For example, when a thickness of the package is reduced to correspond to the width of the package, durability of the package weakens. Thus, even in a case where the width of the package is reduced, a height of the package needs to be maintained. In this case, the height of the package may be maintained by variously designing a height of the sacrificial pad Mp.

(30) For example, when the size of the conductive ball is reduced, the sacrificial pad Mp may be designed to have a relatively large height. The sacrificial pad Mp may be freely designed using an RDL process. When the sacrificial pad Mp is designed to stand high as described above, a partial height of some pads or the conductive ball may be supplemented even when the grinding process is performed.

(31) In particular, an under-bump metallurgy (UBM) layer having an adhesion function or a protection function may be further formed on the sacrificial pad Mp and provide a reliable electrical and mechanical interface between the pad and the conductive ball.

(32) Referring to FIG. 7, a heat dissipation pad 112 may be further provided on a top surface of the semiconductor substrate 110. In another embodiment of the present invention, when the above-described sacrificial pad Mp is formed using an RDL process, the heat dissipation pad 112 may be also patterned. The heat dissipation pad 112 may be formed of the same material as the sacrificial pad Mp and have high thermal conductivity. Heat generated by the semiconductor chip 110 may be effectively dissipated by the heat dissipation pad 112.

(33) The heat dissipation pad 112 may have a thickness greater than or equal to that of the sacrificial pad Mp. Particularly, according to the semiconductor C2FO-WLP of the present invention, the heat dissipation pad 112 is exposed by performing a thin-film process of partially removing a back side of the package using a grinding process to reduce a thickness of the package.

(34) According to the embodiment of the present invention, the thickness of the semiconductor package is reduced using the above-described grinding process. When the heat dissipation pad 112 is not additionally provided, since the semiconductor chip 110 is directly exposed to the outside and not coated with an additional molding member, a normal warpage phenomenon is greatly reduced.

(35) That is, since a back-side portion of the semiconductor chip 110 is directly exposed to the outside and dissipates heat while the molding member is not provided on the exposed portion of the semiconductor chip 110, a double effect of suppressing a warpage phenomenon due to a CTE difference may be expected.

(36) Referring to FIG. 8, a redistribution layer RDL may be formed on the sacrificial substrate M using an RDL process, and various patterning processes for adjusting a height of the sacrificial pad Mp may be performed along with a process of patterning the heat dissipation pad 112. Thus, a thickness of the entire package may be reduced, and the patterning process may be greatly shortened.

(37) Accordingly, a C2FO-WLP 100 according to another embodiment of the present invention may include a redistribution layer RDL, a semiconductor chip 110 having a first surface (or bottom surface) electrically connected to the redistribution layer RDL through stud contacts or bumps 102, a protective member 130 configured to protect side surfaces of the semiconductor chip 110, a heat dissipation pad 112 adhered to a second surface (or top surface) of the semiconductor chip 110, sacrificial pads Mp configured to be substantially coplanar with the heat dissipation pad 112, and interconnectors disposed outside the semiconductor chip 110. A lower portion of the interconnector may be connected to the redistribution layer RDL, and an upper portion of the interconnector may be connected to the sacrificial pad Mp.

(38) Although the heat dissipation pad 112 is formed of the same material using the same process as that of the sacrificial pad Mp, the heat dissipation pad 112 may be formed to a thickness greater than or equal to a thickness of the sacrificial pad Mp.

(39) Referring to FIG. 9, a fan-out POP package 200 of the present invention is a package-on-package (PoP) type in which one-side package is stacked on another-side package. The PoP package 200 includes a fan-out lower package 100a, a fan-out upper package 100b, and upper/lower interconnectors 120 provided outside the lower package 100a and configured to connect a pair of packages 100a and 100b.

(40) The present invention is characterized in that an interconnector 120 is not formed using a via process. The interconnector 120 of the present invention may be formed using a metal-core solder ball process.

(41) The lower package 100a includes a redistribution layer RDL, a lower semiconductor chip 110a adhered to the redistribution layer RDL on the redistribution layer RDL through stud contacts or bumps 102, a lower protective member 130a configured to protect the lower semiconductor chip 110a, and a lower connection member 140a.

(42) The upper package 100b may include an upper substrate F, at least one upper semiconductor chip 110b wire-bonded to the upper connection member 140b, and an upper protective member 130b configured to protect the upper semiconductor chip 110b. The upper connection member 140b may be directly connected to the interconnector 120.

(43) The lower semiconductor chip 100a may include a logic semiconductor, and the upper semiconductor chip 100b may include a memory semiconductor.

(44) As described above, the interconnector 120 for connecting upper and lower packages according to the present invention is formed during a process for the lower package 100a.

(45) Meanwhile, the lower semiconductor chip 110a may be electrically connected to the redistribution layer RDL by the stud contacts or bumps 102. The stud contact or bump 102 may be formed using a stud bump process, a copper (Cu) (or another metal) filter process, or a solder ball process.

(46) Hereinafter, a method of manufacturing a fan-out PoP according to the present invention will be described with reference to the accompanying drawings.

(47) A process of manufacturing a semiconductor chip will be described with reference to FIGS. 12 and 10A to 10D:

(48) Preparing a semiconductor substrate (S10);

(49) Referring to FIG. 10A, a semiconductor substrate S is provided. In this case, the semiconductor substrate S includes a strip-type wafer. A semiconductor pad Sp (or a wafer pad) is formed on one surface of the semiconductor substrate S (or referred to as a wafer). The pad Sp may be formed using an RDL process.

(50) Laminating an adhesive tape on one surface of the semiconductor substrate (S12);

(51) Referring to FIG. 10B, the semiconductor substrate S is coated with a die-attached film (DAF) or another adhesive tape by a predetermined thickness and laminated on one surface thereof.

(52) Bonding a contact metal to a semiconductor pad (S14);

(53) Referring to FIG. 10C, a contact metal Sc is formed on the semiconductor pad Sp using a metal stud bump bonding process or a solder ball process. The contact metal Sc undergoes an exposure process described below to form stud contacts or bumps 102.

(54) Separating the semiconductor substrate into individual semiconductor chips (S16);

(55) Referring to FIG. 10D, a process of separating the semiconductor substrate S into individual semiconductor chips 110 using a singulation process may be performed. Thus, the individual semiconductor chip (refer to 110 in FIG. 4) to which the contact metal Sc is bonded is provided on the semiconductor pad Sp.

(56) A process of manufacturing a fan-out package will be described with reference to FIGS. 12 and 11A to 11G:

(57) Preparing a sacrificial substrate (S20);

(58) Referring to FIG. 11A, a sacrificial substrate M may include a mirror wafer. The sacrificial substrate M is provided and a sacrificial pad Mp is formed on one surface of the sacrificial substrate M. The sacrificial pad Mp may be formed using an RDL process. Since a package process of the present invention includes forming the semiconductor chip on the sacrificial substrate M, a warpage phenomenon caused by thermal expansion may be minimized during a high-temperature process.

(59) Meanwhile, according to the embodiment of the present invention, when the pad Mp is formed on the sacrificial substrate M, a seed may be formed on the sacrificial substrate M corresponding to the pad Mp, and the pad Mp may be formed using the seed.

(60) B bonding an interconnector metal to the sacrificial pad on the sacrificial pad (S22);

(61) Referring to FIG. 11B, an interconnector metal Mc is formed on the sacrificial pad Mp using a solder ball process or a metal post process. The interconnector metal Mc undergoes a solder ball process described below to form an upper-lower interconnector (refer to 120 in FIG. 4), which replaces a via forming process and a via filling process.

(62) Mounting an individual semiconductor chip including the contact metal provided on the semiconductor pad, in a face-up form on the sacrificial substrate including the interconnector metal provided on the sacrificial pad (S30);

(63) Referring to FIG. 11C, each semiconductor chip 110 may be fixed on the sacrificial substrate M using an adhesive tape (e.g., DAF). In this case, the semiconductor chip 110 fixed on the sacrificial substrate M by the adhesive tape (e.g., DAF) may be fixed without being moved during a molding process or a planarization process described below. Thus, a reduction in yield may be minimized during an RDL process described below.

(64) Molding a protective member on the sacrificial substrate (S32);

(65) Referring to FIG. 11D, an epoxy molding compound (EMC) is deposited on the contact metal Sc bonded to the semiconductor pad Sp and the interconnector metal Mc bonded to the sacrificial pad Mp. The EMC may be coated with a protective member 130 to cover the contact metal Sc and the interconnector metal Mc.

(66) Grinding and planarizing the protective member (S34);

(67) Referring to FIG. 11E, a planarization process is continuously performed until the contact metal Sc and the interconnector metal Mc are exposed. As a result, the contact metal Sc and the interconnector metal Mc, which are exposed using the planarization process, form the stud contacts or bumps (refer to 102 in FIG. 4) and the interconnectors (refer to 120 in FIG. 4).

(68) Redistribution for electrically connecting the bump and the interconnector to the outside (S40);

(69) Referring to FIG. 11F, as a result of a top-side RDL process, a redistribution layer RDL is formed to electrically connect another package (refer to 100b in FIG. 9) to the outside through the interconnectors 120 and electrically connect the semiconductor chip (refer to 100a in FIG. 9) to the outside through the stud contacts or bumps 102. Further, a redistribution connection member 140 is formed.

(70) Removing the sacrificial substrate from the semiconductor chip (S42);

(71) Referring to FIG. 11G, the sacrificial substrate M is ground to remove the sacrificial substrate M from the protective member 130. Portions of the sacrificial pad Mp and the heat dissipation pad 112 are removed using a grinding process. Thus, the semiconductor chip 110 and the sacrificial pad Mp are exposed and electrically connected to another package (refer to 100b in FIG. 9).

(72) In this case, when the sacrificial substrate M is removed, the sacrificial pad Mp may remain to be as thick as a thickness of the heat dissipation pad 112. However, since the thickness of the heat dissipation pad 112 is greater than a thickness of the sacrificial pad Mp, the sacrificial pad Mp may be wholly removed, and only the heat dissipation pad 112 may remain.

(73) As described above, it can be seen that the present invention provides a fan-out PoP in which interconnectors configured to connect upper and lower packages are formed using conductive balls, and a metal-core solder ball process is used without using a via forming process and a via filling process after molding the conductive ball. It will be understood by one of ordinary skill in the art that various other changes may be made within the spirit and scope of the present invention.