Method for communicating between at least one first system and at least one second system

Abstract

The invention relates to a method for communicating between at least one first system (2) and at least one second system (3) via a full-duplex synchronous serial link (4) capable of simultaneously routing data between said systems (2, 3), said data comprising: at least one message (12; 43) from the first system (2) to the second system (3), at least one message (16; 45) from the second system (3) to the first system (2), and a clock signal (13; 44). According to the method: the second system (3) receives a message (12; 43) and a clock signal (13; 44) sent by the first system (2), delayed and substantially in phase; the second system (3) sends the first system (2) a message (16; 45); the clock signal (13; 44) received by the second system (3) is returned (17; 46) to the first system (2) along with the message (16; 45) sent by the second system (3); and the first system (2) receives the message (16; 45) sent by the second system (3) and the returned clock signal (17; 46), delayed and substantially in phase.

Claims

1. An assembly, comprising: a communication system galvanically isolated between one first system and one second system, said communication system comprising: a full-duplex synchronous serial link between at least one first system and at least one second system, the link comprising: a first wire running between said systems and allowing the transmission of a message or messages from the first system to the second system; a second wire running between said systems and allowing the transmission of a message or messages from the second system to the first system, and a third wire running between said systems and allowing the transmission of a clock signal generated by the first system to the second system; and a fourth wire linking an area of the third wire and the first system, wherein the fourth wire allows the transmission of the clock signal from the second system back to the first system, and wherein the transmission of the clock signal from the second system to the first system and the transmission of the message or messages from the second system to the first system are delayed and are in phase, wherein galvanic isolation crossed by the link, said area of the third wire being arranged downstream of the isolation when the link is traveled from the first system in the direction of the second system, wherein a first slave system comprising a microcontroller or a microprocessor; and a second master system, the link including a fifth wire linking the first system and crossing the galvanic isolation, wherein the galvanic isolation comprises a first part and a second part arranged in parallel, wherein the first part of the galvanic isolation is crossed by the first, second, third, and fourth wires, and wherein the second part of the galvanic isolation is crossed by the fifth wire.

2. The assembly as claimed in claim 1, wherein the link is a link of Serial Peripheral Interface (SPI) type.

3. The assembly as claimed in claim 1, wherein the first system is master and wherein the second system is slave.

4. The assembly as claimed in claim 1, wherein the full-duplex synchronous serial link has a speed in the range of 5 Mbits/s to 20 Mbits/s.

5. The assembly as claimed in claim 1, wherein the first system comprises a first half-duplex module in charge of transmitting data over the link and a second half-duplex module in charge of receiving data routed over the link.

6. The assembly as claimed in claim 1, wherein the second system comprises a full-duplex module in charge of communicating with the master system.

7. The assembly as claimed in claim 1, wherein the first system is master and comprises a programmable logic circuit (FPGA).

8. The assembly as claimed in claim 1, wherein the first system is slave and comprises a microcontroller or a microprocessor.

9. The assembly as claimed in claim 1, wherein the data routed over the link comprise duty cycle values intended to be applied to switches of an inverter and measured current values.

10. The assembly as claimed in claim 9, wherein one of the first system and the second system interacts with a generator of duty cycle values and the other of the first system and the second system interacts with an electrical circuit comprising an inverter and an electric motor.

11. The assembly as claimed in claim 1, wherein the area of the third wire is positioned on the third wire in such a way as to send back to the first system a clock signal identical to that received by the second system.

12. The assembly as claimed in claim 1, wherein the galvanic isolation is interposed between the first system and the second system and wherein the full-duplex synchronous serial link crosses the galvanic isolation.

13. The assembly as claimed in claim 1, wherein the full-duplex synchronous serial link is configured to have a speed in the range of 15 Mbits/s to 20 Mbits/s.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be better understood upon reading the following description of non-limiting exemplary embodiments of the latter, and upon examining the appended drawing in which:

(2) FIGS. 1 and 2 represent a full-duplex synchronous serial link of the prior art already described,

(3) FIG. 3 represents an assembly according to a first embodiment of the invention,

(4) FIG. 4 illustrates a sequence of communication with the assembly in FIG. 3,

(5) FIG. 5 represents an assembly according to a second embodiment of the invention and,

(6) FIG. 6 illustrates a sequence of communication with the assembly in FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

(7) FIG. 3 represents an assembly 1 in which methods according to exemplary embodiments of the invention can be carried out.

(8) The assembly 1 comprises in the example in FIG. 3 one first system 2 and one second system 3 exchanging data by way of a full-duplex synchronous serial link 4.

(9) In the example under consideration, the assembly 1 is embedded in a vehicle that comprises an electrical circuit including an electric motor 6, a battery and an inverter interposed between the battery and the electric motor. The electrical circuit can comprise a connector making it possible to charge the battery by way of an electrical network.

(10) The assembly 1 is in the example under consideration part of a device for driving the switches of the inverter.

(11) The first system 2 is for example a peripheral interacting with the inverter to control the switches of the inverter and with the electric motor 6 to measure the current flowing through each phase of the stator of the motor 6, the latter being particularly multi-phase, for example three-phase.

(12) The first system 2 sends for example duty cycle values to the switches of the inverter and receives, after passage through an analog/digital converter 7, values of the currents measured in the phases of the stator of the motor 6.

(13) The second system 3 communicates in the example under consideration with a generator 8 of duty cycle values as a function of current values. This generator 8 employs a software process, for example.

(14) The first system 2 is master in the example in FIGS. 3 and 4 and it is produced in this example using a programmable logic circuit (FPGA). The master system 2 comprises in this example two modules associated with the link 4, each module being a half-duplex module. A first module 10 is responsible for the sending of the message 12 to the second system 3 which is slave here and for the sending of a clock signal 13 with which the message 12 is synchronized.

(15) A second module 14 is responsible for receiving the message 16 sent by the second system 3 and clock signals 17, as will be seen further on.

(16) The link 4 can be of SPI type, in which case each module 10 and 14 is a half-duplex SPI controller.

(17) The second system 3 comprises in the example under consideration a single module 18 associated with the link 4. This module 18 is a full-duplex module, sending messages 16 to the first system 2 and receiving the messages 12 sent by the first system. This module also receives the clock signal 13 generated by the first system 2. When the communication is carried out over a link 4 of PSI type, the module 18 is a full-duplex SPI controller.

(18) In the example under consideration, the link 4 allows the sending by the first system 2 of current values to the second system 3 and the sending by the second system 3 of duty cycle values generated on the basis of these current values by the generator 8.

(19) The link 4 is in the example in FIG. 3 composed of four wires 30 to 33. The wire 30 is responsible for the routing of the messages 12 from the first system 2 to the second system 3. The wire 31 is responsible for the routing of the clock signal generated by the first system 2 to the second system 3. The wire 32 is responsible for the routing of the messages 16 from the second system 3 to the first system 2. A fourth wire 33 is provided, this wire 33 linking an area 35 of the wire 31 and the first system 2. The fourth wire 33 plays the part of return for the wire 31.

(20) In the example in FIG. 3, the first system 2 is galvanically isolated with respect to the second system 3. This galvanic isolation 22 is here produced by way of a transformer but the invention is not limited to a particular production of the galvanic isolation. The galvanic isolation 22 is in this example a multi-channel isolation, each wire 30 to 33 being received in a specific channel of the isolation 22.

(21) As represented in FIG. 3, the area 35 of the wire 31 from which the fourth wire 33 runs can be situated downstream of the isolation 22 when the link 4 is traveled from the first system 2 in the direction of the second system 3. This area 35 is for example situated as close as possible to the second system 3, in such a way as to send back to the first system 2 a clock signal substantially identical to that received by the second system 3.

(22) The sequence of communication illustrated in FIG. 4 with the assembly in FIG. 3 will now be described.

(23) A message 12 is sent by the first system 2 which is master here via its module 10 to the second system 3 which is slave here. This message 12 is synchronized with a clock signal 13. The crossing of the galvanic isolation 22 generates a delay d which is substantially the same for the message 12 and the clock signal 13. In the examples described, one and the same delay d is applied by the link 4 to the data that it routes, independently of the direction of routing. In variants, not represented, one and the same delay d1 is applied by the link 4 to the data routed from the first system 2 to the second system 3, i.e. to the message 12 and to the clock signal 13, whereas a second delay d2, different to the first delay d1, is applied to the data routed from the second system 3 to the first system 2, i.e. to the message 16 and to the clock signal 17. This difference can be due to the use of different insulators from one direction of routing to the other.

(24) The message 12 and the clock signal 13 then arrive in phase at the second system 3. The module 18 then reads the message 12 with respect to the clock signal 13.

(25) A message 16 is sent back by the second system 3 to the first system 2. Owing to the presence of the fourth wire 33 in the link 4, a clock signal 17, which actually corresponds in the example under consideration to the clock signal 13 received by the module 18, is sent to the first system 2. This clock signal 17 is in phase with the message 16 sent by the second system 3. The crossing of the galvanic isolation 22 induces on the message 16 and the clock signal 17 a delay d that is substantially equal for these two data, and which is also in the example under consideration substantially equal to the delay induced by the galvanic isolation 22 during the routing from the first system 2 to the second system 3 of the message 12 and of the clock signal 13.

(26) The clock signal 17 and the message 16 then arrive in phase at the first system 2. The module 14 then proceeds with the reading of the message 16 with respect to the clock signal 17.

(27) As can be seen in FIG. 4, the clock signal 17 is, in the example described, delayed by twice the delay induced by the link 4 when it is received by the module with respect to the clock signal 13 initially transmitted by the module 10 but this delay does not disturb the reading of the message 16 by the module 14.

(28) We will now describe, with reference to the FIGS. 5 and 6, an assembly 1 according to a second embodiment of the invention.

(29) This assembly 1 differs from that represented in FIG. 3 by the fact that the first system 2 generating the clock signal is slave whereas the second system 3 is master. Furthermore, the first system 2 interacts with the generator 8 of duty cycle values whereas the second system 3 interacts with the electric motor 6 and with the analog-to-digital converter 7.

(30) The first system 2 comprises in this example a microcontroller including two half-duplex modules 40 and 41, the first half-duplex module 40 being in charge of sending messages 43 and a clock signal 44 to the second system 3 whereas the second half-duplex module 41 is in charge of receiving messages 45 sent by the second slave system and a clock signal 46.

(31) The second system 3 comprises in the example in FIG. 5 an FPGA including a single full-duplex module 48 in charge of communicating over the link 4.

(32) As represented in FIG. 5, each system 2 or 3 comprises in this example a synchronization module 50. Still in this example, the link comprises a fifth wire 51 and the galvanic isolation is in two parts, a first multi-channel part 52 is similar to the isolation 22 in FIG. 3 and crossed by the wires 30 to 33 whereas a second isolation 53 is dedicated to the isolation of the fifth wire 51. This fifth wire 51 and the modules 50 allow the second system 3, which is master here, to clock the communication.

(33) As represented in FIG. 6, similarly to that which has been described with reference to FIG. 4, the first system 2 sends a message 43 and a clock signal 44 that are received by the second system 3 in phase and delayed by a substantially equal delay d. The second system 3 sends back a message 45 that is accompanied by a clock signal 46 generated using the return formed by the fourth wire 33. The first system 2 then receives via its second module 41 the message 45 and the clock signal 46 once again delayed by one and the same delay, here equal to the delay d, and can read the message 45 with respect to the clock signal 46.

(34) The invention is not limited to the examples that have just been described.

(35) In particular, as mentioned above, the invention does not necessarily imply that the link applies to the data routed from the first system to the second system a delay equal to that which the link applies to the data routed from the second system to the first system.

(36) The expression including a or comprising a must be understood to mean including at least one or comprising at least one except when the opposite is specified.