Array substrate, method for manufacturing array substrate, and display device

Abstract

Disclosed is an array substrate, a method for manufacturing the array substrate, and a display device. The array substrate includes: a plurality of pixel units arranged in an array, each pixel unit being provided with one thin film transistor including an active layer and a polymer film on array. The polymer film on array is formed with a first via hole, and the active layer is conductive in a region thereof corresponding to the first via hole, such that a pixel electrode located on the polymer film on array is electrically connected to the source through the first via hole.

Claims

1. A method for manufacturing an array substrate, comprising the steps of: forming a drain and a source on a same layer through one and a same patterning procedure; forming an active layer partially covering an upper surface of the drain and an upper surface of the source on the same layer of the drain and the source; forming a polymer film on array covering the active layer, and forming a first via hole on the polymer film on array to expose the active layer partially; treating a region of the active layer corresponding to the first via hole, such that the region of the active layer is conductive; and forming a pixel electrode directly disposed on the polymer film on array, which is electrically connected to the source through the region of the active layer corresponding to the first via hole.

2. The method of according to claim 1, wherein the step of treating a region of the active layer corresponding to the first via hole, such that the region of the active layer is conductive includes: enabling the region of the active layer corresponding to the first via hole to be an n-type heavily doped region by treatment with plasma, such that the region of the active layer is conductive.

3. The method according to claim 2, wherein the plasma is hydrogen ions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to explicitly illustrate the technical solution of the embodiments of the present disclosure, the embodiments will be described in combination with accompanying drawings, in which:

(2) FIG. 1 schematically shows the structure of an array substrate in the prior art;

(3) FIG. 2 schematically shows the structure of an array substrate according to an embodiment of the present disclosure;

(4) FIG. 3 schematically shows a flow chart of a method for manufacturing the array substrate according to the embodiment of the present disclosure; and

(5) FIGS. 4 to 7 schematically show manufacturing procedures of the array substrate of FIG. 2.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(6) The present disclosure will be explained by reference to the following detailed description of embodiments taken in connection with the accompanying drawings, whereby it can be readily understood how to solve the technical problem by the technical means according to the present disclosure and achieve the technical effects thereof, and thus the technical solution according to the present disclosure can be implemented. It is important to note that as long as there is no conflict, combinations of the above-described embodiments and of technical features therein are possible, and technical solutions obtained therefrom are intended to be within the scope of the present disclosure.

(7) In an embodiment of the present disclosure, an array substrate is provided, including a plurality of pixel units arranged in an array, each pixel unit being provided with one thin film transistor.

(8) As shown in FIG. 2, the thin film transistor includes, from the bottom up, a gate 1, a gate insulation layer 2, a drain 4 and a source 5 located in a same layer, and an active layer 3 connecting and partially covering the drain 4 and the source 5. Obviously, the thin film transistor is a bottom gate thin film transistor.

(9) Further, on the thin film transistor, the array substrate includes an insulation layer 14 covering the active layer 3, a polymer film on array 9 located on the insulation layer 14, and a pixel electrode 6 located on the polymer film on array 9, wherein the polymer film on array 9 is formed with a first via hole 15, and the insulation layer 14 is formed with a second via hole 16. The first via hole 15 is nested into the second via hole 16. The active layer 3 is electrically conductive in a region thereof corresponding to the first via hole 15, such that the pixel electrode 6 located on the polymer film on array 9 can be electrically connected to the source 5 through the first via hole 15.

(10) Specifically, plasma treatment can be performed, and the region of the active layer 3 corresponding to the first via hole 15 can be bombarded with positively charged ions such as hydrogen ions and phosphorus ions, so as to enable the region to be an n-type heavily doped region 17. This can enhance conductivity of this region, so that the pixel electrode 6 can be brought into contact with the active layer 3 through the first via hole 15, i.e., the purpose of electrically connecting the pixel electrode 6 to the source 5 located under the active layer 3 can be achieved.

(11) Moreover, the active layer 3 separates the polymer film on array 9 from the source 5, thus preventing generation of a nonconductive substance upon contact of the polymer film on array 9 to the source 5. And the material of the active layer 3 determines that it cannot react with the polymer film on array 9. Thus, the pixel electrode 6 can realize an effective electrical connection to the source 5, and the yield of the display device is thereby ensured.

(12) Specifically, in the embodiment of the present disclosure, the active layer 3 can be made of a material such as amorphous silicon and low-temperature polysilicon. However, in order to improve doping efficiency of the active layer 3, the active layer 3 can be made of oxide semiconductor, wherein the active layer 3 can preferably be made of indium gallium zinc oxide (IGZO).

(13) IGZO is an amorphous oxide containing indium, gallium, and zinc. With a carrier mobility 20 to 30 times that of amorphous silicon, IGZO can greatly improve charging and discharging rates of a TFT to the pixel electrode 6, and improve response speed of a pixel, so as to achieve a greater refresh rate. Meanwhile, faster response also significantly improves row scan rate of the pixel, thus rendering ultra-high resolution possible in the display device.

(14) In order to manufacture the above-described array substrate, in an embodiment of the present disclosure, a method for manufacturing the above-described array substrate is further provided, as shown in FIG. 3. The method comprises the following steps.

(15) In step S101, a drain and a source are formed on a same layer through one and a same patterning procedure.

(16) In step S102, an active layer partially covering the drain and the source is formed on the drain and the source.

(17) In step S103, a polymer film on array provided with a first via hole is formed, to expose the active layer partially.

(18) In step S104, a region of the active layer corresponding to the first via hole is treated, such that the region of the active layer is conductive.

(19) In step S105, a pixel electrode is formed, the pixel electrode being electrically connectable to the source through the region of the active layer corresponding to the first via hole.

(20) The array substrate provided in the embodiment of the present disclosure can be obtained specifically by the following manufacturing steps.

(21) A first metal layer for manufacturing the structures of the gate 1, a gate line, and the like is formed on a base 18 by physical vapor deposition (PVD), followed by exposure through a corresponding mask plate, and procedures such as development, wet etching, and stripping to form the gate 1.

(22) The base 18 may be a base substrate or a buffer layer disposed on the base substrate. The buffer layer can provide an ideal isolation buffer between the gate 1 and the base substrate, and can enhance adhesion between the gate 1 and the base.

(23) Subsequently, the gate insulation layer 2 for insulating the gate 1, and the drain 4 and the source 5 is formed on the gate 1 by coating or the like. The gate insulation layer 2 may be made of an insulating material such as silicon nitride (Si.sub.xN.sub.y) or silicon oxide (Si.sub.xO.sub.y). After the formation of the gate insulation layer 2, a second metal layer is formed on the gate insulation layer 2 through a PVD procedure again. The second metal layer is used for forming the structures such as the drain 4 and the source 5 that are provided on the same layer, and a data line. The second metal layer is exposed through a corresponding mask plate, followed by procedures such development, wet etching, and stripping to manufacture the structures such as the drain 4, the source 5, and the data line.

(24) After the drain 4 and the source 5 are manufactured, the active layer 3 is manufactured to obtain the array substrate as shown in FIG. 4. An IGZO layer is formed on the drain 4 and the source 5 through PVD, followed by exposure through a corresponding mask plate, and procedures such as development, wet etching, and stripping, to obtain a pattern of the active layer 3, wherein the active layer 3 has a thickness in the range from 40 to 100 nm, and has a large contact area with the drain 4 and the source 5 to cover a majority of the drain 4 and the source 5. With this structure, not only effective contact between the active layer 3 and the drain 4 and the source 5 can be ensured, but also the source 5 can be protected from coming in contact with the polymer film on array 9.

(25) Afterwards, the insulation layer 14 is formed on the active layer 3 by plasma enhanced chemical vapor deposition (PECVD), and the insulation layer 14 can also be made of a conventional insulating material such as silicon nitride and silicon oxide. Since the insulation layer 14 is insulative and cannot be electrically conductive, in order to allow the pixel electrode 6 to be electrically conductive with the source 5, it is necessary to form the second via hole 16 by procedures such as exposure, development, and dry etching performed on the insulation layer 14 through a corresponding mask plate, as shown in FIG. 5.

(26) Since the active layer 3 in this embodiment covers the majority of the source 5, the second via hole 16 cannot expose the source 5, but exposes the active layer 3 covering the source 5.

(27) After the second via hole 16 is formed, the polymer film on array 9 is formed on the insulation layer 14 by a coating procedure or the like. In this embodiment, the polymer film on array 9 is formed on the insulation layer 14 in order to increase an aperture ratio of the display device. Due to the existence of the polymer film on array 9, the pixel electrode 6 may extend on a portion of the data line, thereby increasing the aperture ratio of the display device. This is because the polymer film on array 9 has a sufficient thickness to prevent an excessive parasitic capacitance between the pixel electrode 6 and the data line, which would otherwise deteriorate the display effect of the display device.

(28) Although the second via hole 16 is formed in the insulation layer 14, since the second via hole 16 exposes the active layer 3 covering the source 5, the polymer film on array 9 cannot be in contact with the source 5 through the second via hole 16 to react with the source 5 and form a nonconductive substance. In addition, since the polymer film on array 9 does not react with the active layer 3 made of IGZO, the polymer film on array 9 will not affect characteristics of the active layer 3.

(29) Since the polymer film on array 9 is electrically nonconductive, and the pixel electrode 6 is provided on the polymer film on array 9, in order for the pixel electrode 6 to be electrically connected to the source 5, it is necessary to provide the polymer film on array 9 with the first via hole 15, which is nested in the second via hole 16, to merely expose a portion of the active layer 3 also, as shown in FIG. 6.

(30) Obviously, if the active layer 3 is not specifically treated, since the active layer 3 is not made of a conductive material, the pixel electrode 6 in direct contact with the active layer 3 still cannot be electrically connected to the source 5 in an effective manner. Therefore, in the embodiment of the present disclosure, the exposed portion of the active layer 3 is subjected to treatment of hydrogen ion bombardment based on the first via hole 15 provided in the polymer film on array 9, so that this portion becomes the n-type heavily doped region 17, as shown in FIG. 7. The conductivity of this portion of the active layer 3 can be thereby improved. Thus, after the pixel electrode 6 comes into contact with the active layer 3 through the first via hole 15, good electrical connection between the pixel electrode 6 and the source 5 can be achieved through the conductive n-type heavily doped region 17.

(31) Finally, on the polymer film on array 9, an indium tin oxide (ITO) layer for preparing the pixel electrode 6 is formed by the PVD procedure again. Subsequently, the pattern of the pixel electrode 6 is obtained by exposure through a corresponding mask plate, and procedures such as development, wet etching, and stripping, so as to obtain the array substrate as shown in FIG. 2.

(32) To conclude the above, in the embodiment of the present disclosure, the array substrate is provided, comprising the plurality of pixel units arranged in an array, the active layer in the pixel unit partially covering the source and the drain, to prevent the polymer film on array from coming in contact with the source. At the same time, the polymer film on array is formed with the first via hole, and the active layer is electrically conductive in the region thereof corresponding to the first via hole, thereby ensuring the electrical connection between the pixel electrode and the source. This is favorable for improvement of the yield of the array substrate.

(33) In the embodiment of the present disclosure, the display device is further provided, including the above-described array substrate. The display device can be a television, a display, a mobile phone, a tablet computer, or the like.

(34) The above embodiments are described only for better understanding, rather than restricting, the present disclosure. Any person skilled in the art can make amendments to the implementing forms or details without departing from the spirit and scope of the present disclosure. The scope of the present disclosure should still be subject to the scope defined in the claims.