Array substrate and manufacturing method thereof

Abstract

The present disclosure discloses an array substrate and manufacturing method thereof. The method includes: forming a gate layer on the surface of a substrate; forming an insulating layer on the surface of the gate layer; forming a polysilicon layer having a separating portion on the surface of the insulating layer; and forming a source drain layer on the surface the polysilicon layer having the separating portion, such that the source drain layer is not directly in contact with the polysilicon layer. Through the above-mentioned method, the contact resistance of the source drain layer and the amorphous silicon layer is effectively improved, thereby effectively reducing the leakage current, and the characteristic of TFT device is greatly improved.

Claims

1. An array substrate, comprising: a gate layer, an insulating layer, a polysilicon layer, and a source drain layer successively formed on a substrate; wherein the polysilicon layer comprises a separating portion separating the source drain layer and the polysilicon layer, and the electron mobility of the separating portion is lesser than the electron mobility of the polysilicon layer; wherein the insulating layer is etched with a recess, the separating portion is a sidewall of the recess on the insulating layer.

2. The array substrate of claim 1, wherein the separating portion is formed of an amorphous silicon material.

3. The array substrate of claim 1, wherein the polysilicon layer is formed by performing crystallizing on the amorphous silicon layer at 650 C. through rapid thermal annealing.

4. The array substrate of claim 1, wherein the gate layer is formed by etching a metal layer formed through vapor deposition.

5. The array substrate of claim 1, wherein the insulating layer is formed through physical or chemical deposition.

6. The array substrate of claim 1, wherein the source electrode and the drain electrode in the source drain layer are separated by a channel, the channel is formed by etching after depositing and patterning a source drain layer on a polysilicon layer having a separating portion.

7. The array substrate of claim 6, wherein a passivation layer is deposited on the surfaces of the source electrode and the drain electrode.

8. The array substrate of claim 1, further comprising: a buffer layer, formed between a substrate and a gate layer, the buffer layer is a light shielding layer or an ion blocking layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of the structure of an array substrate of the prior art.

(2) FIG. 2 is a flow chart of an embodiment of a manufacturing method for an array substrate of the present disclosure.

(3) FIG. 3 is a structural flow chart of a manufacturing method for an array substrate according to one embodiment of the present disclosure.

(4) FIG. 4 is a structural flow chart of a manufacturing method for an array substrate according to one embodiment of the present disclosure.

(5) FIG. 5 is a structural flow chart of a manufacturing method for an array substrate according to one embodiment of the present disclosure.

(6) FIG. 6 is a structural flow chart of another manufacturing method for an array substrate according to one embodiment of the present disclosure.

(7) FIG. 7 is a structural flow chart of another manufacturing method for an array substrate according to one embodiment of the present disclosure.

(8) FIG. 8 is a structural flow chart of another manufacturing method for an array substrate according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

(9) Referring to FIG. 2, a flow chart of an embodiment of a manufacturing method for an array substrate of the present disclosure is depicted. The method may include the following blocks.

(10) At 201: forming a gate layer on the surface of a substrate.

(11) Specifically, the substrate is placed in a deposition chamber, a metal layer is formed by vapor deposition, and the metal layer is patterned to form a gate layer. In which, a buffer layer is deposited on the substrate before forming the metal layer, and the buffer layer may be provided with a light shielding layer and an ion blocking layer according to the use of the array substrate, which is not repeated herein.

(12) The substrate may be made of at least one kind of glass and quartz. In other embodiments, it may be made of other kinds of transparent material, which is not limited herein.

(13) At 202: forming an insulating layer on the surface of the gate layer.

(14) In which, the gate insulating layer is formed by physical or chemical vapor deposition. In which, the gate insulating layer includes at least one kinds of silicon nitride SiNx and amorphous silicon oxide SiOx.

(15) At 203: forming a polysilicon layer having a separating portion on the surface of the insulating layer.

(16) Specifically, an amorphous silicon layer is formed on the insulating layer by patterning, a photoresist is provided on the patterned amorphous silicon layer, implantes boron ion in the amorphous silicon layer, and the photoresist is removed after photomasking, in which the width of the opening of the photoresist is smaller than the width of the amorphous silicon layer.

(17) Optionally, a recess is defined in a predetermined region in the middle of the insulating layer, the amorphous silicon layer is deposited on the insulating layer, and the amorphous silicon layer in the groove is retained; a polysilicon conductor layer is formed in the groove by depositing, and the boron ion is implanted into the polysilicon conductor layer performs crystallization on the amorphous silicon layer.

(18) In an optional embodiment, rapid thermal annealing technique can be adopted to crystallize on the amorphous silicon layer.

(19) In a specific embodiment, the amorphous silicon layer may crystallize at the temperature of 650 C. In other embodiments, the amorphous silicon layer may crystallize at other temperatures such as 700 C. and 640 C., as long as the crystallization of the amorphous silicon layer can be achieved in accordance with the standard, which is not limited herein. The baking time can be 15 minutes, 14 minutes, or 16 minutes are also permitted, which is not limited herein.

(20) In another embodiment, the dopant ion, i.e., boron ion and phosphorus ion, can be diffused through excimer laser annealing, so as to form the polysilicon layer, which is not limited herein.

(21) At 204: forming a source drain layer on the surface of the polysilicon conductor layer having the separating portion, such that the source drain layer is not directly in contact with the polysilicon layer.

(22) In which, the source drain layer is deposited and patterned, and is etched to form a channel on the source drain layer, in which the source electrode and the drain electrode (in the source drain layer) are separated by the channel; and a passivation layer is deposited on the surfaces of the source electrode and the drain electrode.

(23) Specifically, a source electrode and a drain electrode separated by a channel are formed on the polysilicon conductor layer, and an insulating passivation layer is deposited on the surface of a thin film transistor after the gate electrode, the source electrode and the drain electrode are formed.

(24) The present disclosure will now be further described with reference to the accompanying drawings.

(25) As shown in FIGS. 3-5, the manufacturing process of an array substrate according to an embodiment of the present embodiment is as follows.

(26) As shown in FIG. 3, a substrate 1 is placed in a deposition chamber, and a buffer layer 2 is formed on the substrate 1 utilizing plasma enhanced chemical vapor deposition (PECVD), in which the buffer layer 2 includes a shading layer and an ion blocking layer (not shown) after lithography; and then PECVD is utilized again to form a gate layer 3 on the buffer layer 2 through deposition and patterning, and then an insulating layer 4 is formed on the gate layer 3 through deposition and patterning, an amorphous silicon layer 5 is provided on the patterned insulating layer 4 and patterned, and a layer of photoresist 6 is provided on two sides of the patterned amorphous silicon layer 5 and patterned (as shown in FIG. 4), such that the width of the amorphous silicon layer 5 is larger than the width of the opening of the photoresist 6 on the two sides.

(27) As shown in FIG. 4, a certain dose of boron ion is further implanted through ion implantation technique, in which the carrier of the boron ion may be a mixed gas of B.sub.2H.sub.6 and H.sub.2. The photoresists are removed after photomasking, and the solid phase crystallization process is performed on the amorphous silicon layer 5 through rapid thermal annealing. The rapid thermal annealing is utilized to crystallize on the amorphous silicon layer at 650 C., the crystallization is performed from the upper surface to the lower portion, the upper surface of the amorphous silicon layer 5 will form a polysilicon conductor layer 8 of a small impedance, and the lower portion of the polysilicon conductor layer 8 will form a semiconductor-like polysilicon layer 7. Since the width of the amorphous silicon layer 5 is larger than the width of the opening of the photoresists 6 on the two sides, and the film of the photoresists 6 blocks the implantation of the ion on the two sides so that the two sides of the amorphous silicon layer 5 are not adulterated with boron ion and retain the state of amorphous silicon on the two sides to form an amorphous silicon separating portions 9.

(28) As shown in FIG. 5, an source electrode and an drain electrode (SD electrode) are deposited and patterned to form a source drain layer 11, and the polysilicon conductor layer 8 is etched with the SD electrode as a bunker so as to etch away the polysilicon conductor layer 8 on the upper surface of a channel 10 and the semiconductor-like polysilicon layer 7 on the lower portion of the channel 10 is retained, and then a passivation layer 12 is formed by patterning to cover the channel 10, and finally the manufacture of the array substrate is completed after verification is passed.

(29) Different from the prior art, this embodiment replaces the conventional excimer laser annealing crystallization by adopting the solid phase crystallization in the process of crystallization, which greatly reduces the temperature and the time required for the crystallization, and effectively reduces the production cost. In addition, in this embodiment, the direct contact of the source drain layer and the polysilicon layer in the conventional structure is changed, and the amorphous silicon is utilized to contact the source drain layer so that the contact resistance is greatly improved, thereby achieving the objective of greatly reducing the electrical leakage, and the characteristic of TFT devices is greatly improved.

(30) As shown in FIGS. 6-8, the manufacturing process of an array substrate according to another embodiment of the present embodiment is as follows.

(31) As shown in FIG. 6, a substrate 14 is placed in a deposition chamber, and a buffer layer 15 is formed on a substrate 14 utilizing PECVD, in which the buffer layer 15 includes a shading layer and an ion blocking layer (not shown) after lithography; and then PECVD is utilized again to form a gate layer 16 on the buffer layer 15 through deposition and patterning; an insulating layer 17 is formed on the gate layer 16 through deposition and patterning, a recess 18 (as shown in FIG. 6) is defined in a predetermined region of an insulating layer 17 (generally, the middle portion of the insulating layer 17).

(32) As shown in FIG. 7, an amorphous silicon layer (not shown) is formed in the recess 18, a polysilicon conductor layer 20 (see FIG. 7) is formed on the amorphous silicon layer, and solid phase crystallization is performed on the amorphous silicon layer after adding an appropriate amount of B.sub.2H.sub.6. When baked at 650 C. for about 15 minutes, the crystallization proceeds from the upper surface to the lower portion, and the polysilicon conductor layer 20 on the upper surface of the amorphous silicon layer does not change, and the lower portion of the polysilicon conductor layer 20 will form a semiconductor-like polysilicon layer 19.

(33) As shown in FIG. 8, an SD electrode (source electrode and drain electrode) is deposited and patterned to form a source drain layer 21, and etches the polysilicon conductor layer 20 with the SD electrode as a bunker so as to etch away the polysilicon conductor layer 20 on the surface of a channel 23 (see FIG. 8) and the semiconductor-like polysilicon layer 19 on the lower portion of the channel 23 is retained, and then a passivation layer 22 is formed by patterning to cover the channel 23, and finally the manufacture of the array substrate is completed after verification is passed.

(34) Different from the above-mentioned embodiment, the separating portion of this embodiment adopts the side wall of the recess on the insulating layer to replace the separating portion formed of an amorphous silicon material, which further improves the contact resistance, thereby achieving the objective of greatly reducing the electrical leakage, and the characteristic of TFT device is greatly improved. In addition, in contrast to the above-mentioned embodiment, this embodiment omits the process of disposing and removing the photoresist, which further reduces the production cost and improves the production efficiency.

(35) The present disclosure also provides an array substrate including a gate layer, an insulating layer, a polysilicon layer, and a source drain layer are successively formed on a substrate, in which the polysilicon layer includes a separating portion, the separating portion separated the source drain layer from the polysilicon layer and the electron mobility of the separating portion is lesser than the electron mobility of the polysilicon layer.

(36) In which, a buffer layer is provided on a substrate, the buffer layer includes a shading layer and an ion blocking layer after lithography, a gate layer is provided on the buffer layer, and an insulating layer is provided on the gate layer, a polysilicon layer and a source drain layer are provided on the insulating layer; separation portions are provided on two sides of the polysilicon layer, thereby achieving the objective of greatly reducing the electrical leakage.

(37) Specifically, an array substrate manufacturing method includes: forming a gate layer on the surface of a substrate; forming an insulating layer on the surface of the gate layer, forming a polysilicon layer having a separating portion on the surface of insulating layer; and forming a source drain layer on the surface of the polysilicon layer having the separating portion, such that the source drain layer is not directly in contact with the polysilicon layer.

(38) In a specific embodiment, as shown in FIGS. 3-5, which includes a substrate 1, a buffer layer 2, a gate layer 3, an insulating layer 4, an amorphous silicon layer 5, a photoresist 6, a polysilicon layer 7, a polysilicon conductor layer 8, an amorphous silicon separating portion 9, a channel 10, a source drain layer 11, and a passivation layer 12; in which the buffer layer 2 may be adjusted to a plurality of layers according to a specific array substrate specification; in which the polysilicon layer 7 includes a separating portion 9, the separating portion 9 separates the source drain layer 11 and the polysilicon layer 7, and the electron mobility of the separating portion 9 is lesser than the electron mobility of the polysilicon layer 7.

(39) In which, the separating portion is formed of an amorphous silicon material.

(40) Specifically, the material of the amorphous silicon separating portion is an amorphous silicon material, which is generally two magnitudes different from the polysilicon. Therefore, in comparison with directly contacting with the polysilicon, the resistance can be greatly improved when the source drain layer contacts the amorphous silicon layer, thereby achieving the objective of greatly reducing the electrical leakage.

(41) In another specific embodiment, as shown in FIGS. 6-8, which includes a substrate 14, a buffer layer 15, a gate layer 16, an insulating layer 17, a recess 18, a polysilicon layer 19, a polysilicon conductor layer 20, a source drain layer 21, and a passivation layer 22; in which the buffer layer 15 may be adjusted to a plurality of layers according to a specific array substrate specification; in which the polysilicon layer 19 includes a separating portion 23 (not shown), the separating portion 23 separates the source drain layer 21 and the polysilicon layer 19, and the electron mobility of the separating portion 23 is lesser than the electron mobility of the polysilicon layer 19; the separating portion is the side wall of the recess 18 on the insulating layer 17.

(42) In which, the separating portion adopts the side wall of the recess on the insulating layer to replace the separating portion formed of an amorphous silicon material, which further improves the contact resistance, thereby achieving the objective of greatly reducing the electrical leakage, and the characteristic of TFT device is greatly improved.

(43) Different from the prior art, this embodiment can greatly improve the contact resistance by changing the direct contact of the source drain layer and the polysilicon layer in the conventional structure, and utilizing the separating portion to separate the polysilicon layer and the source drain layer so that the contact resistance is greatly improved, thereby achieving the objective of greatly reducing the electrical leakage, and the characteristic of TFT device is greatly improved.

(44) The foregoing is merely embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure. Any equivalent structure or flow transformation made based on the specification and the accompanying drawings of the present disclosure, or any direct or indirect applications of the disclosure on other related fields, shall all be covered within the protection of the present disclosure.