On-Chip Random ID Generation

Abstract

A method by which a hub unit can discover IDs from a plurality of satellite units across a shared communication link that connects each of the satellite units to the hub unit, each satellite unit having a satellite unit ID, the method comprising the hub unit broadcasting a message over the shared communication link, the message including an ID segment with a string of bits shorter than a bit length of the satellite unit IDs and an ID segment location; and each satellite unit receiving the broadcast message and comparing the ID segment with an ID portion of its own satellite unit ID starting at the ID segment location, if the ID portion for a satellite unit matches the ID segment, the satellite unit transmitting its complete satellite unit ID to the hub unit over the shared communication link.

Claims

1. A method by which a hub unit can discover IDs from a plurality of satellite units across a shared communication link that connects each of the satellite units to the hub unit, each satellite unit having a satellite unit ID, the method comprising: the hub unit broadcasting a message over the shared communication link, the message including an ID segment with a string of bits shorter than a bit length of the satellite unit IDs and an ID segment location; and each satellite unit receiving the broadcast message and comparing the ID segment with an ID portion of its own satellite unit ID starting at the ID segment location, if the ID portion for a satellite unit matches the ID segment, the satellite unit transmitting its complete satellite unit ID to the hub unit over the shared communication link.

2. A method according to claim 1, in which all of the satellite unit IDs have the same bit length.

3. A method according to claim 1, wherein the hub unit receives and stores the satellite unit IDs sent from the satellite units over the shared communication link.

4. A method according to claim 1, wherein the hub unit keeps sending broadcast messages, each time changing the ID segment and/or the ID segment location, until all of the satellite unit IDs have been discovered.

5. A method according to claim 1, wherein the broadcast message includes the length of the ID segment.

6. A method according to claim 1, wherein the hub unit detects a collision when two or more satellite units have IDs that include the same ID segment at the same location and both satellite units will return their full IDs over the shared communication link.

7. A method according to claim 6, wherein the hub unit detects a collision location as the bit number in the returned IDs at which the collision has occurred and, on its next iteration of sending the broadcast message, the hub unit changes the ID segment location to the collision location.

8. A CMOS circuit for use in generating an on-chip ID, the circuit comprising: a bit ID-generation block including a pair of sub-cells, each sub-cell having an output node and an input; wherein the sub-cells are configured such that following antenna-effect damage to one of the sub-cells during fabrication, application of a supply voltage to the inputs will result in a voltage differential between the output nodes of the pair of sub-cells; the bit ID-generation block further comprising a comparator connected to the output nodes of the pair of sub-cells and configured to output a bit ID value based on the differential voltage between the output nodes of the sub-cells.

9. A CMOS circuit according to claim 8, wherein the comparator is configured so that its output is either equal to the supply voltage, interpreted as a bit value of 1, or is zero volts, interpreted as a bit value of 0.

10. A CMOS circuit according to claim 8, comprising a plurality (M) of bit ID-generation blocks to generate an on-chip ID having M bits, each bit ID-generation block including a pair of sub-cells, each sub-cell having an output node and an input; wherein for each bit ID-generation block the pair of sub-cells are configured such that following antenna-effect damage to one of the sub-cells during fabrication, application of a supply voltage to the inputs will result in a voltage differential between the output nodes of the pair of sub-cells; each bit ID-generation block further comprising a comparator connected to the output nodes of the pair of sub-cells and configured to output a bit ID value based on the differential voltage between the output nodes of the sub-cells.

11. A CMOS circuit according to claim 8, wherein each sub-cell of the pair of sub-cells in the or each bit ID-generation block comprises: an NMOS transistor and a PMOS transistor, with the source and drain of the NMOS transistor being connected together and to the drain of the PMOS transistor; the gate of the NMOS transistor being connected to the gate of the NMOS transistor of the other sub-cell of the pair and connected to ground; the gate and drain of the PMOS transistor being connected to the sub-cell input; and the sub-cell output node being on the connection between the PMOS transistor drain and the NMOS transistor source.

12. A CMOS circuit according to claim 11, wherein the damage to the sub-cell is damage to its NMOS gate.

13. A CMOS circuit according to claim 8, wherein for each sub-cell there is a switch between the output node and the comparator by which the comparator can be disconnected from the sub-cells.

14. An implantable system comprising a plurality of implantable devices, each implantable device including a CMOS chip having a CMOS circuit according to claim 8.

15. An implantable system according to claim 14, comprising a control unit and a shared communication link over which the control unit can communicate with the plurality of implantable devices.

16. An implantable system according to claim 15, wherein the control unit is configured to send messages to the plurality of implantable devices over the shared communication link and to address each message to a specific implantable device using the on-chip ID of said specific implantable device.

17. A method according to claim 1, wherein each satellite unit comprises a CMOS chip having a CMOS circuit for generating the satellite unit ID, the CMOS circuit comprising: a bit ID-generation block including a pair of sub-cells, each sub-cell having an output node and an input; wherein the sub-cells are configured such that following antenna-effect damage to one of the sub-cells during fabrication, application of a supply voltage to the inputs will result in a voltage differential between the output nodes of the pair of sub-cells; the bit ID-generation block further comprising a comparator connected to the output nodes of the pair of sub-cells and configured to output a bit ID value based on the differential voltage between the output nodes of the sub-cells.

18. A method according to claim 1, wherein the hub unit assigns a unique secondary ID to each satellite unit, each unique secondary ID having a shorter bit length than the satellite unit ID of the respective satellite unit.

19. A method according to claim 1, wherein a specific length ID portion of each satellite unit ID at a specific location in the IDs is used as a secondary ID for each satellite unit, and/or wherein each satellite unit is allocated a unique time-frame or a unique frequency for transmission over the shared link, the unique time-frame or frequency being derived from the satellite unit ID for each satellite unit or from a secondary ID assigned to each satellite unit.

20. (canceled)

21. A method for transmitting messages from each of a plurality of satellite units to a hub unit over a shared communication link, each satellite unit having a unique ID and being assigned a unique time-frame in which to transmit messages to the hub unit over the shared communication link or a unique frequency for message transmission over the shared communication link, the unique time-frame or frequency being derived from the satellite unit's unique ID.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

[0047] FIG. 1 schematically illustrates an implantable neural prosthesis system that employs ID-generation blocks in accordance with an embodiment of the present invention;

[0048] FIG. 2 shows an exemplary command for ID discovery and corresponding comparison with an ID; and

[0049] FIG. 3 shows an exemplary ID interrogation algorithm used for ID discovery.

DETAILED DESCRIPTION AND FURTHER OPTIONAL FEATURES OF THE INVENTION

[0050] The invention is exemplified with reference to an implantable neural prosthesis, shown in FIG. 1, consisting of N+1 active implanted devices. There is a single Chest Implant (CIM) and N identical Brain Implants (BIM) connected together through a shared wired or wireless communication channel. Each BIM includes an integrated circuit (IC) fabricated in standard CMOS technology.

[0051] To enable full-duplex communication between the CIM and multiple BIM's (through the shared communication channel), the BIM's need to be individually addressable by the CIM. Moreover, each BIM should access the channel in a pre-determined time or frequency frame to avoid data collision. The corresponding channel access methods are known as Time-Domain-Multiple-Access (TDMA) and Frequency-Domain-Multiple-Access (FDMA), respectively. To determine the time (or frequency) frame for each of these identical BIM's, it is essential to provide a unique identification code (ID) for each BIM. Once the BIM's are made individually addressable, the channel-access-time (or frequency) window can be selected individually, by the CIM. Alternatively, the ID can be used by the BIM alone to directly determine the time (frequency) frame.

[0052] A random, permanent ID is generated in this example by exploiting a well-known failure mechanism in CMOS fabrication called process plasma-induced damage, more commonly known as the antenna-effect, as discussed above.

[0053] The proposed circuit to generate a random-bit based on the antenna effect is shown in the box at the right-hand side of FIG. 1 (right). Here, each cell includes two identical sub-cells with NMOS (M1, M2) and PMOS transistors (M3,M4). To ensure the gate-breakdown happens, the peripheral area of the extended-gate-metal of M1 (also connected to M3) is maximised. Moreover, to ensure good randomness, the gates of M1 and M2 are connected together using all metal and polysilicon layers using a perfectly symmetrical design. Therefore, if for example the gate of M1 breaks down, both gates M1 and M2 are discharged and this in turn reduces the electrical field across the gate oxide of M2 to below E.sub.th so that M2 does not break down. If the layout of both gates is perfectly symmetrical, the probability of breaking one or the other gate is 50%.

[0054] All polysilicon and metal layers except the top metal layer are used extend the side-area of M1 (and M3) gate, to maximise the charge pick-up and antenna-effect. The top metal layer is used to connect the gate to ground. The drain and source terminals of the NMOS are connected together and to the drain of a PMOS. The gate and source of the PMOS are tied-up to charge up the drain/source of M1 with a small leakage current.

[0055] In the case of a full-breakage in the gate of M1, its source (and drain of M3) is short-circuited to ground and the gate of M2 charges up to VDD. However, in non-extreme cases, the damage to the gate only leads to gate oxide degradation resulting in a reduced impedance in the gate of M1 (with respect to M2) and a resistive path through its gate-oxide (i.e. it becomes leaky). This leads to a voltage-division between the output resistance of M3 and the gate-oxide resistance of M1 resulting in a smaller voltage at node N1 than at N2.

[0056] Conversely, in the case where M2 is damaged (i.e. M2 becomes leaky) there will be a higher voltage at node N1 than at N2.

[0057] In this example, the differential voltage between N1 and N2 is amplified through a comparator (for example, a fully differential cross-coupled comparator as shown in FIG. 1).

[0058] During start-up, the voltages of the two nodes charge-up slowly through the leakage current provided by the PMOS transistors. This induces large transient currents in the comparator. In this example, to minimise start-up current (surge), switches S1 and S2 are placed between nodes N1, N2 and the comparator. The switches are open at start-up and can then be closed shortly after (e.g. a few milliseconds after) start-up. Each switch may, for example, be an NMOS transistor that can have open and close states based on the application of a low (e.g. 0V) or high (e.g. source voltage) voltage applied to its gate.

[0059] ID Size Determination

[0060] An M-bit ID generation block can be embedded within each BIM to provide a random ID for each BIM. The ID size (M) should be as large as possible to reduce the probability of having two identical IDs generated for two BIMs across a total of M BIMs. However, N should be minimized to save area and dynamic power consumption of the BIM. Here we calculate the probability (P.sub.eq) of having the ID of two BIM's equal. The calculations are because each bit is generated completely randomly and independently from all the other bits and the probability of an ID bit being zero or one is exactly equal.

P.sub.eq=(M1) 1/2.sup.N+(M2) 1/2.sup.N+(M3) 1/2.sup.N+ . . . +(M3) 1/2.sup.N=M(M1) 1/2.sup.(N+1)

[0061] The minimum number of bits in the ID that leads to two equal IDs on two or more different BIM's (among N total BIM's) with a probability of less than is:

M(M1) 1/2.sup.(N+1)>.fwdarw.M>(In(M(M1))In())/In(2)1

where can be made arbitrarily small. For example to ensure that the probability of two BIMs (out of 100) end up with identical IDs is less than 10.sup.8, an ID block with 39-bits is required.

[0062] ID Readout Method

[0063] To enable the CIM to address the individual BIM's, as well as determining the unique IDs for each BIM, the CIM needs to read and register all IDs in its memory prior to any communication. An ID readout phase is thus required during which all the IDs are scanned and read out, traditionally using an external reader and then saved to non-volatile memory (NVM) of the CIM. This method requires time and extra cost as it consists of an extra readout-step before assembly and implantation of the system.

[0064] Here we propose a method for the CIM to read the ID of each BIM through the shared communication channel after assembly and/or implantation. This is based on a polling method that implements a search algorithm with the CIM guessing a portion of the ID and requesting the BIMs to respond only if it has successfully guessed a part of its ID.

[0065] The CIM includes: (i) non-volatile memory to register IDs of all the optrodes; and (ii) data collision detection.

[0066] The steps for ID-readout are as follows: [0067] (i) CIM issues a command: give ID (A,n,i)to all the BIMs. [0068] (ii) If a BIM successfully matches the received pattern (A,n,i) to its ID, it will respond by sending its full ID. [0069] (iii) The CIM changes the (A,n i) pattern until it receives the IDs from all the BIMs. [0070] (iv) If a collision occurs at bit C, the CIM changes (A,n,i) accordingly.
where A, n and i are the bit-pattern, the number of bits in the bit-pattern and the location of the bit-pattern in the M-bit ID (See FIG. 2). For example, the following command: give ID (0101, 4, 12) asks all the BIMs to search for the 4-bit pattern 0101 at position/bit 12 in its ID, and then reply with its full ID if the pattern matches.

[0071] If two (or more) BIMs happen to find (A,n,i), they will both reply with their ID to the CIM. In this case they either have the exact same ID (which is highly unlikely if N is chosen to be relatively large), or they are different in one or more bits, at which a collision happens which can be detected at the CIM.

[0072] A corresponding lightweight ID declaration algorithm is embedded within each BIM. The ID declaration on the optrode simply checks for (A,n,i) in its ID and responds only if it finds a match. If it matches it responses with its full ID. The BIM therefore includes a circuit block for comparison and respond.

[0073] An example of the ID-readout algorithm is shown in FIG. 3.

[0074] Dynamic-ID Allocation

[0075] As discussed previously, a time (or frequency) frame needs to be allocated for each BIM to share the communication channel. This time frame for a system of 16 BIMs can be implemented using a minimum of 4-bits. This 4-bit frame-identifier is called dynamic ID (DID), and is determined by the CIM and saved in both the BIM and CIM. This number can then be used to address the individual BIM's instead of requiring the long, full M-bit ID. The CIM allocates the DIDs to each BIM after all the IDs are determined.

[0076] Adopting this approach, the number of data-bits transmitted can be kept to a minimum. Preferably, all of the time-frames in the TDMA communication are occupied to achieve maximum data-rate.

[0077] Secondary Static-ID (SSID) Allocation

[0078] An alternative to DID is that CIM extracts an L-bit secondary-static ID (SSID) from the M-bit ID of the BIMs and uses this smaller ID to address the BIMs across the shared communication channel. For example, if all BIMs have and ID in which the first 5-bits are different, a secondary static ID with only 5-bits can be used to address all of them.

[0079] The advantage of using the SSID over the dynamic ID is if the system or any of the BIM's loses power and restarts, then the IDs will not be forgotten. By saving the SSID location and number of bits in NVM within the CIM, after start-up with a single command all the SSIDs can be established. Whereas for the DID-allocation after each start-up the number of required commands to re-stablish communication is equal to the number of BIMs.

[0080] The minimum number of bits needed for the SSID is determined by the number of BIMs. For example, if there are 16 BIMs, only 4 bits are required for the SSID, whereas for a system having 32 BIMs, 5 bits are required. More generally, for a system with N BIMs, the number of bits required for the SSID is log.sub.2(N).

[0081] Thus, ff a log.sub.2(N)-bit SSID is found (e.g. using an appropriate algorithm on the IDs for all of the BIMs), the DID allocation phase can be bypassed, and the SSID can be used directly to determine the time-frame (or frequency) for each BIM.

[0082] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

[0083] All references referred to above are hereby incorporated by reference.