WAFER STENCIL FOR CONTROLLING DIE ATTACH MATERIAL THICKNESS ON DIE

Abstract

A method of applying a die attach material includes forming a wafer stencil by selectively removing on the back side of a wafer including a plurality of semiconductor die having an active top side a predetermined depth to form a recess having an inner circumference while not removing an outer most circumference of the wafer. The recess is filled with a B-stage adhesive material. The wafer is singulated to form a plurality singulated semiconductor die. The singulated semiconductor die is die attached back side down to a package substrate, and then the B-stage adhesive material is cured. The B-stage adhesive material across its full area generally has a minimum thickness of at least 20 m and a maximum thickness range of 6 m.

Claims

1. A method, comprising: forming a wafer stencil by selectively removing on the back side of a wafer comprising a plurality of semiconductor die having an active top side a predetermined depth to form a recess having an inner circumference while not removing an outer most circumference of the wafer; filling the recess with a B-stage adhesive material; singulating the wafer to form a plurality singulated semiconductor die; die attaching the singulated semiconductor die back side down to a package substrate, and curing the B-stage adhesive material.

2. The method of claim 1, wherein the selectively removing comprises back grinding.

3. The method of claim 1, wherein the predetermined depth is 20 m to 60 m.

4. The method of claim 1, wherein the raised ring is 1 mm to 5 mm wide.

5. The method of claim 1, further comprising a partial curing of the B-stage adhesive material before the singulating.

6. The method of claim 1, further comprising a full curing of the B-stage adhesive material before the singulating, and again filling the recess with a second layer of B-stage adhesive material before the singulating.

7. The method of claim 1, wherein the package substrate comprises small outline transistor (SOT) package.

8. The method of claim 1, wherein the package substrate comprises a lead frame.

9. The method of claim 7, wherein the lead frame comprises a Quad Flat No-Lead (QFN) lead frame.

10. The method of claim 1, wherein the B-stage adhesive material after the curing across its full area has a minimum thickness of at least 20 m and a maximum thickness range of 6 m.

11. A semiconductor die, comprising: a substrate having an active top side and a back side surface; a B-stage adhesive material across an area of the back side surface, wherein the B-stage adhesive material across the area has a minimum thickness of at least 20 m and a maximum thickness range of 6 m.

12. The semiconductor die of claim 11, wherein the maximum thickness range is 4 m.

13. The semiconductor die of claim 11, wherein the B-stage adhesive material comprises an epoxy.

14. The semiconductor die of claim 11, wherein the B-stage adhesive material comprises a top B-stage adhesive layer on a bottom B-stage adhesive layer.

15. A packaged semiconductor device, comprising: a semiconductor die, comprising: a substrate having an active top side and a back side surface; a dielectric material comprising a B-stage adhesive material across an area of the back side surface, wherein the B-stage adhesive material across its full area has a minimum thickness of at least 20 m and a maximum thickness range of 60 m, and a package substrate, wherein the semiconductor die is attached back side down on the package substrate.

16. The packaged semiconductor device of claim 15, wherein the thickness of the B-stage adhesive material is 20 m to 60 m.

17. The packaged semiconductor device of claim 15, wherein the package substrate comprises small outline transistor (SOT) package.

18. The packaged semiconductor device of claim 15, wherein the package substrate comprises a lead frame.

19. The packaged semiconductor device of claim 15, wherein the lead frame comprises a Quad Flat No-Lead (QFN) lead frame.

20. The packaged semiconductor device of claim 19, wherein the packaged semiconductor device comprises a Chip on Lead (COL) assembly.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0011] FIGS. 1A-E show successive cross sectional views corresponding to steps in an example method of applying a B-stage die attach material to the back side of a wafer using a disclosed wafer stencil for controlling the die attach thickness, according to an example aspect.

[0012] FIG. 2 is a diagram illustrating a cross-section view of a COL QFN packaged semiconductor device that includes a semiconductor die that had the B-stage adhesive die attach in the package formed by a disclosed wafer stencil for controlling the die attach thickness on the back side of the semiconductor die, where the semiconductor die is attached to lead fingers.

[0013] FIG. 3 is a diagram illustrating a cross-section view of a QFN packaged semiconductor device that includes a die pad that includes a semiconductor die that had the B-stage adhesive die attach material in the package formed by a disclosed wafer stencil for controlling the die attach thickness on the back side of the semiconductor die, where the semiconductor die is attached the die pad.

[0014] FIG. 4 is a cross section diagram of an SOT QFN packaged semiconductor device that includes a die pad package and a semiconductor die that had the B-stage adhesive die attach material in the package formed by a disclosed wafer stencil for controlling the die attach thickness on the back side of the semiconductor die.

DETAILED DESCRIPTION

[0015] Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure.

[0016] FIGS. 1A-E show successive cross sectional views corresponding to steps in an example single-layer method 100 for applying a B-stage adhesive die attach material to the back side of a wafer using a disclosed wafer stencil for controlling the die attach thickness, according to an example aspect. Step 101 comprises forming a wafer stencil 150 by selectively removing wafer material on the back side of a wafer 150 that includes a plurality of semiconductor die having an active top side 110a a predetermined depth to form a recess 110b.sub.1 having an inner circumference while not removing an outer most circumference 110b.sub.2 of the wafer which has the appearance of a raised ring. FIG. 1A shows the results after step 101 where the wafer stencil 150 comprising a wafer 110 with a plurality of semiconductor die (individual die not shown, which typically comprise hundreds or thousands of die separated by scribe lines) having an active top side 110a is shown after selectively removing material from a back side of the wafer 110 to form the recess 110b.sub.1. The wafer 110 can be previously conventionally back ground to about 200 m, or can be at its original thickness of about 25 mils (635 m). The semiconductor die can be IC die, or a discrete die such as a power diode, power transistor, or a trench capacitor.

[0017] The outer most circumference 110b.sub.2 can be approximately 1 to 5 mm wide ring, typically 2 to 3 mm corresponding to the edge exclusion zone of the wafer 110. The selectively removing can comprise back grinding, lasering, or dry etching (e.g., reactive ion etching (RIE)) or wet etching, with the etch processing generally utilizing an etch mask to enabling selectively etching. The predetermined depth is set by the depth of the inner recess 110b.sub.1 that has a depth designed for a later B-stage adhesive layer addition within the recess.

[0018] Step 102 comprises filing the inner recess 110b.sub.1 of the wafer stencil 150 with a B-stage adhesive material. FIG. 1B shows the wafer stencil shown in FIG. 1A now on a vacuum chuck or adhesive tape 120 after the step 102 filling of the inner recess 110b.sub.1 with a B-stage adhesive material 115, then shaving the B-stage adhesive material 115 with a shaver 125 (or squeegee), shown almost finished cutting the B-stage adhesive material to set the thickness of the B-stage adhesive material as shown to the level of the top surface of the outer most circumference 110b.sub.2. By leaving a disclosed outer most circumference 110b.sub.2 on the outer circumference of the wafer 110, wafer warpage is lowered, wafer strength is improved, and the ease of wafer handling is improved. Moreover, the outer most circumference 110b.sub.2 on the outer circumference of the wafer 110 that provides added mechanical support improves the ease of processing after wafer thinning including dicing tape attach, and back side coating.

[0019] Some high performance epoxies are formulated as B-stage systems. As known in polymer chemistry, a B-stage epoxy is a polymer-based system wherein the first reaction between the resin and the curing agent/hardener is purposely not completed. Due to this, the polymer system is in a partially cured stage. When this polymer system is then reheated at elevated temperatures, the polymer cross-linking is completed and the system fully cures.

[0020] The B-stage adhesive material 115 comprises a material with good adhesive properties (i.e., is sticky) when it is set but not fully cured (e.g., the first stage), so that it can securely hold a wafer during wafer handling operations and die attachment is thus facilitated. Generally, the B-stage adhesive material 115 should be compatible with both the wafer 110 and the support structure that the singulated dice are intended to be mounted on. By way of example, there are a number of B-stage epoxy compositions that are compatible with and adhere well to the back surface of semiconductor wafers and commonly used support structures that can be used with disclosed aspects.

[0021] FIG. 1C shows the wafer 110 after shaving is completed and after partially curing the B-stage adhesive material which is now shown as 115. Although no adhesive shrinkage is shown in FIG. 1C due to the partial curing, there is generally some shrinkage due to the cross-linking involved.The filling of the B-stage adhesive can be to a height that is set so that after the partial cure the known material shrinkage % results in the partially cured B-stage adhesive material 115 being essentially planar, generally within 1 m, relative to the top surface of the outer most circumference 110b.sub.2.

[0022] FIG. 1D shows the wafer 110 now attached back side down on a dicing tape 130 with the blade 132 of a mechanical saw shown beginning the singulation process. However, laser singulation may also be used. In step 103 the wafer is singulated to form a plurality singulated semiconductor die. FIG. 1E shows the wafer 110 after step 103 being fully singulated with the semiconductor die shown as 210 separated having their own partially cured B-stage adhesive material 115. After die attach of the back side of the semiconductor die down to a package substrate, the B-stage adhesive material 115 is then fully cured using a curing process with a higher temperature and generally as longer time as compared to the partial curing process. There is also a small amount of adhesive shrinkage at final cure. The B-stage adhesive material after die attach across its full area has a minimum thickness of at least 20 m and a maximum thickness range of 3 m (6 m), such as 2 m (4 m). The thickness of the fully cured B-stage adhesive material is typically 20 m to 60 m, but can be as thick as nearly the wafer thickness, such as up to about 600 m.

[0023] As known in the art, subsequent processing includes die picking and placing the singulated die on a package substrate, then die attaching the die to the package substrate. The package substrate can comprise a lead frame, a printed circuit board (PCB), another semiconductor die, or generally any other package substrate.

[0024] The process flow can comprise a single B-stage epoxy layer as described above or a double-layer B-stage adhesive process. Plasma processing generally proceeds epoxy printing in either case. In the double-layer process the first B-stage epoxy layer is fully cured and this layer adheres to the back side of the wafer, and there is a second B-stage epoxy layer applied on top of the cured first B-stage epoxy layer which is then partially cured, followed by wafer singulation, die attach to a package substrate, and then fully curing the second B-stage epoxy layer.

[0025] FIG. 2 is a diagram illustrating a cross-section view of a COL QFN packaged semiconductor device (QFN package) 200, wherein QFN package 200 includes a semiconductor die 210 that had the fully cured B-stage adhesive material shown as 215 in the package formed by a disclosed wafer stencil for controlling the die attach thickness on the back side of the semiconductor die 210 attached to lead fingers shown as 205a and 205b. The semiconductor die 210 can comprise an IC die, and the active surface 210a includes functional circuitry comprising circuit elements (including transistors, and generally diodes, resistors, capacitors, etc.) formed therein for generally realizing at least circuit function, and an inactive back side surface (inactive surface) 210b. Example circuit functions include analog (e.g., amplifier or power converter), radio frequency (RF), digital, or non-volatile memory functions. The semiconductor die 210 also includes an inactive surface 210b having cured B-stage adhesive material 215 thereon which is utilized to attach the inactive surface 210b of the semiconductor die 210 to the lead fingers shown as 205a and 205b.

[0026] Furthermore, on the active surface 210a there is a plurality of bond pads shown as 218a, 218b located at a perimeter of active surface 210a, wherein the bond pad(s) 218a, 218b enable the semiconductor die 210 to be coupled to leads 205a, 205b by one or more wire bonds 234. The semiconductor die 210 may be formed of, for example, silicon, silicon dioxide, germanium, gallium arsenide, and/or similar material(s), and may be, for example, a complementary metal-oxide semiconductor (CMOS) chip, a micro-electro-mechanical (MEMS) chip, or a similar semiconductor chip.

[0027] Wire bonds 234 are typically formed of an electrically conductive material such as copper, gold, silver, platinum, or similar conductive material. Once the semiconductor die 210 is attached to the lead fingers shown as 205a and 205b and wire bonds 234 are added, these components are molded together utilizing mold material 240. Mold material 240 is typically a plastic or similar non-electrically conductive material, and is utilized to protect the semiconductor die 210, the lead fingers 205a and 205b, and the wire bonds 234.

[0028] FIG. 3 is a diagram illustrating a cross-section view of a QFN packaged semiconductor device (QFN package) 300 that includes a die pad 315, wherein QFN package 300 includes a semiconductor die 210 having a die pad 315 that includes a semiconductor die that had the cured B-stage adhesive material 215 in the package formed by a disclosed wafer stencil for controlling the die attach thickness on the back side of the semiconductor die attached to the die pad 315. The die pad 315 is typically formed from a conductive material (e.g., a metal) and includes a mold lock utilized to attach the die pad 315 to a mold material 240.

[0029] A SOT package is known to be a very small, inexpensive surface-mount plastic-molded packages with leads on their two long sides commonly used for mainly discrete components and simple IC's. FIG. 4 is a cross section diagram of a SOT packaged semiconductor device package (SOT package) 400 that includes a semiconductor die 210 that had the cured B-stage adhesive material 215 in the package formed by a disclosed wafer stencil for controlling the die attach thickness on the back side of the semiconductor die 210. The semiconductor die 210 is affixed to a die attach pad 414 using a disclosed cured B-stage adhesive material 215. The die attach pad 414 is part of a lead frame that includes a plurality of leads 418a, 418b.

[0030] In the example shown, lead 418a is connected to the die attach pad 414, whereas the other lead 418b is connected to a bond pad (not visible) on the top or active surface of the die 210 using a bond wire 234. The entire package 400, including the die 210, die attach pad 414, wire bonds 234, and the non-external portions of the leads 418a, 418b, are encapsulated in the mold material 240. Although only two leads 418a and 418b are shown in the cross section, it should be noted that a typical SOT package will have additional leads. For example, a typical Small Outline Package (SOP) package may have several signal leads, input and output leads as well as ground and power supply leads. One lead, here shown as 418a, is used as a ground lead that is directly coupled to the die attach pad 414. By grounding the die attach pad 414, the non-active surface 210b of the die 210 is also grounded, which is improves the electrical operation of the circuitry on the semiconductor die 210.

[0031] As noted above, disclosed wafer stencils control the thickness of the die attach B-stage process. This technique eliminates the conventional need to have different stencil thicknesses for each package requirement, and improves wafer warpage issue particularly for very thin wafers during B-stage application and after die attach cure for large wafer diameters, such as having a 300 mm size.

[0032] Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor packages and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

[0033] Those skilled in the art to which this Disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this Disclosure.