SEMICONDUCTOR DEVICE AND ESD PROTECTION DEVICE COMPRISING THE SAME

Abstract

A silicon chip package structure, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacture is provided. The disclosure provides improvements to a Chip Silicon Package (CSP) structure by reducing the active area needed to be sacrificed to create a drain area.

Claims

1. A silicon chip package structure, the silicon chip package structure comprising: a silicon substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a silicon body silicon body having a first body surface side and a second body surface side opposite to the first body surface side, and provided with its second body surface side to the first substrate surface side of the silicon substrate, the silicon body comprising an epitaxial layer at its second body surface side configured as a channel and a body well layer at its first body surface side configured as a drift region; at least one drain, at least one source and at least one gate, wherein the source and the drain are provided at the first body surface side of the silicon body and the gate is formed as a trench positioned between the source and the drain and extending from the first body surface side of the silicon body through the body well layer into the epitaxial layer, the gate trench being insulated from the body well layer with a local oxidation of silicon (LOCOS) layer and the epitaxial layer with a gate oxidation layer, wherein the gate trench is formed of two stacked gate trench segments isolated from each other by means of a LOCOS layer, each stacked gate trench segment being electronically connected to a respective gate terminal.

2. The silicon chip package structure according to claim 1, further comprising at least n drain terminals and at least n source terminals alternately positioned relative to each other, thereby forming at least n sets of pairs of one drain and one source and at least n stacked gate trenches, each stacked gate trench positioned between alternating drains and sources, with n being 2 or more.

3. The silicon chip package structure according to claim 1, wherein, seen in a direction parallel to a longitudinal orientation of the gate trench, the gate terminal of one stacked gate trench segment extends at a further distance from the gate trench compared to the gate terminal of the other stacked gate trench segment.

4. The silicon chip package structure according to claim 1, further comprising at least a layer of isolating material comprising a conductive material circuit pattern comprising circuit section connected to the trench gate, the source and the drain.

5. The silicon chip package structure according to claim 1, wherein the second side of the silicon substrate is connected to ground potential.

6. The silicon chip package structure according to claim 1, wherein the gate is made from a polysilicon material.

7. The silicon chip package structure according to claim 1, wherein the gate oxidation layer insulating the stacked gate trench segment closest to the first body surface side of the silicon body has a thickness that is thicker than a thickness of the gate oxidation layer insulating the other stacked gate trench segment furthest to the first body surface side of the silicon body.

8. The silicon chip package structure according to claim 2, wherein, seen in a direction parallel to a longitudinal orientation of the gate trench, the gate terminal of one stacked gate trench segment extends at a further distance from the gate trench compared to the gate terminal of the other stacked gate trench segment.

9. The silicon chip package structure according to claim 2, further comprising at least a layer of isolating material comprising a conductive material circuit pattern comprising circuit section connected to the trench gate, the source and the drain.

10. The silicon chip package structure according to claim 2, wherein the second side of the silicon substrate is connected to ground potential.

11. The silicon chip package structure according to claim 2, wherein the gate is made from a polysilicon material.

12. The silicon chip package structure according to claim 2, wherein the gate oxidation layer insulating the stacked gate trench segment closest to the first body surface side of the silicon body has a thickness that is thicker than a thickness of the gate oxidation layer insulating the other stacked gate trench segment furthest to the first body surface side of the silicon body.

13. A method of manufacturing a silicon chip package structure in particular a metal-oxide-semiconductor field-effect transistor according to claim 1, the method comprising the steps of: a. providing a silicon substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; b. providing a semiconductor epitaxial layer on the first substrate surface side of the silicon substrate; c. pad oxide forming a SiO2 layer on the epitaxial layer; d. providing a body well layer on the semiconductor epitaxial layer; e. forming of N-well and P-well; f. providing thermal treatment; g. applying hard mask treatment; h. forming a gate trench through etching; i. performing first sacrificial oxidation; j. performing a threshold voltage implementation at the bottom of the trench through the sacrificial oxidation; k. removing sacrificial oxidation and depositing a gate oxidation layer; l. depositing and etching a first polysilicon layer of gate layer in the trench; m. performing local oxidation of silicon process; n. depositing and etching a second polysilicon layer of gate layer in the trench on the first polysilicon layer of gate layer; o. implementing a source, a drain and bulk implants on the first top of the silicon chip package structure; and p. encapsulating thereby forming the silicon chip package structure.

14. The method according to claim 13, wherein borophosphosilicate glass is used for encapsulation.

15. The method according to claim 13, wherein contacts are formulated by metal deposition followed by etching a circuit pattern.

16. The method according to claim 13, wherein the step of encapsulation is repeated at least two times thereby forming a multilayer encapsulation.

17. The method according to claim 13, wherein the contacts in the encapsulation layer are formed by holes filled with conductive material.

18. The method according to claim 14, wherein contacts are formulated by metal deposition followed by etching a circuit pattern.

19. An electronic active element comprising a metal base with a heat sink, a polymer body, at least two electrodes and the silicon chip package structure according to claim 1, wherein the source terminal, the drain terminal and the gate terminal are connected to one of the two electrodes or the metal base accordingly, and wherein the silicon chip package structure is encapsulated in the polymer body with at least a part of the electrodes and metal base being exposed.

20. The silicon chip package structure according to claim 1, wherein the silicon chip package structure is a metal-oxide-semiconductor field-effect transistor (MOSFET)

Description

BRIEF DESCRIPTION OF DRAWINGS

[0036] The disclosure will now be discussed with reference to the drawings, which show in:

[0037] FIG. 1 shows schematic cross section of a CSP product.

[0038] FIG. 2A shows a schematic cross section of a CSP product and depicts a one gate (G) approach.

[0039] FIG. 2B shows a schematic cross section of a CSP product and depicts a split gate (G) approach.

[0040] FIGS. 3A, 3B and 3C show schematic upper views of three possible layout implementations.

[0041] FIGS. 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h, 4i, 4j, 4k, and 4l shows a schematic representation of steps for manufacturing a CSP product according to the disclosure.

[0042] FIG. 5 shows schematic cross sections of a CSP product in different locations.

[0043] FIG. 6 shows schematic cross sections of a multigame CSP product.

[0044] FIG. 7 shows schematic cross sections of CSP product manufacturing steps results.

[0045] FIG. 8 shows schematic upper views of a CSP product in a first example, and a second example.

[0046] FIG. 9 shows schematic upper views of a CSP product in a third example, and a fourth example.

[0047] FIG. 10 shows a schematic upper view of a CSP product in a fifth example.

DETAILED DESCRIPTION

[0048] In certain examples, aspects of the present disclosure relate to a silicon chip package (100) structure in particular to a metal-oxide-semiconductor field-effect transistor (MOSFET). The silicon chip package structure (100) relates to a silicone active electronic element having a multilayer structure, in some embodiments those layers can be formed by different materials or by the same material with different structural characteristics or dopants.

[0049] In some examples, different layers can be formed with the same material having same structure and same dopants (or no dopants at all) but those layers are deposited in fewer steps of the same depositing process (PVD, CVD and others known epitaxial layer (EPI) deposition methods) or using different depositing processes.

[0050] In a particular example (FIG. 1 and FIGS. 2A-2B) the silicon chip package structure (100) comprises a silicon substrate (110) having a first substrate surface side (111) and a second substrate surface side (112) opposite to the first substrate surface side (111). The silicon chip package (100) structure further comprises a silicon body (120) having a first body surface side (121) and a second body surface side (122) opposite to the first body surface side (121), and provided with its second body surface side (122) to the first substrate surface side (111) of the silicon substrate (110), the silicon body (120) comprising an epitaxial layer (EPI) at its second body surface side (122) functioning as a channel and a body well layer at its first body surface side (121) functioning as a drift region. Reference numeral (200) denotes a field oxide layer which is a relatively thick oxide (typically 100-500 nm) formed to passivate and protect the gate from the source and drain regions. This layer (200) is formed during the LOCOS process, and thus also called a LOCOS layer and will be described in more detail with reference to the step performed in FIG. 4i. In FIGS. 2A-2B and 7 reference numeral (210) may denote an ILD layer (or Inter Level Dielectric layer) used to electrically separate or shield closely spaced interconnect lines. Similarly, in the Figures reference numeral (220) denotes a shield oxide layer.

[0051] The second side (112) of the silicon substrate (110) can be connected to ground potential (GND).

[0052] At least one drain (D), at least one source (S) and at least one gate (G) is provided, wherein the source (S) and the drain (D) are provided at the first body surface side (121) of the silicon body (120) and the gate (G) is formed as a trench (130) positioned between the source (S) and the drain (D) and extending from the first body surface side (121) of the silicon body (120) through the body well layer into the epitaxial layer (EPI), the gate (G) trench (130) being insulated from the body well layer with a LOCOS layer (200) and the epitaxial layer (EPI) with a gate (G) oxidation layer (GOX). See FIG. 2A for a cross section of the example outlined above, as well as FIGS. 3A and 3C.

[0053] FIG. 2B discloses another example according to the disclosure, wherein the gate (G) trench (130) is formed of two stacked gate (G) trench segments (Poli1, Poli2) isolated from each other by means of a LOCOS layer. Each stacked gate (G) trench (130) segment can be electronically connected to a respective gate (G) terminal (141, 142). See also FIG. 3B.

[0054] The silicon chip package (100) preferably comprises at least n drain (D) terminals (150) and at least n source (S) terminals (160) which are alternately positioned relative to each other. See FIGS. 3A-3C, FIG. 6, FIG. 8-10. Accordingly, these configurations as shown in the Figures form at least n sets of pairs of one drain (D, 150) and one source (S, 160) and at least n stacked gate (G) trenches (130), wherein each stacked gate (G) trench (130) is positioned between alternating drains (D, 150) and sources (S, 160).

[0055] It is noted, that the number n of sets of drain terminals and source terminals is at least two, and preferably 2 or more.

[0056] As shown in the drawings (FIGS. 3, 5, 8-10), the gate (G) terminal (141, 142) of one stacked gate (G) trench (130) segment extends, seen in a direction parallel to a longitudinal orientation of the gate (G) trench (130), at a further distance from the gate (G) trench (130) compared to the gate (G) terminal (141, 142) of the other stacked gate (G) trench (130) segment.

[0057] As depicted in FIGS. 5 and 6, the silicon chip package structure (100) may comprise at least a layer of isolating material (170). The layer of isolating material (170) comprises a conductive material circuit pattern (180) comprising a circuit section which is connected to the trench gate (G), the source (S, 160) and the drain (D, 150).

[0058] Suitable materials of the gate (G) comprises a polysilicon material.

[0059] As clearly shown in FIG. 1, it should be noted that the thickness of the LOCOS layer (200) which is insulating the stacked gate (G) trench (130) segment closest to the first body surface side (121) of the silicon body (120) is thicker than a thickness of the gate (G) oxidation layer (GOX) insulating the other stacked gate (G) trench (130) segment furthest to the first body surface side (121) of the silicon body (120), in fact closer to the second body surface side (122) of the silicon body (120). The gate structure with the thin GOX layer acts as a channel and the gate structure with thicker oxide (LOCOS) acts as a drift to sustain breakdown voltage (BVDSS).

[0060] The method of manufacturing a silicon chip package structure (100) in particular a metal-oxide-semiconductor field-effect transistor (MOSFET) according to the disclosure is depicted in FIGS. 4a-4l, the method comprising the steps of: [0061] a. in FIG. 4a, providing a silicon substrate (110) having a first substrate surface side (111) and a second substrate surface side (112) opposite to the first substrate surface side; [0062] b. in FIG. 4a, providing a semiconductor epitaxial layer (EPI) on the first substrate surface side (111) of the silicon substrate (110); [0063] c. in FIG. 4a, forming a SiO.sub.2 (190) layer on the epitaxial layer (EPI); [0064] d. in FIG. 4a, providing a guard ring on the semiconductor epitaxial layer (EPI); [0065] e. in FIG. 4a, forming of N-well (N) and P-well (P); [0066] f. providing thermal treatment; [0067] g. in FIG. 4b, applying hard mask treatment (HM); [0068] h. in FIG. 4c, forming a gate (G) trench (130) through etching; [0069] i. in FIGS. 4d-4e performing first sacrificial (SAC) oxidation; [0070] j. in FIGS. 4d-4e, performing threshold voltage implementation at the bottom of the trench forming a threshold voltage implementation region (VT IMP) through the sacrificial (SAC) oxidation; [0071] k. in FIGS. 4f-4g, removing sacrificial (SAC) oxidation and growing a gate (G) oxidation layer (GOX); [0072] l. in FIG. 4h, depositing and etching a first polysilicon layer of gate (G) layer (Poli1) in the trench; [0073] m. in FIG. 4i, performing local oxidation of silicon process forming a local oxidation of silicon layer (LOCOS), also denoted as a field oxide layer (200) see FIG. 1; [0074] n. in FIGS. 4j-4k, depositing and etching a second polysilicon layer of gate (G) layer (Poli2) in the trench on the first polysilicon layer of gate (G) layer (Poli1); [0075] o. in FIG. 4l implementing a source (S), a drain (D) and bulk implants on the first surface of the silicon chip package structure (100); [0076] p. finally, encapsulating thereby forming the silicon chip package structure (100).

[0077] In certain examples borophosphosilicate glass can be used for the step of encapsulation.

[0078] The preferred example has electric contacts which are formed by metal deposition followed by the step of etching a circuit pattern. In a preferable example the step of encapsulation is repeated at least two times thereby forming a multilayer encapsulation. Further improved encapsulation can be achieved by repeating the encapsulation step preferably 3 or even 4 times.

[0079] The contacts in the encapsulation layer are formed by holes which may be filled with a conductive material, such as tungsten or any Al compound (Al, AlSi, AlCu, AlSiCu).

[0080] According to an example, the drawings also depict an electronic active element obtained with the method according to the disclosure. The electronic active element comprises a metal base with a heat sink, a polymer body, at least two electrodes and the silicon chip package structure (100) according to the disclosure. As shown in the drawings, the source (S) terminal (160), the drain (D) terminal (150) and the gate (G) terminal (141, 142) are connected to one of the two electrodes or the metal base. The silicon chip package structure (100) is encapsulated in the polymer body with at least a part of the electrodes and metal base being exposed.

[0081] The gate oxide layer (GOX) is the dielectric layer that separates the gate terminal of a MOSFET (metal-oxide-semiconductor field-effect transistor) from the underlying source and drain terminals as well as the conductive channel that connects source and drain when the transistor is turned on. The gate oxide layer (GOX) may be formed by thermal oxidation of the silicon of the channel in order form a thin insulating layer of silicon dioxide (SAC) having a thickness of 5-200 nm. The insulating silicon dioxide layer is formed through a process of self-limiting oxidation. A conductive gate material is subsequently deposited over the gate oxide to form the transistor.

[0082] LOCOS, short for Local Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si—SiO2 interface at a lower point than the rest of the silicon surface. In the process a silicon oxide insulating structure is fabricated as a field oxide layer (200), see FIG. 1, so that the Si—SiO.sub.2 interface occurs at a lower point than the rest of the silicon surface. The oxygen penetrates in depth of the wafer, reacts with silicon and transforms it into silicon oxide.

[0083] Sacrificial (SAC) oxide denotes a semiconductor process flow technique that adds and thereafter removes a sacrificial dielectric layer to smoothen surfaces and/or remove defects from a grown or etched silicon surface.

LIST OF REFERENCE NUMERALS

[0084] 100 silicon chip package structure [0085] 110 silicon substrate [0086] 111 first substrate surface side [0087] 112 second substrate surface side [0088] 120 silicon body [0089] 121 first body surface side [0090] 122 second body surface side [0091] 130 gate trench [0092] 141, 142 gate (G) terminal [0093] 150 drain (D) terminal [0094] 160 source (S) terminal [0095] 170 layer of insulating material [0096] 180 conductive material circuit pattern [0097] 200 field oxide layer [0098] 210 ILD/Inter Level Dielectric layer [0099] 220 shield oxide layer