Thin film transistor substrate including multi-level transparent electrodes having slits

Abstract

Disclosed is a display device having a thin film transistor substrate, which may prevent afterimage and flicker defects by reducing the non-uniformity of an electric field. In the thin film transistor substrate, a pixel electrode includes a transparent edge electrode and a transparent inner electrode, which are spaced apart from each other with a first slit having a first width interposed therebetween, and a common electrode is exposed from the other-side end of the transparent edge electrode by a second width, which is smaller than the first width, in the width direction of a data line. As such, an inner area and an edge area in each sub pixel have uniform electric field distribution.

Claims

1. A display device having a thin film transistor substrate, the thin film transistor substrate comprising: a data line; a transparent upper electrode that is non-overlapping with the data line, the transparent upper electrode including a transparent first electrode, at least two transparent second electrodes and a first slit disposed between the at least two transparent second electrodes, the transparent first electrode closer to the data line than the at least two transparent second electrodes; and a transparent lower electrode including a second slit that overlaps the data line.

2. The display device of claim 1, wherein the transparent lower electrode includes a portion that extends past a side of the transparent first electrode towards the second slit.

3. The display device of claim 2, wherein a width of the portion of the transparent lower electrode that extends past the side of the transparent first electrode is narrower than a width of the first slit.

4. The display device of claim 3, wherein a ratio of the width of the portion to the width of the first slit is in a range from 0.1 to 0.74.

5. The display device of claim 1, wherein the transparent first electrode extends in a direction along the data line.

6. The display device of claim 5, wherein the at least two transparent second electrodes extends in the direction along the data line and is farther away from the data line than the transparent first electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:

(2) FIG. 1 is a sectional view illustrating a conventional thin film transistor substrate;

(3) FIG. 2 is a view illustrating residual DC quantity depending on the difference in the distance between pixel electrodes illustrated in FIG. 1;

(4) FIG. 3 is a view illustrating the dissipation of residual DC component in the thin film transistor substrate illustrated in FIG. 1;

(5) FIG. 4 is a sectional view illustrating a thin film transistor substrate in accordance with a first embodiment of the present invention;

(6) FIG. 5 is a sectional view illustrating the fringe field between pixel electrodes and a common electrode, illustrated in FIG. 4, on a per position basis;

(7) FIG. 6 is a sectional view illustrating a thin film transistor substrate in accordance with a second embodiment of the present invention;

(8) FIG. 7 is a sectional view illustrating the fringe field between pixel electrodes and a common electrode, illustrated in FIG. 6, on a per position basis;

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

(9) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(10) FIG. 4 is a sectional view illustrating a thin film transistor substrate in accordance with a first embodiment of the present invention.

(11) The thin film transistor substrate illustrated in FIG. 4 includes a thin film transistor 130, a pixel electrode 122 connected to the thin film transistor 130, a common electrode 124 for creating the fringe field in a pixel area in cooperation with the pixel electrode 122, and a floating conductive layer 132 overlapping a data line 104.

(12) The thin film transistor 130 is formed at the intersection of a gate line and the data line 104. The thin film transistor 130 charges the pixel electrode 122 with a video signal of the data line 104 in response to a scan signal of the gate line. To this end, the thin film transistor 130 includes a gate electrode 106, a source electrode 108, a drain electrode 110, an active layer 114, and an ohmic contact layer 116.

(13) The gate electrode 106 overlaps a channel of the active layer 114 with a gate insulation layer 112 interposed therebetween. The gate electrode 106 may be a single layer or multiple layers formed on a substrate 101 using any one selected from among molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, without being limited thereto. A gate signal is supplied to the gate electrode 106 through the gate line.

(14) The active layer 114 is formed on the gate insulation layer 112 to overlap the gate electrode 106, thereby forming a channel between the source and drain electrodes 108 and 110. The ohmic contact layer 116 is formed on the area of the active layer 114 excluding the channel in order to realize ohmic contact between each of the source and drain electrodes 108 and 110 and the active layer 114. The active layer 114 and the ohmic contact layer 116 are formed to overlap not only the source and drain electrodes 108 and 110, but also the data line 104.

(15) The source electrode 108 may be a single layer or multiple layers formed on the ohmic contact layer 116 using any one selected from among molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, without being limited thereto. A video signal is supplied to the source electrode 108 through the data line 104.

(16) The drain electrode 110 faces the source electrode 108 with the channel interposed therebetween, and is formed of the same material as the source electrode 108. The drain electrode 110 is exposed through a pixel contact hole 120, which penetrates a first protective layer 118, a planarization layer 128, and a second protective layer 138, thereby being electrically connected to the pixel electrode 122.

(17) The floating conductive layer 132 is disposed above the common electrode 124 to overlap the data line 104. More particularly, the floating conductive layer 132 is formed on the second protective layer 138 in the same plane as the pixel electrode 122 using the same transparent conductive material as the pixel electrode 122. As such, the floating conductive layer 132 and the pixel electrode 122 may be formed at the same time via the same masking process, which may prevent the implementation of an additional masking process and an increase in cost. No electrical signal from an external source is applied to the floating conductive layer 132.

(18) The common electrode 124 is formed in each sub-pixel area and receives a common voltage through a common line. As such, the common electrode 124, to which the common voltage is supplied, creates the fringe field in cooperation with the pixel electrode 122, to which the video signal is supplied through the thin film transistor 130.

(19) The pixel electrode 122 is connected to the drain electrode 110 exposed through the pixel contact hole 120. The pixel electrodes 122 of respective sub-pixels include transparent edge electrodes 122b located close to the data line 104, and transparent inner electrodes 122a located between the transparent edge electrodes 122b. Each of the transparent inner electrodes 122a is spaced apart from the adjacent transparent inner electrode 122a or the adjacent transparent edge electrode 122b with a first slit 122s having a first width w1 interposed therebetween. As illustrated in FIG. 5, the first fringe field FF1 is generated in a first inner area IA1 between one-side end of the transparent inner electrode 122a and the common electrode 124, and the second fringe field FF2, which has a similar potential to that of the first inner area IA1 is generated in a second inner area IA2 between the other-side end of the transparent inner electrode 122a and the common electrode 124. At this time, each first slit 122s has the first width w1 to allow the outermost end point of the first fringe field FF1, generated in the first inner area IA1, and the outermost end point of the second fringe field FF2, generated in the second inner area IA2, to coincide or overlap with each other.

(20) In addition, because the transparent edge electrode 122b is spaced apart from the floating conductive layer 132 by a second width w2, which is smaller than the first width w1, the common electrode 124 is exposed from the other-side end of the transparent edge electrode 122b by the second width w2 in the width direction of the data line 104. Here, the ratio of the second width w2 and the first width w1 is within the range from 0.1 to 0.5. Accordingly, because each of the first and second inner areas IA1 and IA2 and an edge area EA have similar surface-areas, the length of an alignment layer 136 in the edge area EA is similar to that of each of the first and second inner areas IA1 and IA2.

(21) Thereby, because there occurs no difference in the resistance of the alignment layer 136 between the first and second inner areas IA1 and IA2 and the edge area EA, a third fringe field FF3 generated in the edge area EA has potential similar to that of each of the first and second inner areas IA1 and IA2. In this way, the first and second inner areas IA1 and IA2 and the edge area EA have similar residual DC components, and consequently, take the same amount of time to dissipate the residual DC components. That is, the residual DC component in the edge area EA is reduced compared to the related art to be similar to that in each of the first and second inner areas IA1 and IA2, which ensures more rapid dissipation of the residual DC component than in the related art. As a result, the present invention may prevent afterimage and flicker defects attributable to the nonuniformity of the electric field.

(22) FIG. 6 is a sectional view illustrating a thin film transistor substrate in accordance with a second embodiment of the present invention.

(23) The thin film transistor substrate illustrated in FIG. 6 includes the same constituent elements as the thin film transistor substrate illustrated in FIG. 4 except that the floating conductive layer is replaced with the common electrode 124 having a second slit 134 otherwise known as a gap. Thus, a detailed description related to the same constituent elements will be omitted.

(24) The common electrode 124 includes a second slit 134 located in the area overlapping the data line 104. Due to the second slit 134, the common electrode 124 in each sub-pixel area protrudes toward the data line 104 than does the pixel electrode 122. Because the common electrode 124 is exposed from the other-side end of the transparent edge electrode 122b by the second width w2 in the width direction of the data line 104, the other-side end of the common electrode 124 exposed by the second slit 134 is spaced apart from the other-side end of the transparent edge electrode 122b by the second width w2. As such, as illustrated in FIG. 7, the first fringe field 1-1-1 is generated in the first inner area IA1 between one-side end of the transparent edge electrode 122b or the one-side end of the transparent inner electrode 122a, and the common electrode 124. The second fringe field FF2 is generated in the second inner area IA2 between other-side end of the transparent inner electrode 122a, and the common electrode 124. And, the third fringe field 1-1-3, which has a similar potential to that of each of the first and second inner areas IA1 and IA2, is generated in the edge area EA between the other-side end of the transparent edge electrode 122b and the common electrode 124.

(25) At this time, the ratio of the second width w2 of the first slit 122s and the first width w1 of the common electrode 124 is set so that the residual DC component of the inner area IA and the residual DC component of the edge area EA, are similar to each other. For example, the second width w2 of the common electrode 124, which protrudes beyond the transparent edge electrode 122b, is smaller than the first width w1 of the first slit 122s, and the ratio of the second width w2 of the first slit 122s and the first width w1 of the common electrode 124 is within the range from 0.1 to 0.74. So long as this ratio is satisfied, the residual DC quantity of the inner areas IA1 and IA2 and the residual DC quantity of the edge area EA are similar to each other. That is, when the ratio of the second width w2 of the first slit 122s and the first width w1 of the common electrode 124 is within the range from 0.1 to 0.74, it can be appreciated as shown in table 1 that the inner areas IA1 and IA2 and the edge area EA have similar residual DC component, causing uniform distribution of the electric field in the inner areas IA1 and IA2 and the edge area EA. On the other hand, when the ratio exceeds 0.74, it can be appreciated as shown in table 1 that the residual DC component of the edge area EA becomes greater than the residual DC component of the inner areas IA1 and IA2, causing non-uniform distribution of the electric field in the inner areas IA1 and IA2 and the edge area EA.

(26) TABLE-US-00001 TABLE 1 The ratio of The residual The residual DC the second width w2 and DC quantity quantity of the first width w1 of the inner area the edge area 0.64 2.39 2.35 0.74 2.42 0.85 2.46 1.00 2.50 1.17 5.53

(27) As described above, because the first and second inner areas IA1 and IA2 and the edge area EA have similar electric field distributions in the second embodiment of the present invention, the first and second inner areas IA1 and IA2 and the edge area EA have the same residual DC component, and thus take the same amount of time to dissipate the residual DC component. That is, the residual DC component of the edge area EA is reduced compared to the related art to be similar to that of each of the first and second inner areas IA1 and IA2, which ensures more rapid dissipation of the residual DC component than in the related art. As a result, an embodiment of the present invention may prevent afterimage and flicker defects attributable to the non-uniformity of the electric field.

(28) Meanwhile, although an embodiment of the present invention describes the configuration in which the pixel electrode 122 (i.e. a transparent upper electrode) is disposed above the common electrode 124 (i.e. a transparent lower electrode) by way of example, alternatively, the common electrode may be disposed above the pixel electrode. In addition, although an embodiment of the present invention describes the configuration in which the first slit 122s is arranged parallel to the data line 104 by way of example, alternatively, the first slit 122s may be arranged parallel to a gate line. In this case, the transparent edge electrode 122b is located close to the gate line.

(29) As is apparent from the above description, according to an embodiment of the present invention, first and second inner areas and an edge area, which are located in each sub-pixel, have similar electric field distributions. Thereby, according to an embodiment of the present invention, the first and second inner areas and the edge area have the same residual DC component, and take the same amount of time to dissipate the residual DC component, which may prevent afterimage and flicker defects attributable to the nonuniformity of the electric field.

(30) It will be apparent to those skilled in the art that the present invention described above is not limited to the embodiments described above and the accompanying drawings, and various substitutions, modifications, and alterations may be devised within the spirit and scope of the present invention.